KONGUNADU COLLEGE OF ENGINEERING AND TECHNOLOGY

NAMAKKAL- TRICHY MAIN ROAD, THOTTIAM AC-06

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Rev: 0

LESSON PLAN

Faculty Name : S.BASKAR, AP/ECE

Subject Code & Name : EC6601 VLSI DESIGN
Year / Semester : III/VI-A
Degree & Branch : BE/ECE
Lecture Hours

Unit No. of Hrs Allotted as per syllabus No. of Hrs Planned

Unit – I 9 09
Unit – II 9 09
Unit – III 9 09
Unit – IV 9 10
Unit – V 9 09
Total No. of Hrs 45 46

Objectives:
On completion of this course the student will understand
 Introducing the basic concept of MOS transistor principle and analyze the circuit
level design
 Learning the Design concept of static and dynamic CMOS and analyze their
performance.
 Knowing design concept of Sequential logic circuits using latches and registers
 Understanding the design procedure of Arithmetic system and analyzes their
performance.
 Illustrating the Design methodology of digital IC and implement on it full custom and semi custom approach.
Sl. Proposed Proposed Actual Actual Delivery Books
Topic(s) Date Hours Methods Referred
No. Date Hours
UNIT I- MOS TRANSISTOR PRINCIPLE
1 5 NMOS Enhancement transistors PPT R1,R4
17.12.18
2 8 PMOS Enhancement transistors PPT R1,R4
17.12.18
Process parameters for MOS and PPT R1,R4
3 2
18.12.18 CMOS
Electrical properties of CMOS circuits- PPT R1,R4
4 9
19.12.18 Non-Ideal IV characteristics
5 4 Ideal IV characteristics C&T R1,R4
22.12.18
C-V characteristics, DC transfer PPT R1,R4
6 1
23.12.18 characteristics
7 2 Device modeling PPT R1,R4
23.12.18
Sl. Proposed Proposed Actual Actual Delivery Books
Topic(s) Date Hours Methods Referred
No. Date Hours
 KONGUNADU COLLEGE OF ENGINEERING AND TECHNOLOGY
NAMAKKAL- TRICHY MAIN ROAD, THOTTIAM AC-06
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Rev: 0

Scaling principles and fundamental PPT R1,R4

8 3
23.12.18 limits
Propagation delays, Stick diagram, PPT R1,R4
9 5 Layout Diagram, VLSI design testing and
24.12.18 verification
UNIT II- COMBINATIONAL LOGIC CIRCUITS
Examples of Combinational Logic PPT R1,R4
10 8
24.12.18 Design
11 2 Elmore’s constant PPT R1,R4
25.12.18
12 5 Pass transistor Logic PPT R1,R4
29.12.18
13 5 Transmission gates PPT R1,R4
31.12.18
static CMOS design-complementary C&T R1,R4
14 8
31.12.18 CMOS gates
TERMINAL EXAMINATION – I (3.1.2019-9.1.2019)
15 4 static CMOS design-Ratioed logic PPT R1,R4
12.1.19
16 4 Dynamic CMOS design PPT R1,R4
19.1.19
Dynamic CMOS design-cascading PPT R1,R4
17 5
21.1.19 dynamic gates
Power dissipation, Low power design PPT R1,R4
18 8
21.1.19 principles
UNIT III- SEQUENTIAL LOGIC CIRCUITS
Static and Dynamic Latches and PPT R1,R4
19 2
22.1.19 Registers
20 7 Timing issues PPT R1,R4
23.1.19
21 4 Pipelines C&T R1,R4
26.1.19
22 5 clock strategies C&T R1,R4
28.1.19
Memory architecture-N-word, array PPT R1,R4
23 8
28.1.19 structured
Memory architecture- PPT R1,R4
24 2
29.1.19 Hierarchial,content addressable
Special PPT R1,R4
25 memory control circuits
Class
Special PPT R1,R4
26 Low power memory circuits
Class
Special Synchronous design, Asynchronous PPT R1,R4
27
Class design
Sl. Proposed Proposed Actual Actual Delivery Books
Topic(s) Date Hours Methods Referred
No. Date Hours
UNIT IV- DESIGNING ARITHMETIC BUILDING BLOCKS
 KONGUNADU COLLEGE OF ENGINEERING AND TECHNOLOGY
NAMAKKAL- TRICHY MAIN ROAD, THOTTIAM AC-06
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Rev: 0

28 4 Data path circuits PPT R1,R4

2.2.19
29 5 Architectures for ripple carry adders PPT R1,R4
4.2.19
30 8 carry look ahead adders PPT R1,R4
4.2.19
High speed adders-carry bypass PPT R1,R4
31 2
5.2.19 transistor
High speed adders-linear carry, square PPT R1,R4
32 4
9.2.19 root carry –chain adder
33 2 Accumulators C&T R1,R4
12.2.19
Special PPT R1,R4
34 Multipliers
Class
Special C&T R1,R4
35 Dividers
Class
Special PPT R1,R4
36 Barrel shifters, speed and area tradeoff
Class
Special
37 CBS
Class
TERMINAL EXAMINATION – II (13.2.2019-19.2.2019)
38 4 Full custom design PPT T1,R4
23.2.19
39 5 Semi custom design PPT T1,R4
25.2.19
40 8 Standard cell design PPT T1,R4
25.2.19
41 2 Cell libraries PPT T1,R4
26.2.19
Special C&T T1,R4
42 FPGA building block architectures
Class
Special FPGA interconnect routing procedures- C&T T1,R4
43
Class Actel ACT
Special PPT T1,R4
44 Xilinx LCA,EPLD
Class
Special Altera Max 5000 and 7000 PPT T1,R4
45
Class
Special Altera Max 9000, Altera FLEX C&T T1,R4
46
Class

OUTCOMES:
Upon Completion of the course, the students will be able to:

 Students can be able to understand the design concept of MOS transistor principle and
students able to analyze the electrical properties of CMOS circuits.
 KONGUNADU COLLEGE OF ENGINEERING AND TECHNOLOGY
NAMAKKAL- TRICHY MAIN ROAD, THOTTIAM AC-06
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Rev: 0

 . Students can be able to learn the Design procedure of CMOS logic design and measure
the fundamental parameters such as area complexity, power and reliability
 Students can be able to analyze the performance of Sequential logic circuits using
pipeline system
 Students can be able to design Arithmetic building blocks such as adder, multiplier
shifter, divider, memory and datapath, and optimize them.
 Students can be able to design semi customized IC and implement using standard cell
based ASIC, gate arrays and FPGA.
TEXT BOOK:
1. Jan Rabaey, Anantha Chandrakasan, B.Nikolic, “Digital Integrated Circuits:
A Design Perspective”, Second Edition, Prentice Hall of India, 2003.
2. M.J. Smith, “Application Specific Integrated Circuits”, Addisson Wesley, 1997

REFERENCES:
1 N.Weste, K.Eshraghian, “Principles of CMOS VLSI Design”, Second Edition,
Addision Wesley 1993
2. R.Jacob Baker, Harry W.LI., David E.Boyee, “CMOS Circuit Design, Layout and
Simulation”, Prentice Hall of India 2005 3. A.Pucknell, Kamran Eshraghian, “BASIC
VLSI Design”, Third Edition, Prentice Hall of India, 2007.
3. A.Pucknell, Kamran Eshraghian, “BASIC VLSI Design”, Third Edition, Prentice
Hall of India, 2007
4. Dr.R.Uma, “VLSI Design”, New Edition2016-2017,Sri Krishna Hitech Publishing
Company Pvt.Ltd 2017.

Faculty signature Head of the Department

KONGUNADU COLLEGE OF ENGINEERING AND TECHNOLOGY
NAMAKKAL- TRICHY MAIN ROAD, THOTTIAM AC-06
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Rev: 0