Arun Patel

Eliyahu Zamir
ECE1388F - Final Project Report Manuel Saldaña

1. Functional Specification
This project focuses on the full-custom design of a 200MHz 6-bit Flash ADC converter implemented
using the TSMC 0.35µm process technology [1]. It uses separate analog and digital power rails (VDD =
3.3V), and encodes a single-ended analog input between 0V and VDD. A more complete set of
specifications can be found in the datasheet in the Appendix.

2. Chip Design
This section describes the chip in terms of the modular structure shown in the top-level architecture
diagram (Figure 1) in the Appendix. The entire chip layout diagram (Figure 2) is also available in the
Appendix.

2.1 Analog Subsection

The ADC was designed to for a maximum input range between 0V to VDD (3.3V typical). In order to
accommodate this large range, two types of preamplifiers were designed: a PMOS-based preamplifier
for operation between 0-½VDD, and an NMOS-based preamplifier for operation between ½VDD-VDD.
The cascaded gain of the pre-amplifier and the latched comparators (when transparent) was designed to
be higher than 32dB (typ.) to provide sufficient gain margin for 6-bit resolution. A CML-to-CMOS
converter was designed to interface the CML output of the latched comparator with the CMOS-level
encoder. Schematic simulations show that the 62 latched comparators are capable of operating on a
200MHz input signal with 6-bit resolution at a sampling rate of 1.2GSamples/s. In order to meet our
original power dissipation specification, each of the 62 latched comparator branches was designed to
consume no more than 500µA of static current to satisfy power specifications.

To ensure excellent matching between components, the resistors used in the comparator ladder were
surrounded with dummy resistors. The preamplifiers and latched comparators were laid out using inter-
digitated fingers for the same reason. A 50µm separation region was inserted between the latched
comparators and the CML-to-CMOS converters to shield the analog section of the chip from the noise-
inducing digital section. Numerous N-Well diffusion contacts connected to VDD were inserted within
this isolation region to improve the shielding. Figure 3 illustrates the layout of the block.

2.2 Digital Subsection

2.2.1. Priority Encoder
A 64-bit priority encoder based on [2] was used to simplify the conversion of the thermometer-code
output of the latched comparators to binary output, and to improve the overall robustness of the ADC.
This particular design was chosen for its high performance, as well as the ease of layout due to its
regular structure. It utilizes a two-stage pipeline operating on opposite phases of the clock to compute
the final 63-bit encoded result. The design is based on a combination of dynamic and pass-transistor
logic, and must be clocked carefully to avoid erroneous results. The insertion of 63 dynamic latches at
the input of the block was also required to satisfy the monotonicity constraint of the dynamic logic.

Since only one output will be active at a given point in time, this block greatly simplifies the
implementation of the following Priority to Binary conversion block. It also improves robustness in the
case where one of the latched comparators were to fail: the missed code in the thermometer output does
not affect the priority-encoded output for the remainder of the latches. Figure 4 illustrates the layout.

Arun Patel – 994225575 Eliyahu Zamir – 961339780 Manuel Saldaña - 94117139

ECE1388 Final Project Report Dec. 21st, 2004
2.2.2. Priority to Binary Converter
The Priority-to-Binary converter transforms the 63-bit priority encoded output of the previous block into
a 6-bit binary representation using six 32-input dynamic OR gates. This block was designed using
dynamic logic because it interfaces easily with the previous block, and it is simple to implement (32
NMOS transistors in parallel, not series as in CMOS). The latter reason translates into reduced area and
capacitance, and therefore an increase in speed. The gates use a foot transistor to avoid contention
during the precharge phase, and is implemented using 2X transistors since the logical effort of a
dynamic OR gate is independent of the number of inputs. A 6-bit D-type register is used to stabilize the
outputs for an entire clock cycle. Figure 5 shows the layout of this block.

2.3 Clock Management Subsection

The clock management subsystem consists of a set of buffers which generates true and inverted clocks,
and delays the generated clock signals according to the requirements of the analog and digital sub-
blocks. For improved high speed performance, varying sizes of pseudo-NMOS inverters were used
instead of conventional CMOS inverters. The PMOS load elements of each inverter were designed to
have roughly ¼ the drive strength of the NMOS transistor element. Larger buffers were laid out using
smaller transistors connected in parallel to reduce output resistance and conserve area. The layout is
shown in Figure 6.

2.4 Pad Frame

The pad frame was designed using the area-optimized pad and I/O structures supplied by Prof. Genov.
Since analog and digital sections of the chip utilized separate power and ground busses, the pad frame
was broken into two sections. Back-to-back ESD diodes structures were placed between the ground and
supply rails of the two sections to protect the chip in case an ESD pulse were to occur between an analog
and digital pin. Figure 7 illustrates the layout of the pad frame and the pin assignments.

The pad frame was laid out using CMC guidelines with a pad pitch of 150µm. All input and output pads
were surrounded by VDD and ground pads to prevent cross-talk. This also prevents ground bounce by
reducing the overall supply pin inductance, and avoids excessive current flow through a single pin.

3. Division of Labour
Arun Patel
Initial research and simulation of folding quantizer design, research and development of priority encoder
circuit (schematics and layout), top-level architecture design and modeling, chip-level simulation, clock
management design (schematics), global layout, and preparation of reports and presentation slides.

Eliyahu Zamir
Initial research into high-speed comparator design, analog circuit design (schematics and layout of pre-
amplifiers, resistor ladders, latched comparators, biasing networks, and CML-to-CMOS conversion
logic), interfacing and isolation of analog and digital circuitry, pad-frame design (schematics and layout,
including ESD protection), and global layout.

Manuel Saldaña
Market surveys of analog-to-digital topologies, research into dynamic logic design, implementation of
64-to-6-bit binary encoder circuit based on dynamic logic (schematics and layout), implementation of 6-
bit D-type output register (schematics and layout), clock management cell layout, and global layout.

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ECE1388 Final Project Report Dec. 21st, 2004

4. Appendices
4.1 Figures

Figure 1 – Top-Level Architecture Diagram

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ECE1388 Final Project Report Dec. 21st, 2004

Figure 2 – Chip Layout Diagram

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ECE1388 Final Project Report Dec. 21st, 2004

Figure 3 – Analog Subsection Layout

Figure 4 – Priority Encoder Layout

Figure 5 - Priority-to-Binary Converter

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ECE1388 Final Project Report Dec. 21st, 2004

Figure 6 – Clock Management Block Layout

Figure 7 – Pad Frame Layout

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ECE1388 Final Project Report Dec. 21st, 2004

4.2 Completed Chip Report Files

The following section contains the LVS and DRC reports for the completed product. The LVS program
reports that the net-lists match, and there are zero design rule errors or warnings.

4.2.1. LVS Report

@(#)$CDS: LVS version 4.4.5 04/20/2000 16:37 (cds11182) $

Like matching is enabled.

Net swapping is enabled.
Using terminal names as correspondence points.

Net-list summary for /pc/r/r1/apatel/ece1388/LVS/layout/netlist

count
1618 nets
13 terminals
8800 nfet
72 resistor
52 diode
6275 pfet

Net-list summary for /pc/r/r1/apatel/ece1388/LVS/schematic/netlist

count
1618 nets
13 terminals
1808 nfet
72 resistor
52 diode
1108 pfet

Terminal correspondence points

1 ANALOG_GND
2 ANALOG_IN
3 ANALOG_VDD
4 CLOCK_IN
5 D<0>
6 D<1>
7 D<2>
8 D<3>
9 D<4>
10 D<5>
11 ENABLE
12 gnd!
13 vdd!

38 net-list ambiguities were resolved by random selection.

The net-lists match.

layout schematic
instances
un-matched 0 0
rewired 0 0
size errors 0 0
pruned 0 0
active 15199 3040
total 15199 3040

nets
un-matched 0 0
merged 0 0
pruned 0 0
active 1618 1618
total 1618 1618

terminals

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ECE1388 Final Project Report Dec. 21st, 2004
un-matched 0 0
matched but
different type 0 0
total 13 13

Probe files from /pc/r/r1/apatel/ece1388/LVS/schematic

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:

Probe files from /pc/r/r1/apatel/ece1388/LVS/layout

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:

4.2.2. DRC Report

\o Program: @(#)$CDS: icfb.exe version 4.4.5 05/04/2000 19:33 (cds11182) $
\o Hierarchy: /nfs/vrg/cmc/cmc/tools/cadence.2000a/IC.445.qsr1/tools.sun4v/dfII/
\o Sub version: sub-version 4.4.5.100.10
\o X server: StarNet Communications Corp.
\o Depth of Visual (Root): 8 (24)
\o Number of Planes Used: 8
\o X version: 11.0 (vendor release 5223)
\o Window Manager: other
\o User Name: apatel
\o Working Directory: seth.eecg:/pc/r/r1/apatel/ece1388
\o Process Id: 9586
\o
\o COPYRIGHT © 1992-1999 CADENCE DESIGN SYSTEMS INC. ALL RIGHTS RESERVED.
\o © 1992-1999 UNIX SYSTEMS Laboratories INC.,
\o Reproduced with permission.
\o
\o This Cadence Design Systems program and online documentation are
\o proprietary/confidential information and may be disclosed/used only
\o as authorized in a license agreement controlling such use and disclosure.
\o
\o RESTRICTED RIGHTS NOTICE (SHORT FORM)
\o Use/reproduction/disclosure is subject to restriction
\o set forth at FAR 1252.227-19 or its equivalent.
\w X Toolkit Warning:
\w Cannot allocate colormap entry for default background
\w
\o Loading PRshare.cxt
\o Loading auCore.cxt
\o Loading schView.cxt
\o Loading selectSv.cxt
\o running /nfs/vrg/cmc/cmc/tools/cadence.2000a/IC.445.qsr1/tools.sun4v/dfII/local/.cdsinit ...

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ECE1388 Final Project Report Dec. 21st, 2004
\o Running /nfs/vrg/cmc/cmc/tools/cadence.2000a/IC.445.qsr1/tools.sun4v/dfII/local/skill/CMCinit.il ...
\o V1.10 of the CMC Local Technology Environment for Cadence IC tools
\o ******************************************************************************
\o This is Cadence software customized for use in the Canadian Microelectronics
\o Corporation design environment.
\o USE OF THIS SOFTWARE AND/OR ASSOCIATED MATERIALS IS RESTRICTED TO LICENSED SITES ONLY.
\o For more information, contact CMC:
\o Canadian Microelectronics Corporation
\o 210A Carruthers Hall, Queen's University
\o Kingston Ontario Canada K7L 3N6
\o Voice: (613) 530-4666
\o FAX: (613) 548-8104
\o Email support@cmc.ca
\o ******************************************************************************
\o
\o License file is: /CMC/tools/licenses/cds.license:/CMC/tools/licenses/synopsys.license
\o The skillPath is ("." "./skill" "~/skill"
"/nfs/vrg/cmc/cmc/tools/cadence.2000a/IC.445.qsr1/tools.sun4v/dfII/local/lib/cmosp35/skill"
"/nfs/vrg/cmc/cmc/tools/cadence.2000a/IC.445.qsr1/tools.sun4v/dfII/local/skill"
"/nfs/vrg/cmc/cmc/tools/cadence.2000a/IC.445.qsr1/tools.sun4v/dfII/etc")
\o Paths not reachable via skillPath are ("./skill" "~/skill")
\o
\o CMC Gateway menu added to CIW.
\o Setting up environment for CMOSP35 technology...
\o Running
/nfs/vrg/cmc/cmc/tools/cadence.2000a/IC.445.qsr1/tools.sun4v/dfII/local/lib/cmosp35/skill/CMOSP35init.il
...
\o This is the CMC cmosp35 Design Kit V4.2 for Synopsys and Cadence
\o Loading CEplace.cxt
\o Loading CEshare.cxt
\o Registering schematic triggers...
\o Registering schematic triggers...
\o Registering maskLayout triggers...
\o CMOSP35 menu added to CIW.
\o Display.drf file loaded
\o Completed
/nfs/vrg/cmc/cmc/tools/cadence.2000a/IC.445.qsr1/tools.sun4v/dfII/local/lib/cmosp35/skill/CMOSP35init.il
...
\o === starting ~/.cdsinit ...
\o === completed ~/.cdsinit ...
\o Completed /nfs/vrg/cmc/cmc/tools/cadence.2000a/IC.445.qsr1/tools.sun4v/dfII/local/skill/CMCinit.il
...
\o Loading /CMC/kits/VRGlocal/skill/LOCALinit.il
\o 'VRG Info' menu added to CIW.
\o Completed loading /CMC/kits/VRGlocal/skill/LOCALinit.il
\o completed /nfs/vrg/cmc/cmc/tools/cadence.2000a/IC.445.qsr1/tools.sun4v/dfII/local/.cdsinit ...
\p >
\r t
\a mspsCheckPinsUI()
\p >
\a hiiSetCurrentForm('mspsCheckPinsForm)
\r t
\a hiFormDone(mspsCheckPinsForm)
\o Comparing Pins between Library:FinalProject,Cell:chip,View:schematic and
Library:FinalProject,Cell:chip,View:layout
\o The Schematic and Layout Pins match
\o MSPS: done...
\r t
\r nil
\a ivHiExtract()
\p >
\a hiiSetCurrentForm('ivExtOptionsForm)
\r t
\a hiFormApply(ivExtOptionsForm)
\o
\o Extraction started at Sun Dec 12 19:11:05 2004
\o
\o
\o library: FinalProject
\o cell: chip
\o view: layout
\o Rules come from library APSRules.
\o Rules path is divaEXT35n.rul.
\o Inclusion limit is set to 1000.

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ECE1388 Final Project Report Dec. 21st, 2004
\o Running layout extraction analysis
\o flat mode
\o Full checking.
\o For layer p1res :
\o 72 shapes encountered.
\o 72 resistor ivpcell cmosp35 devices well formed.
\o For layer ndiode :
\o 26 shapes encountered.
\o 26 diode ivpcell cmosp35diode devices well formed.
\o For layer pdiode :
\o 26 shapes encountered.
\o 26 diode ivpcell cmosp35diode devices well formed.
\o For layer nmos :
\o 8800 shapes encountered.
\o 8800 nfet ivpcell cmosp35 devices well formed.
\o For layer pmos :
\o 6275 shapes encountered.
\o 6275 pfet ivpcell cmosp35 devices well formed.
\o saving rep FinalProject/chip/extracted
\o Extraction started.......Sun Dec 12 19:11:05 2004
\o completed ....Sun Dec 12 19:12:51 2004
\o CPU TIME = 00:01:00 TOTAL TIME = 00:01:46
\o ********* Summary of rule violation for cell "chip layout" *********
\o
\o Total errors found: 0
\r t

4.3 Data Sheet

4.3.1. Operating Parameters
Specification Simulated ADC Maxim 105ECS
3.3V typical 3.3V 5V
Supply Voltage
Temperature 70ºC typical 70ºC 25ºC (Ambient)
Resolution 6-Bit 6-Bit 6-Bit
Signal Frequency 10Mhz 100MHz 200Mhz
Sampling Rate 20Msample/sec 200MSample/sec 800MSample/sec
Power 200mW 154mW 2600mW
Consumption
Operating Range 0V to VDD 0V to VDD 1.45 to 2.25V
Die Size 2mm X 2mm 1.58mm X 1.58mm Not Available

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ECE1388 Final Project Report Dec. 21st, 2004
4.3.2. Chip Pinout

4.4 Schematics
The following section illustrates the schematics of key components within our design. For further
information, please consult the “Schematics Slides” or “Top-Level Slides” referenced from the project
web-page.

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ECE1388 Final Project Report Dec. 21st, 2004
4.4.1. Latched Comparator

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ECE1388 Final Project Report Dec. 21st, 2004
4.4.2. NMOS Preamplifer

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ECE1388 Final Project Report Dec. 21st, 2004
4.4.3. PMOS Preamplifier

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ECE1388 Final Project Report Dec. 21st, 2004

4.4.4. Resistor Ladder

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ECE1388 Final Project Report Dec. 21st, 2004

4.4.5. CML-to-CMOS Converter

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ECE1388 Final Project Report Dec. 21st, 2004

4.4.6. Priority Encoder

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ECE1388 Final Project Report Dec. 21st, 2004

4.4.7. Priority-to-Binary Encoder

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ECE1388 Final Project Report Dec. 21st, 2004

4.4.8. Clock Management Block

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ECE1388 Final Project Report Dec. 21st, 2004

4.5 Simulations
The following section contains simulation results for the key components within our design. Further
details regarding the simulations can be found in the Appendix section of the project web-page.

4.5.1. Latched Comparators (1.2GHz, Ramp Input)

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ECE1388 Final Project Report Dec. 21st, 2004

4.5.2. Priority Encoder

Arun Patel – 994225575 Eliyahu Zamir – 961339780 Manuel Saldaña - 94117139

ECE1388 Final Project Report Dec. 21st, 2004

4.5.3. Priority to Binary Converter

Arun Patel – 994225575 Eliyahu Zamir – 961339780 Manuel Saldaña - 94117139

ECE1388 Final Project Report Dec. 21st, 2004

4.5.4. Clock Management

Arun Patel – 994225575 Eliyahu Zamir – 961339780 Manuel Saldaña - 94117139

ECE1388 Final Project Report Dec. 21st, 2004

4.5.5. Top Level

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ECE1388 Final Project Report Dec. 21st, 2004

4.6 Reference Material

[1] Maxim Integrated Circuits, Understanding Flash ADCs, www.maxim-ic.com/an810, Application
Note 810, Oct 2nd, 2001.

[2] Kun, C., and Mason, A., A Power-Optimized 64-bit Priority Encoder Utilizing Parallel Priority
Look-Ahead, IEEE International Symposium on Circuits and Systems 2004, vol. II, pp. 753-756.

Arun Patel – 994225575 Eliyahu Zamir – 961339780 Manuel Saldaña - 94117139