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Technology Scaling

In order to build the high performance CMOS circuits certain electrical design rules are taken into account. These rules are used to develop the mathematical model of the physical phenomenon

occurring in the circuits.

As the current CMOS fabrication processes are improved and the device dimensions are shrinking

these design rules will change.

Hence as the device dimensions are changing the electrical parameters of the devices are also has

to

be scaled accordingly to apply the previously developed models to the current modern devices

and circuits.

In scaling of the MOS devices the characteristics of the device are maintained and the basic

operational characteristics are preserved by introducing a dimensionless factor . Efforts are under way to make transistors as small as possible to increase speed and circuit complexity per unit of chip area.

For this purpose, we have to adjust a fabrication process and the bias voltage to allow proper

operation of reduced size devices. The adjustments aim at achieving small dimension, at the same time, avoiding several side effects, such as the smaller dimension effects. Such a shrinking of device without side effects is called as scaling. Advantages of Scaling :

(1) Improved current driving capability improves the device characteristics. (2) Due to small geometries the capacitance reduces. (3) Improved interconnect technology reduces the RC delay. (4) The multiple threshold devices due to scaling adjusts the active and stand by power trade‐offs. (5) The integration density improves due to single chip devices. (6) Enhanced performance in terms of speed and power consumption. (7) Cost of a chip decreases by twice. Disadvantages of Scaling :

1) The power consumption per unit area increases as devices are scaled down. That means scaled devices run increasingly hot. This is a severe performance limitation for scaled devices. 2) The scaling leads to mistakes of having scale proportionally to zero dimension or to zero threshold voltages. 3) Since scaling reduces the carrier mobility, gain of the device reduces. 4) Due to reduction in conductor size, the current handling capacity of the device reduce. To solve this addition metal layers are necessary for more densely packed structure. 5) As the packing density per chip increases, due to higher power density, the device becomes very hot and needs forced cooling at the additional cost. 6) Higher fields also cause hot electron and oxide reliability problems.

Constant Field Scaling : In constant field scaling the scaled devices are obtained by scaling all dimensions of transistor, device voltages and the doping concentration densities by factor α. The most important point in this scaling is the supply voltage is scaled but the electric field remains constant hence the same constant field scaling is given. Constant Voltage Scaling : In constant voltage scaling the supply voltage VDD is kept constant while the process is scaled. With constant voltage scaling the electric field increases which has lead to the development of the lateral double diffused structures. Lateral Scaling: In lateral scaling only the gate length is scaled. This is also called as the "gate shrinking".

CMOS Design Flow :

Figure below shows the CMOS IC design flow, it consists of defining circuit inputs and outputs also called as specifications

of the circuit.

Once the detailed list of inputs and outputs is developed from this the design calculations are performed and the circuit schematic for the intended integrated circuit is designed. This developed schematic is then drawn in CAD (Computer Aided Design) tools e.g. Tanner.

Once the schematic entry is finished then the circuit simulations are carried out and the obtained simulation

results are checked with the intended specifications this step

is called as pre‐layout simulation.

After checking post layout simulation results, the next step is the fabrication of the prototype board.

Once the fabricated board comes the testing of the protype is carried out and the initial specifications are checked, if these results are not matched with the intended specifications then there are two possibilities of error that may be either because

of fabrication or initial specification problem.

If the prototype board passed all the tests then it is given for mass production. This flow is used for custom IC design.

A custom designed IC is also called as ASIC (Application

Specific Integrated Circuit).

Other non‐custom methods of designing chips includes FPGA (Field Programmable Gate Arrays) and standard cell libraries.

The FPGA and standard cell approach is used when low volume and quick design turnaround are important.

Most of the chips that are mass produced such as microprocessors and memories are manufactured using the custom design approach shown in Figure.

using the custom design approach shown in Figure. Body Effect : In I‐V analysis we ass

Body Effect :

In I‐V analysis we assumed that the bulk and source of transistor were tied to ground, what happens if the bulk voltage of NMOS is drops below the source voltage ? To understand this effect suppose VS = 0 and VD = 0 and VG is somewhat less than VTH so that depletion region is formed under the gate but inversion channel does not exist as shown in Figure. As VB becomes more negative (i.e. VB < VS where VS = 0) more holes are attracted to the substrate connection leaving a larger negatively charged ions behind i.e. the depletion region becomes wider as shown in Figure. As we know that the threshold voltage is a function of the total charge in the depletion region (i.e. Qdep). Thus as the body voltage VB drops then depletion charge (Qdep) increases which increases the threshold voltage (VTH). This effect is called as the body effect or back gate effect.

effect is called as the body effect or back gate effect. Hot Electron Effect : When
effect is called as the body effect or back gate effect. Hot Electron Effect : When

Hot Electron Effect :

When the NMOS transistor is operated in the saturation region particularly "pinch off " condition hot carries i.e. electrons are travelling with saturation velocity and cause parasitic effects at the drain side of the channel. This effects are called as hot electron effects. These hot electron have sufficient energy to generate the electron‐hole pairs by impact ionisation. Figure shows the impact ionisation effect in the MOSFET.

Figure shows the impact ionisation effect in the MOSFET. The generated bulk minority carries can be

The generated bulk minority carries can be collected by the drain or injected into the gate oxide. The generated majority carries create a bulk current which can be used to measure the level of the impact ionisation. The carries injection into the gate oxide lead to the hot carrier degradation effect. The hot electrons can be also operate the trap 6 at the silicon‐oxide interface. Therefore the hot electron effect limit the lifetime of the transistor. Thus energy of the hot carries depends mainly on the electric field in the pinch‐off region.

Velocity‐Saturation From the physics of semiconductors it is proved that the velocity of charge carriers is linearly proportional to the electric field and the proportionality constant is called as mobility of carrier. But when we increase the electric field beyond certain velocity called as the thermal velocity or saturated velocity the velocity of the charge carrier does not change with electric field as shown in Figure.

does not change with electric field as shown in Figure. The electric field at which the

The electric field at which the velocity of carrier saturates is called

as the critical electric field. The loss of energy is because of the collisions of carriers called as scattering effect.

In MOSFETs when electrical field along the channel reaches a critical value the velocity of carriers

tends to saturate and the mobility degrades. The saturation velocity for electrons and holes is approximately same i.e. 107 cm/s. The critical field at which saturation occurs depends upon the doping levels and the vertical electric field applied.

Transmission Gate Logic : The transmission gate logic is used to solve the voltage drop problem of the pass transistor logic. This technique uses the complementary properties of NMOS and PMOS

transistors. i.e. NMOS devices passes a strong ‘0’ but a weak ‘1’ while PMOS transistors pass a strong

‘1’ but a weak ‘0’. The transmission gate combines the best of the two devices by placing an NMOS

transistor in parallel with a PMOS transistor as shown in Figure below. The control signals to the transmission gate C and ––C are complementary to each other. The

transmission gate is mainly a bi‐directional switch enabled by the gate signal ‘C’. When C = 1 both MOSFETs are ON and the signal pass through the gate i.e. A = B if C = 1. Whereas C = 0 makes the MOSFETs cut off creating an open circuit between nodes A and B.

cut off cr eating an open circuit between nodes A and B. 2 : 1 MUX

2 : 1 MUX using transmission gate :

A 2:1 multiplexer is shown in Figure below. This gate selects either input A or B on

the basis of the value of the control signal ‘C’.When control signal C is logic low

the output is equal to the input A and when control signal C is logic high the output is equal to the input B.

A 2 : 1 multiplexer can be implemented using transmission gates. Figure below

shows the connection diagram of the 2 : 1 multiplexer using transmission gates. The 2 : 1 MUX selects either A or B depending upon the control signal C. This is equivalent to implementing the Boolean function,

F = (A C + B ––C)

When the control signal C is high then the upper transmission gate is ON and it

C is high then the upper transmission g ate is ON and it passes A through

passes A through it so that output = A.

When the control signal C is low then the upper transmission gate turns OFF and it will not allow A to pass through it, at the same time the lower transmission gate is ‘ON’ and it allows B to pass through

it so the output = B.

and it allows B to pass thr ough it so the output = B. CMOS ‘

CMOS ‘’ Design Rules :

The MOSIS stands for MOS Implementation Service is the IC fabrication service available to universities for layout, simulation, and test the completed designs. The MOSIS rules are scalable ‘’ rules. The MOSIS design rules are as follows :

(6) Rules for metal 1 as shown in Figure below.

1. Minimum width = 3

2. Minimum spacing = 3

3. Minimum overlap of poly contact = 1

4. Minimum overlap of active contact = 1

(1) Rules for N‐well as shown in Figure below.

(1) Rules for N‐well as shown in Figure below.  
 

1. Minimum width = 10

2. Wells at same potential with spacing = 6

 

(7) Rules for via 1 as shown in Figure below.

3. Wells at same potential = 0

1. Minimum size = 2  

4. Wells of different type, spacing = 8

 

2. Minimum spacing = 3

   

3. Minimum overlap by metal 1 = 1

(2) Rules for Active area shown in Figure below.

 

1. Minimum width = 3

   

(8) Rules for metal 2 as shown in Figure below.

2. Minimum spacing = 3

1. Minimum size = 3

3. Source/Drain active to well

2. Minimum spacing = 4

edge = 5

 

4.

Substrate/well contact active

to well edge = 3

     

(9) Rules for metal 3 as shown in Figure below.

3) Rules for poly 1 as shown in Figure below.

   

1.

Minimum width = 6

1. Minimum width = 2

2.

Minimum spacing = 4

2. Minimum spacing = 2

 

3. Minimum gate extension of active = 2

4. Minimum field poly to active = 1

(4) Rules for contact to poly 1 as shown in Figure below.

1. Exact contact size = 2   2

2. Minimum poly 1 overlap = 1

3. Minimum contact spacing = 2

(5) Rules for contact to active as shown in Figure below.

1. Exact contact size = 2  2

2. Minimum active overlap = 1

3. Minimum contact spacing = 2

4. Minimum spacing to gate of transistor = 2

 2. Minimum active overlap = 1  3. Minimum contact spacing = 2  4.
 2. Minimum active overlap = 1  3. Minimum contact spacing = 2  4.
 2. Minimum active overlap = 1  3. Minimum contact spacing = 2  4.
 2. Minimum active overlap = 1  3. Minimum contact spacing = 2  4.
 2. Minimum active overlap = 1  3. Minimum contact spacing = 2  4.

Design Rule Check :

In order to ensure that none of the design rules are violated CAD tools named Design Rule Checking

(DRC) is used. If DRC is not verified then it leads to the non functional design. The layout rules are grouped in three categories that are transistor rules, contact and via rules and

well and substrate contact rules. Transistor rules :

The transistor can be created by overlapping the the active and polysilicon layers. The minimum length of transistor equals 0.24 m which is minimum width of polysilicon, whereas the width of the transistor is atleast 0.3 m which is the minimum width of active layer. Figure below shows the layout of PMOS transistor.

layer. Figure below shows the layout of PMOS transistor. Fig1‐Design‐Rule‐Check Contact and Via rules : A

Fig1‐Design‐Rule‐Check

Contact and Via rules :

A contact forms an interconnection between metal and active or polysilicon layer whereas via forms

an interconnection between two metal lines. A contact or via is formed by overlapping the two interconnecting layers and provides a contact hole filled with metal between the two. Figure below shows the contacts and via used in layout.

Figure below shows the contacts and via used in layout. Fig1‐Design‐Rule‐Check Well and substrate contact

Fig1‐Design‐Rule‐Check

Well and substrate contact rules :

For digital circuit design it is important for the well and substrate regions to be connected to the supply voltages. If this is not done then a resistive path is created between the substrate contact of the transistors and the supply rails which leads to parasitic effects such as latch up.

Layout Design Rules :

The layout design rules provide a set of guidelines for constructing the various masks needed in the fabrication of integrated circuits. Design rules are consisting of the minimum width and minimum spacing requirements between objects on the different layers. The most important parameter used in design rules is the minimum line width. This parameter indicates the mask dimensions of the semiconductor material layers. Layout design rules are used to translate a circuit concept into an actual geometry in silicon. The design rules is the media between circuit engineer and the IC fabrication engineer. The Circuit designers requires smaller designs with high performance and high circuit density whereas the IC fabrication engineer requires high yield process. Minimum line width (MLW) is the minimum MASK dimension that can be safely transferred to the semiconductor material. For the minimum dimension design rules differ from company to company and from process to process. To address this issue scalable design rule approach is used. In this approach rules are defined as a function of single parameter called ‘’. For an IC process ‘’ is set to a value and the design dimensions are converted in the form of numbers. Typically a minimum line width of a process is set to 2e.g. for a 0.25 m process technology ‘’ equals 0.125 m.

Layered Representation of Layout :

The layer representation of layout converts the masks used in CMOS into a simple layout levels that are easier to visualise by the designers. The CMOS design layouts are based on following components :

(1) Substrates or Wells : These wells are p type for NMOS devices and n type for PMOS devices. (2) Diffusion regions : At these regions the transistors are formed and also called as active layer. These are defined by n+ for NMOS and p+ for PMOS transistors. (3) Polysilicon layers : These are used to form the gate electrodes of the transistors. (4) Metal interconnects layers : These are used to form the power supply and ground rails as well as input and output rails. (5) Contact and Via layers : These are used to form the inter layer connections.

JTAG TAP Controller :

The TAP controller is a finite state machine that responds to changes at the TMS and TCK signals of the TAP and controls the sequence of operations of the circuitry defined by standard. It also controls the scanning of data into the various registers of the JTAG architecture. Two state transition paths for scanning the signal at TDI, one for shifting to the instruction register and one for shifting data into the active data register. The state diagram is shown in figure below. All state transitions of the TAP controller shall occur based on the value of TMS at the time of a rising edge of TCK. Actions of the test logic shall occur on either the rising or the falling edge of TCK in each controller state. The behavior of the TAP controller and other test logic in each of the controller states is briefly described as follows.

of the controller states is briefly described as follows. Fig. JTAG TAP controller states flow Test‐Logic‐Reset

Fig. JTAG TAP controller states flow Test‐Logic‐Reset : This state is entered on power‐up of the device. Run‐Test‐Idle : This state allows certain operations to occur depending on the current instruction. Select‐DR‐Scan : This state is entered prior to performing a scan operation on a data register. Select‐IR‐Scan : This state is entered prior to performing a scan operation on the instruction register. Capture‐DR : This state allows data register selected by the current instruction on the rising edge of TCK. Shift‐DR : This state shifts the data, in the currently selected register. Exit1‐DR : This state allows the option of passing on to the Pause‐DR state. Pause‐DR : This wait state allows shifting of data to be temporarily halted. Exit2‐DR : This state allows the option of passing on to the Update‐DR state. Update‐DR : This state causes data contained in the currently selected data register to be loaded into a latched parallel output. Capture‐IR : This state allows data to be loaded from parallel inputs into the instruction register. Shift‐IR : This shifts the values in the instruction register towards TDO. Exit1‐IR : This state allows the option of passing on to the Pause‐IR state. Pause‐IR : This wait state that allows shifting of the instruction to be halted. Exit2‐IR : This state allows the option of passing on to the Update‐IR state. Update‐IR : This state causes the values contained in the instruction register to be loaded into a latched parallel output on the falling edge of TCK after entering this state.