Bistable Circuits - Part I.

Again here ... and after this I'll take a good rest, I think ... !!!

Let's start ... Bistable circuits are well known and used as memory elements, since they
are capable of storing a bit of information. In general, they are known as Flip-Flop and
have two stable states, one at high level (logical 1) and another at low level (logical
zero), It was understood ...?, Applause for me ... thank you, thank you very much ... !!!

Sorry, I was forgetting a little detail, it is possible that when pressing the button there
will be electrical rebounds, it is like having pressed it several times, and yes ... the
results will be totally unexpected, so that of the cables to test these circuits They will
not help us much, it is convenient to use a clock pulse to perform these tests, you know
... !!! an astable circuit, of what we did in previous lessons , from now on we will call
it a clock pulse or Clock or CK .

In general, a Flip-Flop has two output signals, one with the same value of the input and
another with the negation of it or its complement.

First the basics, as always, and then we entangle it a little more.

.: FLIP FLOP BASIC RS

One can be easily built using two NAND or NOR gates connected in such a way as to
feed the input of one with the output of the other, leaving an entry of each gate free,
which will be used for Set and Resetcontrol ...

Resistors R1 and R2 used in both cases are 10k and I put them only to avoid
indeterminate states, observe the circuit with NOR gates ... A high level applied in Set ,
causes the denied output ~ Q to be 0due to the table of the NOR gate, when the input
of the second gate is fed back and the other is grounded, the normal output Q will
be 1 . Now, this signal feeds the first gate, therefore rebounds do not matter, and the FF
will remain in this state until you give a positive pulse to the Reset input

Conclusion: The flip-flop has two inputs Set and Resetthat work with the same signal
level, provides two outputs, a normal output Q that reflects the input signal Set and
another ~ Q that is the complement of the previous one.
If you compare the two flip-flops represented in the graph, you will see that they only
differ in the signal levels that are used, due to the truth table that corresponds to each
type of gate.

.: FLIP FLOP RS - Controlled by a clock pulse:

In this case I will use the example of the NAND gates, but we will add two more gates,
and we will join the input of each one to a Clock signal ...

What we have said above, we need a pulse generator (Astable) to connect it to the
Clock input, once we have it we will interpret the circuit ...

If you put a 0 in Set and the Clock input is 1, everything will happen described in the
previous scheme, let's see what happens when Clock goes to 0 ...

Sorpresaaaaaaaaa ... !!!, the FF remains unchanged in Q and ~ Q . Notice that now the
state of Set and Reset does not matter , this is due to its truth table (it is enough that
one of its inputs is 0 so that its output is 1 ), therefore Set and Reset are disabled.

That is, the Set and Reset levels will be read only when the Clock input is 1 .

NOTE 1: The first circuit we saw (Flip-Flop simple) is called Flip-Flop

Asynchronoussince you can change the status of your outputs at any time, and it only
depends on the Set and Reset inputs.

NOTE 2: The second circuit is controlled by a Clock input and is called Synchronous
Flip-Flop since the change of state of its outputs is synchronized by a clock pulse that
performs the reading of the inputs at a certain instant.
Before continuing I want to show you something very interesting, it's not the only way
to get a Flip-Flop, look at this ...

.: FLIP FLOP - With an inverter

The advantage here is the amount of gates used, it's good, do not you think ...?

Well, I'll leave it for you to analyze it ...