Embedded System Design

(10EC74)

Unit - 01

Prof G B Gour 1
 VTU Syllabus

Prof G B Gour 2
 Unit-01
Introducing Embedded Systems

Philosophy

Overview of Embedded System

How Embedded System is Structured

Development Process of Embedded System

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 Unit-01
Philosophy

Philosophy

Necessity was the mother of Invention

Example:
ancestors, Shovel,
gasoline

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 Unit-01
1. System within another system Embedded Systems

other things includes: music player,

aircraft guidance system etc….

2. System is a Combination software & hardware parts

It can accept some input, analyze and then it should give us the
output that the system is meant for or it should drive the next piece
of machine connected to it.

3. System is a technique which makes products smaller,

faster, reliable & cheaper
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Prof G B Gour 6
 Embedded Computer Sub-
Assembly for Accupoll Electronic
Voting Machine

Picture of the internals of an ADSL modem/router. A modern

example of an embedded system. Labelled parts include
a microprocessor (4), RAM (6), and flash memory (7).
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Prof G B Gour 8
 One of the Modern Embedded Systems is…

Apollo Guidance Computer

Type Avionics
Guidance Computer
Processor Discrete IC RTL based
Frequency 2.048 MHz
Memory 16- bit wordlength,
2048 words RAM

36,864 words ROM

Dimensions 24×12.5×6.5 inches(61×32×17 cm)

Power consumption 55W

Weight 70 lb (32 kg)

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According to Wayne Wolf,
“An Embedded System is a computing system other than
desktop computers.”

An embedded system is the one that has computer hardware

with software embedded in it as one of its most important
components.

It is a device that includes a programmable computer but is not

itself intended to be a general purpose computer

Embedded System can be well defined by taking couple of

classical examples.

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 First, an air conditioner is taken for understanding.

Process variable: temperature

Consider a second example of the pace maker.

Process variable: heart beat count

In air conditioner, temperature is the process variable. A controller inside will keep
on monitoring the process variable. If at all the room temperature changes due to
variation in external temperature, controller will take a counter acting signal and
PV (temperature) will be brought to required range.

Second case, controller inside a pace maker will keep monitoring the heart
beat count. If it is getting low, immediately a counter acting action will be taken
and it will boost up the heart.

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 How to Identify an Embedded System?

Characteristics of an Embedded System

Single functioned ( pager, microwave oven, pace maker…)

Tightly constraint (cost, performance, size & cost)
Real time & Reactive
(breaking system in BMW car, pacemakers action)
Complex Algorithms (digital Camera)
User Interface ( Nokia, ATM machine)
Multi rate ( Digital Camera with still photographing & video shooting)

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Prof G B Gour 13
4. System which brings features & capabilities to everyday things

5. Key components : VLSI

6. General view of System:

o word processing software or video game
o fuel control system

7. Challenges to the System:

o conducting experiments on the Mars
o life saving heart monitoring system

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 Challenges to an Embedded System

First and foremost problem in designing an Embedded System is

“Very Less Availability of Tools and Debuggers”.

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1. Meeting Deadlines w.r.t product!!

Meeting deadline accurately will need high speed hardware. & Increasing
hardware components with quality would increase the cost of the product.

This is the first challenge in front of designers.

2. Hardware Selection

* Embedded Systems never had a luxury of having much hardware.

* Adding more memory of smaller size will increase cost factor.

* It can have an expansion slot for the system, if user is willing to expand memory,
who bothers, let user expand.
* Select a processor that perfectly fits in with requirement.

Too high speed processor would cost more and can drain battery also.

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3. Is it upgradable and maintainable?

* How the developer can fix the problem of already released mobile phone
in the market?

⇒ it must be supporting with up gradation of versions of software for it, and

⇒ the product should be upgradable with the same hardware!

* Secondly, when writing software for embedded systems, it should be

kept in mind on maintainability.

4. Will it work ?
It is proceeded through rigorous testing.
First it can be unit testing, next stage is Sanity Testing and the third stage can
be Regression testing.
Then through continuous monitoring….
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8. Building an Embedded System

Microprocessor

3
Microcomputer basic types of
computing
engines

Microcontroller

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 Microprocessor
firmware, stored in ROM,
Instruction cycle

Microcomputer H/D elements are connected by

System Bus,
Address/ Data / Control buses

while (1)
Microcontroller {
Embedded Program
Instruction Cycle }

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9. An Embedded System w.r.t 3 Engines

Example:
an automobile with 100’s embedded microprocessors &
microcontrollers for managing:

o Engine ignition & Firing

o Transmission shifting
o Power steering
o Anti lock breaking system
o Security system
o Passenger entertainment system

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10. Watchdog Timer

Signal from WATCHDOG TIMER

comes into the processor as NMI

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11. Real Time

o An important constraint in an Embedded System

responding to external or internal events within specified
time interval

12. Types of Real Time systems (based on urgency of

meeting the required time constraints)

Soft Real Hard Real Firm Real

Time System Time System Time System

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 Soft Real Time System
failure to meet the time constraint results only in degraded
performance

Hard Real Time System

failure to meet the time constraint results in considerable risk
to people, environment

Firm Real Time System

lies in between soft & hard real time systems

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13. R T O S

Operating System used in an Embedded micro

computer, is a real time O S; specifically designed &
optimized to predictably handle the strict time
constraints corresponding to events in a real time
context

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 Unit-01
Embedded Design & Development Process

Contemporary Embedded Applications

Simple ones that runs toaster, microwave, video games etc..

Sophisticated ones

controls jet air craft, manage an entertainment

system, control nuclear reactor

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 Embedded System Life Cycle

Increased Productivity
Reduced Design Life Cycle
Improved Product Quality

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Interfacing with Outside World

Major Signals by which an

Embedded System
Communicates with
External World

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Embedded System Design
(10EC74)

Unit - 02

Prof G B Gour 1
 VTU Syllabus

Prof G B Gour 2
 Unit-02
Hardware Side: Introduction

Essential elements of today’s Embedded system

Hardware
going to vary with every design Software &
Firmware

Hierarchy of Hardware components in Today’s world

At Top:
VLSI Circuits, microprocessors, microcontrollers, FPGA’s, CPLD’s &
memories

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 Next Level Down:
MSI Circuits,

Next Level Down:

SSI Circuits,
Glue
Logic
At Bottom:
Electrical signals used to represent data, some controlling information

High Level view of Computing

Core of the System

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 Unit-02
Hardware Side:
Core Level

Computing Core:

Central Hardware component in modern embedded application

( Microprocessor, Microcontroller, microcomputer
or custom designed VLSI circuits or FPGA )

Such actions are controlled by set of software or Firmware

instructions

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 Core Level

The Top Level model has 4 major functional blocks

depicting an embedded hardware & high level signal flow

Memory:

holds collection of program

instructions (S/F & H/D)

provides short term storage for

i/p data, o/p data and
intermediate data

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Data Path & Control Unit ( CPU ) :

Coordinates the activities of the system

Performs computations, data manipulations to execute application

Typical Bus Structure

Bus
electrical wires that carry the related
Address Bus
electrical signals into , out or throughout
Data bus the system

Control Bus

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High Level Functional diagram refined with Bus Structure

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 Bit

Width

Examples:

To transfer 64-bit data on 32-bit Width bus needs 2 transfers of data

To transfer 64-bit data on 8-bit Width bus needs 4 transfers of data

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Microprocessor

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Microcomputer

It is a complete computer system that uses

microprocessor as its computational core;
with many LSI circuits to provide peripheral
functions

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Microcontroller

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DSP

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 Unit-02
Hardware Side:
Representing Information

Information in an Embedded System Application

̶ Numbers, Symbols & Characters

̶ Firmware Instructions ( ROM )
̶ Data ( RAM )

Word Size refers to the size of an integer in

microprocessor

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Word Size ( Examples ) Microprocessor with word size of 32 bits,
called 32-bit machine

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 Unit-02
Hardware Side:
Understanding Numbers

See the Board

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 Unit-02
Hardware Side:
Addresses
Memory

Accessed by an Address Information

int myVar = 10;

int* myVarPtr = &myVar ;

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 Unit-02
Hardware Side:
Instructions

Purpose of an Instruction
is to direct the hardware of the microprocessor to perform a series of
actions like, arithmetic, logical calculations, Read/ Write operations..etc..

Such actions are called “ operations”

Operands entities that instruction operates on

Arity number of operands that an instruction

operates on at any time

Example: x = y + z
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Operators taking only single operand have an arity of one & called
Unary Operator

Common C/ C++ instructions x = y

Value of y is assigned to the operand x

Two operands => binary operator
2 operand instruction or 2 address instruction

z = x + y

2 – operations, Binary operations

3 operand instruction or 3 address instruction

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 x = x + y

2 – operations, Binary operations

2 operand instruction or 2 address instruction

++x or x++

1 – operation, Unary operation

1 operand instruction or 1 address instruction

Single Two Three

Operand Operand Operand
Instruction Instruction Instruction

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Interpretation of bits in 32 bit word w.r.t instructions

Single Operand Instruction

Two Operand Instruction

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 Three Operand Instruction

Which Field is used for operation ?

Who will specify the size ?

It depends on the number of instructions that microprocessor supports

Each such instruction is assigned a unique code called Op-Code.

Example: If microprocessor supports 128 instructions , 7 bits are needed.
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 Unit-02
Hardware Side:
Registers – A First Look

Size of the fields is allocated to the operands is not a BIG PROBLEM

Problem:
How to interpret a 32 bit word as different data types (operands) ?

Problem:
If an instruction containing a single operand , along with op code is
32 bits; then a 32 bit piece of data will not fit into any of the fields,
allocated to hold the operand

Register
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 RISC /CISC

few Registers ( 16 to 256 ) - C I S C

over 1000 Registers - R I S C

Main Points

Number of Registers is not important but, their effect on the

SYSTEM performance is important
Role of Registers: Contents of the Operand field, is a binary
number indicating which of the Registers contains operands

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Example:
Hypothetical Microprocessor with number of instructions 144,
for unique identification of each instruction, needs an op code
with 8 bits => 27 < 144 < 28

Number of registers = 256

Conclusion
For unique identification or access of each register, needs an operand
of 8 bits; REGISTER Designator

Type information
Grouping of bits has no inherent meaning, but interpretation does…..!!
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New Interpretation of the Operand Fields

Single operand Instruction

Two operand Instruction

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 Three operand Instruction

New Interpretation of the WORD in Microprocessor

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Prof G B Gour 28
 Unit-02
Hardware Side:
Embedded Systems – An Instruction set View

Software or Firmware in an Embedded System Written in

High level Assembly

Language High level &Assembly
Language
Language
( Optimized for Speed/
Size )

Instruction Set ( Set of Instructions that machine supports)

It drives the Architecture & Underlying Hardware of the Processor

Architecture I S A

It provides Public Interface for the underlying Hardware

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Instruction Set Instruction types

Gives basic operations supported by the Machine

Objectives:
to transfer or to store the data
make decisions based on the data values of the operations

Data Transfer Moving data within the system

doing exchanges with external devices

Flow Control Decides the order , the instructions executed

Arithmetic & Provides Computational abilities

Logical

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Data Transfer Instructions

has 3 pieces of information

Register Memory I/O Port

supported by 1/2/3 operand instructions

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 Op Code Indicates Operation to be performed on operands

But, Actual selection of operands controlled by addressing mode,

means, portion of each operand field is designated as specification to

hardware , as to how to interpret or use the information in the
remaining bits of the associated address filed.
This specification is called addressing mode for the operand

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 Use of Addressing Mode
Offers greater flexibility in accessing the data & controlling the flow of the
program as it executes
this leads to optimization of performance of an application

Instruction types enhanced to include Addressing Modes

1 - Operand Instruction

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2 - Operand Instruction

3 - Operand Instruction

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 Commonly used Addressing Modes

Why the Operand Address will have to be 4 – bit Wide ..?

To support the 5 modes with Direct or Indirect selection

1. Immediate Mode

Uses one of the operand fields to hold the value of the operand.
( helps to reduce the number of memory access )
This is useful if, the value of the immediate operand is small ;
like loop indices or initializing values.

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 Immediate Instruction in the form of 1 or 2 operand instruction

@ Assembly level

As it has only the immediate

value, & ALU is the implied
target

@ High level language

int x = 0xB;
MOVE OPR1, #Bh

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 Variations on the Immediate Mode Instruction

On some processors, the instruction mnemonic indicates the operation is to use

an immediate operand

Examples:

STI Store Immediate

LDI/LOADI Load Immediate
MOVI Move Immediate

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2. Direct & Indirect Modes

Operand addresses are used rather than operand values

First level of address information is contained in the instruction

Direct Mode

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Indirect Mode

Major Disadvantage
Additional Memory Access needed to retrieve an Operand

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3. Register Direct & Register Indirect Modes

Register contains the address of the operand

Register contains the value of the operand

Advantage
means to easily implement POINTER type Operations used in C/C++

Disadvantage
Additional Memory Access to get operand’s value

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Register Direct Mode

Assumes that , the values of x & y have been stored in registers R2 & R3

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Register Indirect Mode

Assumes that , the values of x & y have been stored in registers R2 & R3

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4. Indexed Mode ( Displacement Addressing Mode )

Advantage
for accessing Array type of data

Disadvantage
Time consumption in computation of ,
Effective Address = Base Address + Contents of Indexing Register
& then retrieving the value from memory

Indexing Adds GREATER burden to system performance

than does indirect addressing

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 Index Register

Base Register

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5. Program Counter Relative Mode ( P C R M )

is mechanically almost identical to the indexed addressing mode

Differences
Value in P C = Base Address
P C is assigned a value of computed effective address
Therefore contents of P C are modified due to inherent execution
As offset added to P C is a signed number, it may refer to an address
either higher or lower then the original value

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 Index register

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 Flow of Control or Execution Flow of Instructions

1. Sequential Flow

C/C++ Code Assembly Code

a = 10 ; MOVE R1, #Ah;

b = 20; MOVE R2, #14h;

c = a + b; ADD R3, R1, R2;

Execution first assigns the values to several variables and then,

performs an arithmetic operation

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2. Branch Flow

Decision Point

Execution based on the outcome of the test on some condition

Example: if else, switch, case

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Unconditional Branch

executed unconditionally, by replacing the contents of P C

by the effective address specified by the operand

Conditional Branch

executed conditionally, based on

Side effects of operations performed on data

Comparison between two variables ( =, < > )
Carry/ Borrow from arithmetic operations
Variable = 0 or ≠ 0

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o Conditional Information is temporarily held in as a collection of bits in
flag register or condition code register

o State of each bit is evaluated & potentially changed following the

execution of every instruction

Typical Conditional Codes

E, NE Operand 1 is Equal / Not Equal to Operand2

Z, NZ Result of Operation is Zero or Not Zero
GT, GE Operand1 is greater than or Greater than or Equal to Operand 2

N Result of operation is Negative

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 Typical Branching Instructions

BR Label Unconditional branch to specifies label

BR Label, BNE Label Branch to specified label if the Equal flag is set or not
set
BZ Label, BNZ Label Branch to specified label if the Zero flag is set or not set

BV Label Branch to specified label if the Overflow flag is set

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 C/C++ Code Assembly Code
if (a = = b) CMP R2, R1;
c = d + e; BE $1
else SUB R3, R4, R5;
c = d - e; BR $2
$1: ADD R3, R4, R5;
$2: ….

Assembler Construct
Variable s a-e are placed in R1-R5
Compiler will create labels $1 & $2 if, the original source was
written in a high level language,
or by the designer if the original source was assembler code

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3. Loop

Entry decision Point

Code

Exit decision Point

It permits the designer to repeatedly execute a set of instructions either

forever or until some condition met

Examples: do, repeat, While, for

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 C/C++ Code Assembly Code
while ( myVar < 10 ) $1: CMP R2, #Ah
{ index = index + 2; BGE $2
myVar ++ ; ADD R3, #2h
} ADD R2, #1h
BR $1
$2: ….

my Var & index placed in R2 & R3 respectively

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4. Procedure or Function Call

Control flow leaves the current context & executes the set of
instructions,
and then returns to the original context

Code i
function Call function
Code i +1

Examples: procedure or Subroutine Call,

Interrupt Handler, Co-routine

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Operation is supported by the instructions:

CALL
P C is unconditionally saved & replaced by specified operand,
Control is transferred to specified memory location

RET
Previously saved contents of P C are restored
& control is returned to previous context

STACK

Data structure that occupies an area in memory &

supports many operations
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 Operation is supported by the instructions:

Push
Increments the address held by the SP to refer to the next place
( new top of stack)
Then, writes the data to be stored into the address in memory indicated by
that address
The address in SP is incremented from a lower memory address to higher
memory address

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Arithmetic & Logical Instructions

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 Unit-02
Embedded Systems:
A Register View
I S A Level

here, instruction set expresses the machine’s ability

to transfer data
to store data
to operate on data
to make decisions…
needed for machine to perform task in solving problems

Underlying I S A is the physical hardware needed to implement the

operations as directed by the instructions

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 Data Path (Set of Registers)
associated set of micro operations
on data held in registers

Control Unit
System’s behavior is expressed by the
directs the execution order of
movement of data among registers
micro operations

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 Register Transfer Level ( R T L )
operation on data found at the instruction level are paralleled by
similar set of operations at the register level

At the Register Transfer Level,

data transfers, operations on data & control flow
described using Register Transfer Language

Within the language, individual operations & transfers are expressed

using Register Transfer Notation ( RTN)

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 RTN
has direct equivalent
in contemporary hardware
design languages like,
HDLs,
Verilog or VHDL

exactly this facilitating the

transformation from design
to implementation

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Prof G B Gour 63
 Unit-02
Embedded Systems:
A Register View of Microprocessor
Data Path & Control of a Microprocessor

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Process Control Microprocessor’s data path is controlled by
4 basic operations of instruction cycle

Fetch
Fetch

At I S A level;
Decode MOVE IR, *PC;

Execute At R T L level;
MAR PC ;
MDR memory [ MAR ] ;
Next IR MDR ;

Instruction Cycle Prof G B Gour 65

 Decode When the Op code of an instruction is extracted &
decoded by the decoder

after this control logic will initiate the execute

portion

Execute Based on the value in the Op code field, control logic

will initiate the execute portion in steps

@ R T L level; @ I S A level;
MAR R1 ; ST *R1, R2;
MDR memory [ MAR ] ; @ C level;
R2 MDR ; *xptr = y ;
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 Next Address of the next instruction to be executed depends on
type of instruction to be executed
state of condition flags as modified by the recently
completed instruction

2 types of Jumps:
1. Shorter Jump: displacement contained in one of the operands of an
instruction
2. Longer Jump: value contained in memory location following an instruction

@ R T L level;
TR0 IR < n…m> @ I S A level;
// say, offset contained in instruction ADD PC, offset ;
TR1 TR0 + PC;
PC TR1; // next instruction..
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 Unit-02
Embedded Systems:
Concepts of STATE & TIME

TIME:
Neglecting delays through the system, o/p is the immediate & direct
function of current i/p(s). The present o/p of FSM depends on...
o Path the system took to reach the current state
o Present values of i/p set

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STATE:
State variables are the variables whose values changes over time & explains
the behavior of the circuit/ system
State of a system at any time is a set of values of State variables

Example: Current & Voltage variables in an analog circuits

initial fixed
1

Behavior of the System

Single variable indicating memory has two states ( 0 or 1). the set of state variables
, the state changes with time are called State Behavior

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 Unit-02
Embedded Systems:
STATE Diagram

In the Embedded World, the state diagram is the one to capture, describe
& specify the behavior of the system.

State b
1

State a

Cyclic Graph or Directed Graph

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Textual Description

enter room
if in State awake

input boring event

Change to State as sleep

else if State as sleep

input fall off chair

change to state awake

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 boring event
as sleep

enter room

fall off chair

awake

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 Unit-02
Embedded Systems:
Finite State Machine-
Theoretical Model

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Prof G B Gour 74
Embedded System Design
(10EC74)

Unit - 03

Prof G B Gour 1
 VTU Syllabus

Prof G B Gour 2
 Unit-03
Memories & Memory Sub System:
Classifying Memory

Memory w.r.t Smaller & Larger Embedded applications

Classifying the Memory

RAM
memory location is available for immediate access with RAM organized
as bits, bytes or words.

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 D RAM
it is simple memory cell design with bit storage , implemented by stored
charge mechanism & the stored charge can leak away, if it not
repeatedly restored.
are used for larger memory systems
I/O is asynchronous w.r.t external system clock

S RAM
it is complex memory cell design with bit storage , implemented by
latch type mechanism & the stored data doesn’t have to be repeatedly
restored.
are used for high speed memory systems, faster than DRAM
I/O is asynchronous w.r.t external system clock

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 Semi Static RAM
periphery is clock activated.
only 1 memory cycle is permitted/ clock
periphery ckt must allowed to reset after each active memory cycle for
minimum pre charge time, hence no refreshing needed.

SD RAM
synchronizes all addresses, data & control signals to system clock
& allows much higher data transfer rates than asynchronous transfers

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 ROM
like a RAM, only location in memory is available for immediate access
RD operation is orders of magnitude faster than WR operation
WR operation usually involves programming the ROM
organized as bits, bytes or words

P ROM
programmed using programming device & that to only once

EP ROM
programmed using programming device & erasure is done by placing the
device under UV light

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 EE P ROM
reprogrammed & erasure is done electrically via programming device

Flash
kind of a EE PROM,
can be reprogrammed in “ in situ”, device doesn’t have to be removed
from the circuit for reprogramming

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 Unit-03
Memories & Memory Sub System:
A General Memory Interface

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Prof G B Gour 9
Memory Interface needs ...

Address Signals: are input to memory

Data Signals : are input or may be output to memory
Control Signals : are inputs

Common memory control Signals ...

C S : enables the memory device for RD/WR

O E : memory device O/P tri state control
R : read operation on memory device
W : WRITE operation on memory device

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 Unit-03
Memories & Memory Sub System:
R O M Overview

ROM In side View

ROM Out side View

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Prof G B Gour 12
 Unit-03
Memories & Memory Sub System:
Static RAM Overview

SRAM – In Side View

SRAM – Out Side View

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Prof G B Gour 14
 Unit-03
Memories & Memory Sub System:
Dynamic RAM Overview

D RAM – In Side View

D RAM – Out side View

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Prof G B Gour 16
 Unit-03
Memories & Memory Sub System:
Chip Organization

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 Unit-03
Memories & Memory Sub System:
Terminology

Access Time – time to access a word in memory

Read Operation

Write Operation

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Memory Cycle Time – time interval from the start of one
RD/WR to the next

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 Block Size – logical view of a set of words

Bandwidth

pattern of data read from memory - square wave

frequency of wave = BW of memory

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 Latency
measures the time required to compute the address of the sequence
& then locate it’s first block of words in memory

Block Access Time

measure of time to access on entire block from the start of READ.
It includes the time to find the 0th word of a block & then to
transfer the remaining words

Page
logical view placed on, large collection of words in memory.
Size of page can be given in words/Blocks

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 Unit-03
Memories & Memory Sub System:
Memory Interface In Detail:
SRAM Design

oTo support 4K- 16 bit words, 12 address lines & 16 data lines needed
o With restriction of only 8 address lines & 8 data lines.. how?..

Memory Array

To support 1K-16 bit words,

need two 1K-8-bit memory
chips

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Prof G B Gour 23
 Unit-03
Memories & Memory Sub System:
Memory Interface In Detail:
DRAM Design

o Duplicates most of the SRAM design

o Potential need to manage the refresh function
( Due to memory size & IC package size difficulty )

Extended Data Output (EDO)

Variations of DRAM
Synchronous DRAM (SDRAM)

Fast Page Mode (FPM)

Need to accommodate the ever increasing speed of contemporary processors

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 Problem with SRAM
In SRAM design, insufficient pins were available on the microprocessor to
allow the necessary address bits to be controlled in parallel.

Solution
Multiplexing address into the chip as a row segment / Column Segment
& demultiplexing following the strobe (RAS/CAS)

Contemporary Variations on the DRAM:

Performance Enhancing Modifications & Basic DRAM Core Operation

Example:
4M-16 bit device a RAM , that will store 4 million 16 bit words

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 DRAM Timing Analysis

RAS – Row Address Strobe

CAS – Column Address Strobe

RAS Cycle – Period of RAS

RAS to CAS delay

Refresh Period -
Max. period by which all the
memory cells must be refreshed

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Basic Timing Cycle is extended to reduce the time to perform Read/Write
Operations

EDO Extended Data Output Concept,

a contemporary modification
tRAS = RAS interval + one or more CAS intervals

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 DRAM Refresh

For normal memory management (normal RD/WR operations), REFRESH

will become overhead.
Therefore, it is desired that the REFRESH operation has minimal impact on
normal RD/WR operations

Normal RD/WR Operation

Methods

Periodical Burst – Refresh

(Potentially effect real time performance)

Alternative Approach

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 Unit-03
Memories & Memory Sub System:
Memory Interface In Detail:
DRAM Memory Interface

From microprocessor’s point of view, the interface for normal RD/WR operations
to DRAM is same as designed for SRAM

Implementation of REFRESH component

Refreshes one row at a time & implement the REFRESH management

outside the chip

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 Example:
Consider 4M word memory chip, organized as
4K rows & 1K columns,
with each row must be refreshed every 64 ms

4K rows = 12 row address bits

1K columns = 10 column address bits
Total 22 address bits

But, memory chip supports only 12 address input pins

10 of the pins will be shared by row & column address bits

provides greater flexibility in

2 phase clocking scheme time than Phase-1 clocking
scheme

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Interval between Phase-2 & Phase-1 sufficient for all changing &
propagating signals to settle before they are acted on by the logic
clocked by Phase-1

To meet the refresh timing constraint:

Refresh Timing
each row must be refreshed every 16µs

But, executing REFRESH, 16 counts earlier:

at 384 counts [ ( 384/ 25 MHz ) = 15.36 µs ]
provides some timing margin
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This could be done by decoding 2 MSB’s of 9 – bit counter , with each
count incremented by 25 MHz

Counter is incremented following the completition of each row refresh

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 Refresh Address

Different from the address used by normal RD/WR operations. For REFRESH
address, a 12-bit binary counter is used.

Counter should be incremented after every row refresh operation

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 A0 - A11 => 12 address bits (4K)
shared by row (ERA)

A12 - A21 => 10 address bits (1K)

shared by columns (ECA)

RA0 – RA11 => 12 address bits

shared by refresh row (E Rf A)

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 Timing for the normal row & column address enable signals:

Phase-2

Phase-1

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Row & column address enable signals are asserted on Phase-1 of the
clock &
RAC/CAS are generated on Phase-2 of the clock

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 Probability of collision with 3 operations:
Refresh Arbitration
Normal RD/WR
& Refresh

To resolve this arbitration problem:

If a normal RD or WR operation starts, it is allowed to complete

If a refresh operation has started, the normal operation is remembered
In case of a file, the normal operation is given priority

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 Unit-03
Memories & Memory Sub System:
Memory Map
Memory Map of a 16 bit Machine

It identifies the code & data space

1st step in understanding the memory sub

system consisting of 2 parts:

ROM:
used to hold the words that are not
changing at run time

this will be the space for application

firmware

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 RAM:
used to hold the words that are changing at run time

this will be the space for data related to other things

Non-Volatile RAM:
portion of RAM memory that is used for data to be retained, if the power is
removed from the system

In case of memory mapped I/O:

physical memory is not available for data or code
If code or data space exceeds total available primary memory,
then will go for virtual memory/ overlays

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 Unit-03
Memories & Memory Sub System:
Memory Sub System Architecture

Memory Hierarchy using

different memory types
Top Level
slowest, largest, least expensive
memories iDEA:
to execute as
low speed quickly as
SRAM or possible
DRAM

Bottom Level
Smallest, fastest memories

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 Unit-03
Memories & Memory Sub System:
Basic Concept of Caching

Cache:
small & fast memory that temporarily holds
copies of data & program instructions
from main memory

provides rapid execution of instructions/ data held on cache

Today’s high performance microprocessors, implemented around HARWARD

Architecture will have both iCACHE & dCACHE

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Locality of Reference
Problem
Time burdens in an Embedded system are:
memory accesses & memory access speeds

Solution

reduce the number of memory accesses

make each memory access as short as possible

trade off between High speed memories & cost

Locality of Reference

Types of Locality of Reference:

Spatial Locality of Reference
Temporal Locality of Reference

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Cache System Architecture

DRAM

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 Unit-03
Memories & Memory Sub System:
Designing A Cache System

High Level Description Cache HIT-MISS

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 Unit-03
Memories & Memory Sub System:
Dynamic Memory Allocation

Dynamic Memory Allocation:

Allocation of memory during run time
with extensible data structure like linked list or heap
( works well for an embedded system )
Example: C malloc, C++ new operators used with heap

Dynamic Memory Allocation: USES

Managing Main Memory to accommodate...
(i) programs larger than main memory
(ii) multiple processes in main memory
(iii) multiple programs in main memory

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Different Schemes of Dynamic Memory Allocation
( works well with an embedded system )

Swapping

Overlays

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 Multiprogramming

Scheme is useful, if number of tasks are

known in advance.
For this, user space is divided into a fixed sized
partitions as shown...

Case I: System using fixed size partitions of 2K

let 3 jobs viz: J1-1.5K, J2-0.5K & J3-2.1K
brought into memory

Case II: System using variable size partitions of 2K

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Embedded System Design
(10EC74)

Unit - 04

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 VTU Syllabus

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 Unit-04
System Design & Development

Best Design is of little value, if no one is willing to buy it!!!!!

Best Design – Robust & well Documented

Getting ready

The problem may not be what it seems at first blush.

Always look for the Second Right Answer

---- by Roger Van Oeah

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 Getting Started Designing & developing ES requires:

Some of the decisions requires the knowledge of the problem

Some have methods for approaching the solution

requires the knowledge of tools, techniques, available

to move from requirements to application is called

------------------ product life cycle

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 Unit-04
Life Cycle Models:

Product life cycle of an ES application breaks the development process into a

series of interrelated activities.
Each activity transforms its i/p into an o/p.
Steps are organized as per the “ design process model – life cycle model “

At the end of the day we just wants know ...

What customers wants?
Think of a way to give them what they want.
Prove what you have done by building & testing it
Build a lot of the product to prove that it won’t an accident
Use the product to solve the customer’s problem

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 Will start with any stage/ phase/ step of engineering

(1) Hockey Stick Model

Why reliability & Safety are important in early stages of the requirement
specifications & Design phase of life Cycle?

Cost

Time

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 (2) Water-Fall Model

Complete this Phase &

Go on to Next

Recognition of Problems is
delayed until later states of
development, where the
cost of repair is higher

Does not consider the

iterative nature of Real
World

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 (3) V-Cycle Model

Each Development Activity Builds a more Detailed Model of the System

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 (4) Spiral Model

As it is proposed by Barry Boehm, it is also

called Boehm’s Model

It is Risk Oriented View of development

Cycle

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 Advantages:
Spiral model is an improvement over the Water-Fall Model & V-Model
because, it provides for multiple builds with many opportunities for RISK
assessment & customer involvement

Disadvantages:
This method is elaborate, difficult to manage & does not keep all developers
occupied during all the phases

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 (5) Rapid- Prototyping-Incremental

Provides rapid implementation of high level portions of both H/D & S/F
in early stages of the development cycle
It allows the developers to construct working portions of the hardware &
software in incremental stages

Each stage has Design, Code & Unit Test, Integration test, Delivery
Thus it allows one to identify the major problems in the early stages

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 Advantages
Customer benefits with an option to work with a functional unit much earlier
in development cycle
Feed back from customer encourages reverse flow through the process
Thus it can be used to refine or change the prototype to meet the real needs of
the customer

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 Unit-04
Problem Solving – 5 Steps to Design

Requirements Definition

System Specification

Functional Design

Architectural Design

Prototyping

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 Unit-04
Design Process

Design process related with how one particular model approaches the
interpretation of 5-Steps Design.

1) Requirements Definition capturing & formalizing the external

behavior of the system
2) System Specification

3) Functional Design

4) Architectural Design move inside the system, & repeat the process
for the internal implementation to meet the
5) Prototyping desired behavior

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 Designing a Counter:
Example
By trip report from High Avionics .Inc.,

Use some instruments on many of their production lines

Wants to improve the Production & Flow process, would like to monitor the
rate at which Units arrive into each of the major assembly areas.
means ... how many navigation radios are coming in each of the Production line
each hour.

As each Radio arrives at an entry point, will break an IR beam;...means... needs

breaking IR beam generators , generating a 1µs wide -Ve going 5V pulse.
Some older lines may require +Ve going Pulse
Some lines have to measure frequency up to 150,000 MHz
For certain tests to measure frequencies in range 50kHz ± 0.001 kHz &
100Hz± 0.001 Hz (may be Periodic or Non-Periodic)
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 Unit-04
1) Requirements Definition Identifying the Requirements
2) System Specification
3) Functional Design
4) Architectural Design
5) Prototyping

To capture the formal description of the complete system from customer’s point
of view

Then, document as written definitions & descriptions

forms the basis for the formal Design Specification

These requirement definitions plays the role between the customer &
people executing the Design

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 Environment & System

Important to consider both the System & the Environment in which it

operates

System & its Environment

Step-0 -Design

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o From the Perspective of the Environment, the requirements definition must
include...
# Specification for the Environment
# Description of i/p’s & o/p’s through Environment
# Description of necessary behavior of the system
# Description of how the system is to be used

o From the System’s point of view, begins with high level abstraction
with outside view having proper definitions.
o then moving to lower levels of abstraction with more detailed definition

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o After transforming the definition of requirements into specification, will now
focus on High-Level-Behavior of the system

o The complete, accurate & internally consistent specification leads to start

Formal Design (executable & able to work with modeling tool suite)

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 Unit-04
Formulating the Requirements Specification

Ultimately it is a Product being delivered but, not a pile of paper

But, as a rule of thumb;

Specification should be the absolute minimum necessary to capture
& clearly identify all of the necessary requirements

are not discussing about microprocessors,

any development process
..etc..

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 To begin with....

Inputs
Environment System
Outputs

1) Description of all 1) Description of all i/p’s

relevant Entities & & o/p’s with complete
behaviors of all description of the
Activities Functional &
2) how Environment is Operational behaviors
interacting with the
system
How to get
3) effects of Environment TECHNOLOGICAL CONSTRAINTS
such
by the o/p’s from the
information?
System

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1) Environment

Identify all the Entities of the Environment & then characterize their effects
on the System

Characterizing the External Entities or Environment

Each entity that make up the environment is described by the name & Public
Interface consisting of i/p’s , o/p’s & its functional behavior

a) Name & Description of the Entity: (rudder on an Air Craft)

b) Responsibilities - Activities: the actions expected from the environment

( Hydraulic System moving the rudder )

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c) Relationships:
* relationships between the entity & it’s activities
* accessing the relationship is responding
* is it producer or consumer !..

d) Safety & Reliability: to identify all the safety critical issues in the System
Specification Design

2) System To identify all the factors of the public interface of the system &
then characterize their effects on the environment

Characterizing the System

a) System i/p’s & o/p’s: the system interacts with the real world through the
entities described & defined in the environment
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 may include like...
the name of the signal
use of the signal as input or output
nature of the signal as an event, data, state variable ..

b) Responsibilities & Activities :

The functional description defines the external behavior of the system.....
Functional description can be captured by the state charts & control flow graphs
Then will go for formulating these diagrams & specifications

c) Safety & Reliability:

Safety considerations includes, safety guide lines, rules/regulations under
governing agencies....etc..
Reliability includes, the system’s potential risks, failures & management strategy
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 Unit-04
System Design Specification

It tells about how of the Design? but, not what Design is?

Master1:
must specify the system’s public interface

Outside View of
the System

Inside View of Design

the System Specification
Master2:
must specify how requirements
defined for the system’s public
interface
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Quantifying the System’s Requirements:

1) System’s Inputs & Outputs:

2) Responsibilities & Activities

3) Responsibilities & Actions a) Geographical Constraints

4) Operational Specifications b) Constraints on Interface Signals

5) Functional Specifications c) User-Interface Requirements

6) Technological Specifications d) Electrical-Interface Requirements

7) Safety & Reliability

Prof G B Gour 26
 Unit-04
System Specification V/s System Requirements

Requirements gives a Description of Customers Needs

It tells about what system must do? & how well it has to do ?
but not how it does?

System Design Specification tells about how to implement the requirements?

means...
translating the description of needs into a more formal structure & model ...
focus on the complete description of public interface...

The specification document should include..

complete, consistent, comprehensive, traceable to requirements, unambiguous,
modifiable & able to be written
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 Unit-04
Prototyping & Decomposing a System

1) Coupling:
* an estimate of interdependency of the modules
* lower the Coupling, better the job done during partitioning
* how to reduce the coupling? then...

2) Cohesion:
* it will bring the pieces together instead of partitioning..
* is measure of strength of the functional relatedness of elements in
the module
* idea is to create strong, high cohesive modules

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 Unit-04
Functional Design:

Main objective:
* To find internal functional architecture for the system
by formulating the implementation of the Requirements
by the analysis of loose understanding of Design transformed into a
Precise Description

means, Detailed Textual or Graphical description of the system is needed

Example: Aircraft Design

Advantages:
* Early Flexibility
* Time to explore before beginning to constraint system

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 Role of Engineers:
Detailed Textual Functional description is to be understood by those in Application
Domain ( who will be doing HD/SF development)

Functional Decomposition:
•1st Functional decomposition is done by finding IMP internal variables & events
in the system.
Followed by successive Decomposition for each function until will get elementary
functions (forms Functional Model of the System )

Modeling & Verification:

here system’s operations & associated performance requirements can be allocated
to the internal functions &
relations between such functions can be defined.
( this allows expected performance of the system )

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Ideally the functional Model should be executable, to allow verification w.r.t
specification
Example: one such tool behavioral Verilog model

Example of Counter design to be followed

System to be Designed later

Initial Decomposition followed...

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Functional Partitioning & Signal Flow between the major functional blocks

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 Unit-04
Architectural Design:
Goal:
1. To select the most appropriate solution to the original problem(s), based on
variety of architectures
2. Choice of the best suited HD/SF partitioning & allocation of the functionality

Mapping Functions to Hardware:

1. Describes the complete hardware implementation of the system
2. Performance requirements are analyzed & constraints are imposed..like..
Geographical distribution
Physical 7 User Interfaces
Timing constraints & Dependability requirements
Power consumption
Legacy components & cost
System performance & specification

This decides which parts to be implemented in H/D & S/F

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 H/D portion of the system is specified
by a physical architecture with one or
Part I more microprocessors, complex logic
devices & custom ICs

Part II To make decisions about Size, Weight,

Cost, Speed ..etc...

Part III
S/F Part is concurrently developed
Decide about the Real time Kernel
( Co-Design)

idea: is to reduce the size & complexity of the S/F,

developing, testing , debugging Times
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Prof G B Gour 37
 Unit-04
Functional Model V/s Architectural Model

1) Functional Model describes a system by a set of interacting functional elements.

Architectural Model describes the physical architecture of the system based on

real components like microprocessors, analog or digital components...

2) Functional Model, is the basis for a Coarse-grain partitioning of the system

Architectural Model, is Finer-grained & follows from functional model

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 Unit-04
Prototyping:

Prototyping is a proof of concept: ..includes...

Detailed design, Debugging, Validation, Testing

what it means w.r.t small projects & large projects

Prototyping is a Bottom-Up Process:

Resulting Prototype can be Verified

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 Unit-04
Archiving the Project:

When the product is finally released to production, still some work ha been left...?

Means:
During development, lot of information is produced, some of it used/unused,
then what must be saved for future revisions? ARCHIVING

Example: a typical S/F project directory may includes...

source, binaries, Libraries, Tools, Make files, Specifications, Documentation

Why Archiving is required?

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END of UNIT-04

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