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TIOL111
SLLSEV5B – JULY 2017 – REVISED AUGUST 2018
VCC_OUT L+
VOLTAGE
REGULATOR
1 µF 0.1 µF
10 V 100 V
10 NŸ
RX
10 NŸ
TX
CONTROL
Sensor
Microcontroller
LOGIC
Front-End EN CQ
IO-Link Master
DIAGNOSTICS
WAKE and
CONTROL
NFAULT
CUR_OK
TMP_OK L-
PWR_OK
ILIM_ADJ
RSET
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TIOL111
SLLSEV5B – JULY 2017 – REVISED AUGUST 2018 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 12
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 17
3 Description ............................................................. 1 9 Application and Implementation ........................ 19
4 Revision History..................................................... 2 9.1 Application Information............................................ 19
9.2 Typical Application ................................................. 19
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 10 Power Supply Recommendations ..................... 23
6.1 Absolute Maximum Ratings ...................................... 4 11 Layout................................................................... 24
6.2 ESD Ratings.............................................................. 4 11.1 Layout Guidelines ................................................. 24
6.3 Recommended Operating Conditions....................... 4 11.2 Layout Example .................................................... 24
6.4 Thermal Information .................................................. 5 12 Device and Documentation Support ................. 25
6.5 Electrical Characteristics........................................... 5 12.1 Receiving Notification of Documentation Updates 25
6.6 Switching Characteristics .......................................... 7 12.2 Community Resources.......................................... 25
6.7 Typical Characteristics .............................................. 8 12.3 Trademarks ........................................................... 25
7 Parameter Measurement Information .................. 9 12.4 Electrostatic Discharge Caution ............................ 25
12.5 Glossary ................................................................ 25
8 Detailed Description ............................................ 11
8.1 Overview ................................................................. 11 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagrams ..................................... 11
Information ........................................................... 25
4 Revision History
Changes from Revision A (October 2017) to Revision B Page
DMW Package
10-Pin (VSON)
Top View
VCC_IN/OUT 1 10 WAKE
NFAULT 2 9 L+
Thermal
RX 3 8 CQ
Pad
TX 4 7 L-
EN 5 6 ILIM_ADJ
Not to scale
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
IO-Link Interface
CQ 8 I/O IO-Link data signal (bidirectional)
L+ 9 POWER IO-Link supply voltage (24 V nominal)
L- 7 POWER IO-Link ground potential
Local Controller Interface
Driver enable input signal from the local controller. Logic low sets the CQ output at Hi-Z. Weak internal pull-
EN 5 I
down.
WAKE 10 OPEN-DRAIN Wake up indicator to the local controller. Connect this pin via pull-up resistor to VCC_IN/OUT.
RX 3 O Receive data output to the local controller
Transmit data input from the local controller. No effect if EN is low. Logic high sets low-side switch. Logic low
TX 4 I
sets high-side switch. Weak internal pull-up.
Thermal Pad — — Connect to L- for optimal thermal and electrical performance
Internal LDO
VCC_IN/OUT 1 POWER 3.3-V or 5-V linear regulator output; external 3.3-V or 5-V logic supply for option without LDO.
Special Connect Pins
ILIM_ADJ 6 I Input for current limit adjustment. Connect resistor RSET between ILIM_ADJ and L-.
Fault indicator output signal to the microcontroller. A low level indicates either an over- current, an
NFAULT 2 OPEN-DRAIN
undervoltage supply or an overtemperature condition.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Steady state voltage for L+ and CQ –55 55 V
Supply voltage
Transient pulse width < 100 µs for L+ and CQ –65 65 V
Voltage difference |V(L+) – V(CQ)| 55 V
Logic supply voltage (TIOL111) VCC_IN –0.3 6 V
Input logic voltage TX, EN, ILIM_ADJ –0.3 6 V
Output current RX, WAKE, NFAULT –5 5 mA
Storage temperature, Tstg -55 170 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are
with reference to the L- pin, unless otherwise specified.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Minimum 100-nF capacitor is required between L+ and L-. Minimum 1-µF capacitor is required between VCC_IN/OUT and L-.
(3) Passing level is ±4500 V if the device is powered and EN=TX=HIGH.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(1) Current fault indication will be active. Current fault auto recovery will be de-activated.
Leakage current in reverse EN = LOW, TX=x; V(CQ) < V(L-) or V(CQ) > V(L+),
IREV 80 µA
polarity up to |55 V|
EN = HIGH, TX = LOW; V(CQ to L+) = 3 V 550 µA
EN = HIGH, TX = HIGH; V(CQ to L-) = -3 V 10 µA
LINEAR REGULATOR (LDO)
TIOL111-5 4.75 5 5.25 V
V(VCC_OUT) Voltage regulator output
TIOL111-3 3.13 3.3 3.46 V
Voltage regulator drop-out TIOL111-5 1.9 V
V(DROP) voltage ICC = 20 mA load current
(V(L+) – V(VCC_OUT)) TIOL111-3 2.3 V
Line regulation
REG I(VCC_OUT) = 1 mA 1.7 mV/V
(dV(VCC_OUT)/dV(L+))
Load regulation
LREG V(L+) = 24 V, I(VCC_OUT) = 100 µA to 20 mA 1%
(dV(VCC_OUT)/V(VCC_OUT))
PSSR Power Supply Rejection Ratio 100 kHz, I(VCC_OUT) = 20 mA 40 dB
3 1.8
1.6
2.5
1.4
L+ Supply Current (mA)
1
1.5
0.8
1 0.6
0.4
0.5 -40qC
En=High 0.2 25qC
En=Low 125qC
0 0
0 10 20 30 40 0 50 100 150 200 250
L+ Supply Voltage (V) D001
Load Current (mA) D002
No Load TX = Open 25°C
Figure 1. Supply Current vs Supply Voltage Figure 2. Residual Voltage vs Load Current: High Side
1.6 400
Low Side
1.4 350 High Side
1.2 300
Residual Voltage (V)
1 250
IO(LIM) (mA)
0.8 200
0.6 150
0.4 100
-40qC
0.2 25qC 50
125qC
0 0
0 50 100 150 200 250 0 20 40 60 80 100
Load Current (mA) D003
RSET (k:) D004
Figure 3. Residual Voltage vs Load Current: Low Side Figure 4. Current Limit vs RSET
14
13
12
Receiver Threshold (V)
11
10
9
8
7
6
5 VTHH
VTHL
4
7 9 11 13 15 17 19 21 23 25 27 29 31 33 35
L+ Voltage (V) D005
RL
TX CQ
RL CL
EN
VOH VOH
80% 80%
TX 50%
tPHL tPLH CQ CQ
VOH
CQ 50%
20% 20%
VOL VOL VOL
tr tf
TX = HIGH TX = LOW
EN 50% EN 50%
80%
CQ 50% CQ 50%
20%
VOL
V(L+) / 2
CQ 50%
tPLH tPHL
RX 50%
RX RX RX
high high
WAKE WAKE WAKE
tpWAKE
high high
NFAULT NFAULT NFAULT
tpSC
a) Over-current due to transient b) Wake-up pulse from master c) Over-current due to fault condition
8 Detailed Description
8.1 Overview
Figure 11 shows that the TIOL111 or TIOL111-x driver output (CQ) can be used in either push-pull, high-side, or
low-side configuration using the enable (EN) and transmit data (TX) input pins. The internal receiver converts the
24-V signal on the CQ line to standard logic levels on the receive data (RX) pin. A simple parallel interface is
used to receive/transmit data and status information between the slave and the local controller.
These devices have integrated IEC 61000-4-4/5 EFT and surge protection. In addition, tolerance to ±65-V
transients enables flexibility to choose from a wider range of TVS diodes if an application requires higher levels
of protection. These integrated robustness features will simplify the system level design by reducing external
protection circuitry.
TIOL111 or TIOL111-x transceivers implement protection features for overcurrent, overvoltage and over-
temperature conditions. The devices also provide a current-limit setting of the driver output current using an
external resistor.
The devices derive the low-voltage supply from the IO-Link L+ voltage (24 V nominal) via an internal linear
regulator to provide power to the local controller and sensor circuitry.
VCC_ IN L+
RX
CONTROL
TX
LOGIC
CQ
EN
DIAGNOSTICS
WAKE
and
CONTROL
NFAULT
CUR_OK
TMP_OK
PWR_OK L-
ILIM_ADJ
VOLTAGE
VCC_OUT L+
REGULATOR
RX
CONTROL
TX
LOGIC
EN CQ
DIAGNOSTICS
WAKE and
CONTROL
NFAULT
CUR_OK
TMP_OK
PWR_OK L-
ILIM_ADJ
Copyright © 2016, Texas Instruments Incorporated
Receive
Only
CUR_OK = Z
WAKE = Z
Driver = OFF
LDO = ON
Receive and
Wake
Transmit
WAKE = L CQ at IO(LIM) CUR_OK = Z
CUR_OK = Z
for tWU1 < t < tWU2 WAKE = Z
Driver = ON
and RX ≠TX Driver = ON
LDO = ON
LDO = ON
CQ at IO(LIM)
for t > tSC
T > TWRN
CQ
at
IO
(LI
M)
CQ NOT at IO(LIM)
Thermal Current
Warning
T > TWRN Fault
CUR_OK = Z
WAKE = Z
TMP_OK = L
CQ at IO(LIM) and T < TWRN CUR_OK = L
WAKE = Z
Driver = OFF
Driver = EN/EN*
LDO=ON
LDO = ON
T < (TSD + THYS )
t = tSCE N
T > TSD
CQ at IO(LIM)
Thermal Current
Shutdown Fault Recovery
CUR_OK = Z WAKE = Z
TMP_OK = L CUR_OK = L
WAKE = Z Driver = ON for ts c
Driver = OFF LDO=ON
LDO = ON
L+ L+
DC DC
CQ CQ
TIOL 111 TIOL 111
RL RL
L- L-
L+ L+
DC DC
CQ CQ
TIOL 111 TIOL 111
RL RL
L- L-
L+ L+
DC DC
CQ CQ
TIOL 111 TIOL 111
RL RL
L- L-
L+ L+
DC DC
CQ CQ
TIOL 111 TIOL 111
RL RL
L- L-
L+ L+
DC DC
CQ CQ
TIOL 111 TIOL 111
RL RL
L- L-
L+ L+
DC DC
CQ CQ
TIOL 111 TIOL 111
RL RL
L- L-
Combination R
wave
Generator
EUT
L+
Equipment
Equipment
Protection
Auxiliary
CQ
Decoupling > 100 nF
Network L-
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
TIOL111-x
VCC_OUT L+
VOLTAGE
REGULATOR
1 µF 0.1 µF
10 V 100 V
10 NŸ
RX
10 NŸ
TX
CONTROL
Sensor
Microcontroller
LOGIC
Front-End EN CQ
IO-Link Master
DIAGNOSTICS
WAKE and
CONTROL
NFAULT
CUR_OK
TMP_OK L-
PWR_OK
ILIM_ADJ
RSET
L+ L+
CQ CQ
L L
10 V/div
8 V/div
10 V/div
4 V/div
3 V/div
Time 1 Ps/div Time 10 ms/div
125 kHz
Figure 20. CQ in Communication Mode Figure 21. CQ Power Up Delay, Low Side Mode
700 mV/div
10 V/div
300 mA/div
10 V/div
3 V/div
4 V/div
Figure 22. CQ Power Up Delay, High Side Mode Figure 23. CQ in Current Fault, Low Side Mode
5 V/div
6 V/div
300 mA/div
300 mA/div
4 V/div
4 V/div
Figure 24. CQ in Current Fault, High Side Mode Figure 25. CQ in Current Fault Auto Recovery,
Low Side Mode
6 V/div
8 V/div
300 mA/div
2 V/div
4 V/div
Figure 26. CQ in Current Fault Auto Recovery, Figure 27. IO-Link WAKE, Low Side Mode
High Side Mode
2 V/div
8 V/div
40 V/div
2 V/div
3 V/div
Time 10 ms/div
Time 20 Ps/div
1.5-H Inductor With 100 Ω RSET = OPEN
Time 10 ms/div
1.5-H Inductor With 100 Ω RSET = OPEN
11 Layout
WAKE
1uF/10V
100nF/
VC
50V
C
_I
N
/O
NFAULT
U
T
L+
L+
RX CQ
CQ
TX L-
ILIM_ADJ
EN
L-
12.3 Trademarks
E2E is a trademark of Texas Instruments.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 24-Aug-2018
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TIOL1113DMWR ACTIVE VSON DMW 10 1500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TL1113
& no Sb/Br)
TIOL1113DMWT ACTIVE VSON DMW 10 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TL1113
& no Sb/Br)
TIOL1115DMWR ACTIVE VSON DMW 10 1500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TL1115
& no Sb/Br)
TIOL1115DMWT ACTIVE VSON DMW 10 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TL1115
& no Sb/Br)
TIOL111DMWR ACTIVE VSON DMW 10 1500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TL111
& no Sb/Br)
TIOL111DMWT ACTIVE VSON DMW 10 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TL111
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Aug-2018
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Aug-2018
Pack Materials-Page 2
PACKAGE OUTLINE
DMW0010A SCALE 4.000
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
3.1 A
B
2.9
1 MAX C
SEATING PLANE
0.08 C
5 6
2X 11 SYMM
2
1.95 0.1
1
10
8X 0.5
0.475 0.29
10X 10X
PIN 1 ID 0.275 0.19
(OPTIONAL) 0.1 C A B
0.05 C
4223225/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DMW0010A VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
10X (0.575)
(0.575)
1
10
10X (0.24)
(0.725)
11 SYMM
(1.95)
8X (0.5)
(R0.05) TYP
5 6
( 0.2) VIA
SYMM
TYP
(2.825)
4223225/A 08/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DMW0010A VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.24)
(0.535)
SYMM
8X (0.5)
(0.87)
(R0.05) TYP
5 6
2X (1.5)
(2.825)
EXPOSED PAD 11
81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4223225/A 08/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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