La B843P

5 4 3 2 1
D D
Iris HSW/BDW Schematics

Broadwell-ULT
C 2015-01-20 C
REV : A00
B B
A DY : None Installed A
UMA: UMA only installed

Compal Secret Data Compal Electronics, Inc.
OPS: DISCRTE OPTIMUS installed Security Classification
Issued Date 2015/01/20 Deciphered Date 2015/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B483P
Date: W ednesday, January 21, 2015 Sheet 1 of 102
5 4 3 2 1
5 4 3 2 1
CHARGER
HPA02224RGRR-1-GP 44
Project code:
INPUTS OUTPUTS
Iris-2 14 --> 4PD031010001
Iris-2 15 --> 4PD032010001 Iris2/Tulip/VanGogh Block Diagram AD+
BT+
DCBATOUT
PCB P/N: 14216 SYSTEM DC/DC

TPS51225RUKR-GP 45
Revision: X01 INPUTS OUTPUTS
3D3V_AUX_S5
D 5V_AUX_S5 D
DCBATOUT 5V_S5
DDR3L 3D3V_S5
GPU DDR3L 1333/1600MHz Channel A
1333/1600
CPU Core Power
NVIDIA SODIMM A ISL95813HRZ-GP 46,47
33
VRAM(DDR3L) *8 N15V-GM-S-A2 (14"/15") Intel CPU 12
PCIE x 4 INPUTS OUTPUTS
1GB, 2GB (Reserve 4GB) (23x23) 25W
78,79,80,81 DDR3L Reserve N16V-GM Broadwell ULT DCBATOUT VCC_CORE
73,74,75,76,77 28W (UMA) DDR3L DDR3L SUS

15W (DIS) 1333/1600 TPS51716RUKR-GP 49
DIS only DDR3L 1333/1600MHz Channel B
INPUTS OUTPUTS
SODIMM B
12 DCBATOUT 1D35V_S3
DP/VGA Converter WPT-LP 0D675V_S0

VGA Conn. VGA DDI1
8 USB 2.0/1.1 ports CPU 1.05V
Reserve for Vostro 55 REALTEK RTD2168-CGT 55 4 USB 3.0 ports LAN 10/100 RT8237CZQW-2-GP 48
PCIE x 1 RJ45
Co-lay High Definition Audio RealTek RTL8106E INPUTS OUTPUTS
4 SATA ports Reserve RTL8111G for Giga Conn. DCBATOUT 1D05V_S0
HDMI V1.4a HDMI 8 PCIE ports
30
54 LPC I/F CPU 1D5V_S0
C
TLV70215DBVR-GP 51 C
ACPI 4.0a
INPUTS OUTPUTS
PCIE x 1 NGFF WLAN 3D3V_S5 1D5V_S0
Iris2 : 14"/15" LCD eDP 802.11a/b/g/n Switches 36 83
Tulip : 14"/15"/17" LCD USB2.0 x 1 BT V4.0 combo 58 INPUTS OUTPUTS
52 AC 3160
1D35V_S3 1D35V_S0
Touch Panel USB2.0 x 1 5V_S5 5V_S0
LPC BUS 3D3V_S5 3D3V_S0

LPC debug port
65 1D05V_S0 1D05V_VGA_S0
3D3V_S0 3D3V_VGA_S0
Camera 1D35V_S3 1D35V_VGA_S0
USB2.0 x 1
Digital MIC 52 SMBUS Thermal
NUVOTON
KBC NCT7718W 26
NUVOTON PCB LAYER
HDA NPCE285P B2 Version Fan Control
2CH SPEAKER 24 L1:Top
ANPEC
(2CH 2W/4ohm) CODEC APL5606AKI L2:VCC
26
HDA L3:Signal
B Realtek SPI
L4:Signal B
L5:GND
ALC3234 27 L6:Signal
29
PS2 Int. FAN
26
MIC_IN/GND SPI Flash ROM KB 62
8MB 25
HP_R/L
29
Universal Jack
Touch PAD
USB2(USB2.0) I2C Image sensor
USB2.0 x 1 62
IOBD 4
IO Board USB3(USB2.0) USB2.0 x 1

IOBD 4 SATA(Gen3) x 1 HDD
56
Left side
A
USB2.0 x 1 A
USB1(USB3.0) SATA(Gen1) x 1 ODD

Reserve 56
34,35
USB3.0 x 1
CardReader Security Classification Compal Secret Data Compal Electronics, Inc.

USB2.0 x 1 2015/01/20 2015/12/31 Title
Realtek SD Card Slot Issued Date Deciphered Date
Block Diagram
RTS5170 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A00
LA-B483P
Date: Wednesday, January 21, 2015 Sheet 2 of 102
5 4 3 2 1
62
5 4 3 2 1
D D
(Blanking)
C C
B B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = CPU

1D05S_VCCST
RN401
For EMI Reserved XDP_TMS 1 8
XDP_TDI 2 7
D H_CPUPWRGD EC401 1 2 SCD1U16V2KX-3GP 3 6 D
@EMI@ XDP_TDO 4 5
XDP_TRST# EC402 1 2 SCD1U16V2KX-3GP SRN51J-1-GP @

@EMI@
@
XDP_TRST# R402 1 2 51R2J-2-GP
XDP_TCLK R406 1 2 51R2J-2-GP
1D05S_VCCST
HSW_ULT_DDR3L
CPU1B 2 OF 19
Remove TP401 for TP604 spacing.
1
R401 D61
62R2J-GP 1 H_CATERR# K61 PROC_DETECT# MISC
N62 CATERR# J62 XDP_PRDY#
C
Layout Note: <24> H_PECI PECI PRDY# K62 XDP_PREQ#
XDP_PRDY# <96>
XDP_PREQ# <96> C
2
TP402 PREQ# E60 XDP_TCLK

Impedance control:50 ohm PROC_TCK XDP_TCLK <96>
TPAD14-OP-GP E61 XDP_TMS
JTAG PROC_TMS XDP_TMS <96>
1 2 H_PROCHOT#_R K63 E59 XDP_TRST# XDP_TRST# <96>
<24,42,43,48> H_PROCHOT# PROCHOT# PROC_TRST#
R403 THERMAL F63 XDP_TDI XDP_TDI <96>
156R2J-4-GP PROC_TDI F62 XDP_TDO
PROC_TDO XDP_TDO <96>
1
DY 2 H_CPUPWRGD C61
<36> H_THERMTRIP_EN R411 TP403 PROCPWRGD PWR XDP_BPM[7:0]
R405 XDP_BPM[7:0] <96>
TPAD14-OP-GP
2 1 J60 XDP_BPM0
0R2J-2-GP BPM#0 H60 XDP_BPM1
10KR2J-3-GP BPM#1
Layout Note: Close to CPU H61 XDP_BPM2
BPM#2 H62 XDP_BPM3
SM_RCOMP_0 AU60 BPM#3 K59 XDP_BPM4
SM_RCOMP_1 AV60 SM_RCOMP0 DDR3L BPM#4 H63 XDP_BPM5
SM_RCOMP_2 AU61 SM_RCOMP1 BPM#5 K60 XDP_BPM6
SM_DRAMRST# AV15 SM_RCOMP2 BPM#6 J61 XDP_BPM7
DDR_PG_CTRL AV61 SM_DRAMRST# BPM#7
<12> DDR_PG_CTRL SM_PG_CNTL1
B B
HASWELL-6-GP-U
@ 1D35V_S3
R407 1 2 200R2F-L-GP SM_RCOMP_0
Layout Note:
R408 1 2 121R2F-GP SM_RCOMP_1 Place close to DIMM
R409 1 2 100R2F-L1-GP-U SM_RCOMP_2 1 R410
470R2J-2-GP
2
@
SM_DRAMRST# R404 1 2 0_0402_1% DDR3_DRAMRST# <12,13>
Short Pad
Layout Note:
Design Guideline:
SM_RCOMP keep routing length less than 500 mils.
A A

CPU (THERMAL/MISC/PM)
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
DDR3L ball type: Non-Interleaved Type

HSW_ULT_DDR3L 3 OF 19
CPU1C
M_A_DQ[63:0] CPU1D HSW_ULT_DDR3L 4 OF 19

<12> M_A_DQ[63:0] AH63 AU37
M_A_DQ0
M_A_DQ1 AH62 SA_DQ0 SA_CLK#0 AV37 M_A_DIMA_CLK_DDR#0 <12>
D D
M_A_DQ2 AK63 SA_DQ1 SA_CLK0 AW36 M_A_DIMA_CLK_DDR0 <12> M_B_DQ[63:0]
M_A_DQ3 AK62 SA_DQ2 SA_CLK#1 AY36 M_A_DIMA_CLK_DDR#1 <12> <13> M_B_DQ[63:0] M_B_DQ0 AY31 AM38
M_A_DQ4 AH61 SA_DQ3 SA_CLK1 M_A_DIMA_CLK_DDR1 <12> M_B_DQ1 AW31 SB_DQ0 SB_CK#0 AN38 M_B_DIMB_CLK_DDR#0 <13>
M_A_DQ5 AH60 SA_DQ4 AU43 M_B_DQ2 AY29 SB_DQ1 SB_CK0 AK38 M_B_DIMB_CLK_DDR0 <13>
M_A_DQ6 AK61 SA_DQ5 SA_CKE0 AW43 M_A_DIMA_CKE0 <12> M_B_DQ3 AW29 SB_DQ2 SB_CK#1 AL38 M_B_DIMB_CLK_DDR#1 <13>
M_A_DQ7 AK60 SA_DQ6 SA_CKE1 AY42 M_A_DIMA_CKE1 <12> M_B_DQ4 AV31 SB_DQ3 SB_CK1 M_B_DIMB_CLK_DDR1 <13>
M_A_DQ8 AM63 SA_DQ7 SA_CKE2 AY43 M_B_DQ5 AU31 SB_DQ4 AY49
M_A_DQ9 AM62 SA_DQ8 SA_CKE3 M_B_DQ6 AV29 SB_DQ5 SB_CKE0 AU50 M_B_DIMB_CKE0 <13>
M_A_DQ10 AP63 SA_DQ9 AP33 M_B_DQ7 AU29 SB_DQ6 SB_CKE1 AW49 M_B_DIMB_CKE1 <13>
M_A_DQ11 AP62 SA_DQ10 SA_CS#0 AR32 M_A_DIMA_CS#0 <12> M_B_DQ8 AY27 SB_DQ7 SB_CKE2 AV50
M_A_DQ12 AM61 SA_DQ11 SA_CS#1 M_A_DIMA_CS#1 <12> M_B_DQ9 AW27 SB_DQ8 SB_CKE3
M_A_DQ13 AM60 SA_DQ12 AP32 TP_M_A_DIMA_ODT0 1 M_B_DQ10 AY25 SB_DQ9 AM32
M_A_DQ14 AP61 SA_DQ13 SA_ODT0 M_B_DQ11 AW25 SB_DQ10 SB_CS#0 AK32 M_B_DIMB_CS#0 <13>
M_A_DQ15 AP60 SA_DQ14 AY34 M_B_DQ12 AV27 SB_DQ11 SB_CS#1 M_B_DIMB_CS#1 <13>
SA_DQ15 SA_RAS# M_A_RAS# <12> SB_DQ12
M_A_DQ16 AP58 AW34 TP501 M_B_DQ13 AU27 AL32 TP_M_B_DIMB_ODT0 1
SA_DQ16 SA_WE# M_A_WE# <12> SB_DQ13 SB_ODT0
M_A_DQ17 AR58 AU34 TPAD14-OP-GP M_B_DQ14 AV25
SA_DQ17 SA_CAS# M_A_CAS# <12> SB_DQ14
M_A_DQ18 AM57 M_B_DQ15 AU25 AM35
SA_DQ18 SB_DQ15 SB_RAS# M_B_RAS# <13>
M_A_DQ19 AK57 AU35 M_B_DQ16 AM29 AK35 TP503
SA_DQ19 SA_BA0 M_A_BS0 <12> SB_DQ16 SB_WE# M_B_WE# <13>
M_A_DQ20 AL58 AV35 M_B_DQ17 AK29 AM33 TPAD14-OP-GP
SA_DQ20 SA_BA1 M_A_BS1 <12> SB_DQ17 SB_CAS# M_B_CAS# <13>
M_A_DQ21 AK58 AY41 M_B_DQ18 AL28
SA_DQ21 SA_BA2 M_A_BS2 <12> SB_DQ18
M_A_DQ22 AR57 M_B_DQ19 AK28 AL35
SA_DQ22 M_A_A[15:0] <12> SB_DQ19 SB_BA0 M_B_BS0 <13>
M_A_DQ23 AN57 AU36 M_A_A0 M_B_DQ20 AR29 AM36
SA_DQ23 SA_MA0 SB_DQ20 SB_BA1 M_B_BS1 <13>
M_A_DQ24 AP55 AY37 M_A_A1 M_B_DQ21 AN29 AU49
SA_DQ24 SA_MA1 SB_DQ21 SB_BA2 M_B_BS2 <13>
M_A_DQ25 AR55 AR38 M_A_A2 M_B_DQ22 AR28
M_A_DQ26 AM54 SA_DQ25 SA_MA2 AP36 M_A_A3 M_B_DQ23 AP28 SB_DQ22 AP40 M_B_A0 M_B_A[15:0] <13>
M_A_DQ27 AK54 SA_DQ26 SA_MA3 AU39 M_A_A4 M_B_DQ24 AN26 SB_DQ23 SB_MA0 AR40 M_B_A1
M_A_DQ28 AL55 SA_DQ27 SA_MA4 AR36 M_A_A5 M_B_DQ25 AR26 SB_DQ24 SB_MA1 AP42 M_B_A2
M_A_DQ29 AK55 SA_DQ28 SA_MA5 AV40 M_A_A6 M_B_DQ26 AR25 SB_DQ25 SB_MA2 AR42 M_B_A3
M_A_DQ30 AR54 SA_DQ29 SA_MA6 AW39 M_A_A7 M_B_DQ27 AP25 SB_DQ26 SB_MA3 AR45 M_B_A4
M_A_DQ31 AN54 SA_DQ30 DDR CHANNEL A SA_MA7 AY39 M_A_A8 M_B_DQ28 AK26 SB_DQ27 SB_MA4 AP45 M_B_A5
M_A_DQ32 AY58 SA_DQ31 SA_MA8 AU40 M_A_A9 M_B_DQ29 AM26 SB_DQ28 SB_MA5 AW46 M_B_A6
M_A_DQ33 AW58 SA_DQ32 SA_MA9 AP35 M_A_A10 M_B_DQ30 AK25 SB_DQ29 SB_MA6 AY46 M_B_A7
M_A_DQ34 AY56 SA_DQ33 SA_MA10 AW41 M_A_A11 M_B_DQ31 AL25 SB_DQ30 SB_MA7 AY47 M_B_A8
M_A_DQ35 AW56 SA_DQ34 SA_MA11 AU41 M_A_A12 M_B_DQ32 AY23 SB_DQ31 DDR CHANNEL B SB_MA8 AU46 M_B_A9
M_A_DQ36 AV58 SA_DQ35 SA_MA12 AR35 M_A_A13 M_B_DQ33 AW23 SB_DQ32 SB_MA9 AK36 M_B_A10
M_A_DQ37 AU58 SA_DQ36 SA_MA13 AV42 M_A_A14 M_B_DQ34 AY21 SB_DQ33 SB_MA10 AV47 M_B_A11
M_A_DQ38 AV56 SA_DQ37 SA_MA14 AU42 M_A_A15 M_B_DQ35 AW21 SB_DQ34 SB_MA11 AU47 M_B_A12
M_A_DQ39 AU56 SA_DQ38 SA_MA15 M_B_DQ36 AV23 SB_DQ35 SB_MA12 AK33 M_B_A13
SA_DQ39 M_A_DQS#[7:0] <12> SB_DQ36 SB_MA13
M_A_DQ40 AY54 AJ61 M_A_DQS#0 M_B_DQ37 AU23 AR46 M_B_A14
M_A_DQ41 AW54 SA_DQ40 SA_DQSN0 AN62 M_A_DQS#1 M_B_DQ38 AV21 SB_DQ37 SB_MA14 AP46 M_B_A15
M_A_DQ42 AY52 SA_DQ41 SA_DQSN1 AM58 M_A_DQS#2 M_B_DQ39 AU21 SB_DQ38 SB_MA15
C C
SA_DQ42 SA_DQSN2 SB_DQ39 M_B_DQS#[7:0] <13>
M_A_DQ43 AW52 AM55 M_A_DQS#3 M_B_DQ40 AY19 AW30 M_B_DQS#0
M_A_DQ44 AV54 SA_DQ43 SA_DQSN3 AV57 M_A_DQS#4 M_B_DQ41 AW19 SB_DQ40 SB_DQSN0 AV26 M_B_DQS#1
M_A_DQ45 AU54 SA_DQ44 SA_DQSN4 AV53 M_A_DQS#5 M_B_DQ42 AY17 SB_DQ41 SB_DQSN1 AN28 M_B_DQS#2
M_A_DQ46 AV52 SA_DQ45 SA_DQSN5 AL43 M_A_DQS#6 M_B_DQ43 AW17 SB_DQ42 SB_DQSN2 AN25 M_B_DQS#3
M_A_DQ47 AU52 SA_DQ46 SA_DQSN6 AL48 M_A_DQS#7 M_B_DQ44 AV19 SB_DQ43 SB_DQSN3 AW22 M_B_DQS#4
M_A_DQ48 AK40 SA_DQ47 SA_DQSN7 M_B_DQ45 AU19 SB_DQ44 SB_DQSN4 AV18 M_B_DQS#5
SA_DQ48 M_A_DQS[7:0] <12> SB_DQ45 SB_DQSN5
M_A_DQ49 AK42 AJ62 M_A_DQS0 M_B_DQ46 AV17 AN21 M_B_DQS#6
M_A_DQ50 AM43 SA_DQ49 SA_DQSP0 AN61 M_A_DQS1 M_B_DQ47 AU17 SB_DQ46 SB_DQSN6 AN18 M_B_DQS#7
M_A_DQ51 AM45 SA_DQ50 SA_DQSP1 AN58 M_A_DQS2 M_B_DQ48 AR21 SB_DQ47 SB_DQSN7
SA_DQ51 SA_DQSP2 SB_DQ48 M_B_DQS[7:0] <13>
M_A_DQ52 AK45 AN55 M_A_DQS3 M_B_DQ49 AR22 AV30 M_B_DQS0
M_A_DQ53 AK43 SA_DQ52 SA_DQSP3 AW57 M_A_DQS4 M_B_DQ50 AL21 SB_DQ49 SB_DQSP0 AW26 M_B_DQS1
M_A_DQ54 AM40 SA_DQ53 SA_DQSP4 AW53 M_A_DQS5 M_B_DQ51 AM22 SB_DQ50 SB_DQSP1 AM28 M_B_DQS2
M_A_DQ55 AM42 SA_DQ54 SA_DQSP5 AL42 M_A_DQS6 M_B_DQ52 AN22 SB_DQ51 SB_DQSP2 AM25 M_B_DQS3
M_A_DQ56 AM46 SA_DQ55 SA_DQSP6 AL49 M_A_DQS7 M_B_DQ53 AP21 SB_DQ52 SB_DQSP3 AV22 M_B_DQS4
M_A_DQ57 AK46 SA_DQ56 SA_DQSP7 M_B_DQ54 AK21 SB_DQ53 SB_DQSP4 AW18 M_B_DQS5
M_A_DQ58 AM49 SA_DQ57 AP49 +V_SM_VREF_CNT M_B_DQ55 AK22 SB_DQ54 SB_DQSP5 AM21 M_B_DQS6
SA_DQ58 SM_VREF_CA +V_SM_VREF_CNT <37> SB_DQ55 SB_DQSP6
M_A_DQ59 AK49 AR51 M_B_DQ56 AN20 AM18 M_B_DQS7
SA_DQ59 SM_VREF_DQ0 DDR_WR_VREF01 <37> SB_DQ56 SB_DQSP7
M_A_DQ60 AM48 AP51 M_B_DQ57 AR20
SA_DQ60 SM_VREF_DQ1 DDR_WR_VREF02 <37> SB_DQ57
M_A_DQ61 AK48 M_B_DQ58 AK18
M_A_DQ62 AM51 SA_DQ61 M_B_DQ59 AL18 SB_DQ58
M_A_DQ63 AK51 SA_DQ62 M_B_DQ60 AK20 SB_DQ59
SA_DQ63 M_B_DQ61 AM20 SB_DQ60
M_B_DQ62 AR18 SB_DQ61
M_B_DQ63 AP18 SB_DQ62
SB_DQ63
HASWELL-6-GP-U
@ HASWELL-6-GP-U
@
HSW Broadwell
B B
CPU1 4030@ CPU1 BDW_PQS@
CL8064701552900 SR1EN D0 1.9G A31! FH8065801620003 QH15 E0 2.2G
SA00007TA1L SA000083A0L
CPU1 3805@
CPU1 4005@
R3
R3
FH8065801620702 SR210 E0 1.9G FCBGA
CL8064701478404 SR1EK D0 1.7G BGA
SA000083F2L
SA000072Q2L
CPU1 3205@ CPU1 5005@
R3 R3
FH8065801882800 SR215 E0 1.5G FCBGA FH8065801884006 SR244 F0 2G FCBGA
SA000083H1L SA000083E3L
CPU1 5010@
CPU1 5500@
R3
R3
A A
FH8065801620406 SR23Z F0 2.1G FCBGA
FH8065801620004 SR23W F0 2.4G FCBGA
SA00008982L
SA000089A2L
CPU1 5200@
R3
FH8065801620204 SR23Y F0 2.2G FCBGA

SA00008992L Issued Date 2015/01/20 Deciphered Date 2015/12/31 Title
CPU (DDR)
A00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
D D
CPU1S HSW_ULT_DDR3L 19 OF 19
#514405
CFG[19:0]
<96> CFG[19:0]
CFG0 AC60 AV63 RSVDAV63 1 TP601
CFG1 AC62 CFG0 RSVD_TP#AV63 AU63 RSVDAU63 1 TP602
CFG2 AC63 CFG1 RSVD_TP#AU63
CFG3 AA63 CFG2
CFG4 AA60 CFG3 C63 RSVDC63 1 TP603
CFG5 Y62 CFG4 RSVD_TP#C63 C62 RSVDC62 1 TP604
CFG6 Y61 CFG5 RSVD_TP#C62 B43 EDP_SPARE 1 TP605
CFG7 Y60 CFG6 RSVD#B43
CFG8 V62 CFG7 A51 RSVDA51 1 TP606
CFG9 V61 CFG8 RSVD_TP#A51 B51 RSVDB51 1 TP607
CFG10 V60 CFG9 RSVD_TP#B51
CFG11 U60 CFG10 L60 RSVDL60 1 TP608
CFG12 T63 CFG11 RSVD_TP#L60
CFG13 T62 CFG12 RESERVED N60
CFG14 T61 CFG13 RSVD#N60
CFG14 Intel Recommend
CFG15 T60 W23
CFG15 RSVD#W23 Y22 PROC_OPI_COMP3 R606 1 2 49D9R2F-GP
CFG16 AA62 RSVD#Y22 AY15 PROC_OPI_COMP R602 1
DY 2 49D9R2F-GP
CFG18 U63 CFG16 PROC_OPI_RCOMP
CFG18 @
CFG17 AA61 AV62
CFG19 U62 CFG17 RSVD#AV62 D58
C CFG19 RSVD#D58 C
1 2 CFG_RCOMP V63 P22
CFG_RCOMP VSS N21 Layout Note:
A5 VSS
R601
RSVD#A5
1.Referenced "continuous" VSS plane only.
49D9R2F-GP P20 HVM_CLK# 1 2.Avoid routing next to clock pins or noisy
E1 RSVD#P20 R20 HVM_CLK 1 TP619
D1 RSVD#E1 RSVD#R20 TP620 signals.
J20 RSVD#D1 3.Trace width: 12~15mil
H18 RSVD#J20
RSVD#H18 4.Isolation Spacing: 12mil
1 2 TD_IREF B12
TD_IREF 5.Max length: 500mil
R603
8K2R2F-1-GP
@
#514405 PCH strap pin:

CFG3
1
PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

R604
1KR2J-1-GP 0 : ENABLED
DY CFG[3] SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
2
1 : DISABLED
B B
CFG4
1
DISPLAY PORT PRESENCE STRAP

R605
1KR2J-1-GP 0 : ENABLED
CFG[4] AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED TO THE EMBEDDED DISPLAY PORT
2
1 : DISABLED
NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT
A A

CPU (RESERVED)
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
VCC_CORE
HSW_ULT_DDR3L
D CPU1L 12 OF 19 D
L59 C36
1D35V_S3 J58 RSVD#L59 VCC C40
RSVD#J58 VCC C44
1D05S_VCCST AH26 VCC C48
AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
R703 1 2 75R2F-2-GP VR_SVID_ALERT# AJ37 VDDQ VCC E23
AN33 VDDQ VCC E25
R704 1 2 130R2F-1-GP H_CPU_SVIDDAT AP43 VDDQ VCC E27
VCC_CORE AR48 VDDQ VCC E29
Layout Note: AY35 VDDQ VCC E31
AY40 VDDQ VCC E33
1. Place close to CPU VDDQ VCC
#487822 2. VCC_SENSE/ VSS_SENSE AY44 E35
VDDQ VCC
1
AY50 E37
impedance=50 ohm VDDQ VCC E39
3. Length match<25mil R702 F59 VCC E41
VCC_CORE VCC VCC
100R2F-L1-GP-U N58 E43
AC58 RSVD#N58 VCC E45
2
RSVD#AC58 VCC E47
E63 VCC E49
<48> VCC_SENSE VCC_SENSE VCC
AB23 E51
1 TP_VCCIO_OUT A59 RSVD#AB23 VCC E53
E20 VCCIO_OUT VCC E55
+VCCIOA_OUT VCCIOA_OUT VCC
AD23 E57
TP701 AA23 RSVD#AD23 VCC F24
R701 TPAD14-OP-GP AE59 RSVD#AA23 VCC F28
43R2J-GP RSVD#AE59 VCC F32
C 1 2H_CPU_SVIDALRT# L62 VCC F36 C
<48> VR_SVID_ALERT# VIDALERT# VCC
<48> H_CPU_SVIDCLK H_CPU_SVIDCLK N63 HSW ULT POWER F40
3D3V_S5 H_CPU_SVIDDAT L63 VIDSCLK VCC F44
<48> H_CPU_SVIDDAT VIDSOUT VCC
H_VCCST_PW RGD B59 F48
VCCST_PWRGD VCC
SCD1U16V2KX-3GP
<48> H_VR_ENABLE F60 F52

C702 R710 1 @ 2 10KR2J-3-GP C59 VR_EN VCC F56
1D05S_VCCST IMVP_PW RGD_R VR_READY VCC G23
VCC
1
@ D63 G25
PW R_DEBUG H59 VSS VCC G27
<96> PW R_DEBUG PWR_DEBUG# VCC
1D05S_VCCST R705 1 2150R2J-L1-GP-U P62 G29
2
1 RSVDP60 P60 VSS VCC G31

RSVD_TP#P60 VCC
1
TP702 1
TPAD14-OP-GP RSVDP61 P61 G33
U701 R706 TP703 1
TPAD14-OP-GP RSVDN59 N59 RSVD_TP#P61 VCC G35
10KR2J-3-GP TP704 1
TPAD14-OP-GP RSVDN61 N61 RSVD_TP#N59 VCC G37
1 5 @ TP705 TPAD14-OP-GP T59 RSVD_TP#N61 VCC G39
NC#1 VCC AD60 RSVD#T59 VCC G41
2
2 AD59 RSVD#AD60 VCC G43

<36,46> 1D05V_VTT_PW RGD A RSVD#AD59 VCC
AA59 G45
3 4 AE60 RSVD#AA59 VCC G47
GND Y H_VCCST_PW RGD <96> RSVD#AE60 VCC
AC59 G49
EC701 AG58 RSVD#AC59 VCC G51
RSVD#AG58 VCC
1
74LVC1G07GW -GP U59 G53

1D05S_VCCST V59 RSVD#U59 VCC G55
SCD1U16V2KX-3GP
@EMI@ 1D05V_S0 1D05S_VCCST RSVD#V59 VCC G57

@
2
R711 AC22 VCC H23

1 @ 2 0_0603_1% 0.1A AE22 VCCST VCC J23
SC1U10V2KX-1GP
1 2 VCC_CORE AE23 VCCST VCC K23
SC22U6D3V5MX-2GP
VCCST VCC K57
C701
R707 Short Pad VCC
1
AB57 L22
C703
100KR2F-L1-GP
VCC VCC
1
B @ @ AD57 M23 B
R709 AG57 VCC VCC M57
2
47KR2F-GP C24 VCC VCC P57
C28 VCC VCC U57
C32 VCC VCC W57
2
VCC VCC
Need to fine tune to 1.05V.
HASW ELL-6-GP-U
<24,48> IMVP_PW RGD 1 2 IMVP_PW RGD_R

R713
100KR2F-L1-GP
1
1
EC702
R712 @EMI@
SCD1U16V2KX-3GP
47KR2F-GP
2
2
A A

CPU (VCC Core)
A00
LA-B483P
5 4 3 2 1
Main Func 5= CPU 4 3 2 1
D D
CPU1A HSW_ULT_DDR3L 1 OF 19
<54,55> HDMI_CRT_N0 C54 C45

C55 DDI1_TXN0 EDP_TXN0 B46 EDP_TX0_DN <52>
<54,55> HDMI_CRT_P0 DDI1_TXP0 EDP_TXP0 EDP_TX0_DP <52>
<54,55> HDMI_CRT_N1 B58 A47
HDMI<54,55> HDMI_CRT_P1 C58 DDI1_TXN1
DDI1_TXP1
EDP_TXN1
EDP_TXP1
B47 EDP_TX1_DN
EDP_TX1_DP
<52>
<52>
<54> HDMI_DATA0# B55
A55 DDI1_TXN2 C47 +VCCIOA_OUT
<54> HDMI_DATA0 DDI1_TXP2 EDP_TXN2
<54> HDMI_CLK# A57 C46 Design Guideline:
DDI1_TXN3 EDP_TXP2
C <54> HDMI_CLK B57
DDI1_TXP3 EDP_TXN3
A49 EDP_COMP keep routing length max 100 mils. C
1
DDI EDP B49 R801
EDP_TXP3 Trace Width:20 mils.
C51 24D9R2F-L-GP
C50 DDI2_TXN0 A45
DDI2_TXP0 EDP_AUXN EDP_AUX_DN <52>
C53 B45
DDI2_TXN1 EDP_AUXP EDP_AUX_DP <52>
B54
2
C49 DDI2_TXP1 D20 EDP_COMP
B50 DDI2_TXN2 EDP_RCOMP A43 EDP_BRIGHTNESS 1
A53 DDI2_TXP2 EDP_DISP_UTIL
B53 DDI2_TXN3
DDI2_TXP3 TP801
TPAD14-OP-GP
HASW ELL-6-GP-U
B B
A A

CPU (DDI/EDP)
A00
LA-B483P
5 4 3 2 1
Main Func = CPU

CPU1P HSW_ULT_DDR3L 16 OF 19
H17
D33 VSS H57
D D34 VSS VSS J10 D
D35 VSS VSS J22
D37 VSS VSS J59
D38 VSS VSS J63
D39 VSS VSS K1
D41 VSS VSS K12
D42 VSS VSS L13
D43 VSS VSS L15
D45 VSS VSS L17
D46 VSS VSS L18
D47 VSS VSS L20
D49 VSS VSS L58
D5 VSS VSS L61
D50 VSS VSS L7
D51 VSS VSS M22
D53 VSS VSS N10
D54 VSS VSS N3
D55 VSS VSS P59
D57 VSS VSS P63
D59 VSS VSS R10
C D62 VSS VSS R22 C
D8 VSS VSS R8
E11 VSS VSS T1
E17 VSS VSS T58
F20 VSS VSS U20
F26 VSS VSS U22
F30 VSS VSS U61
F34 VSS VSS U9
F38 VSS VSS V10
F42 VSS VSS V3
F46 VSS VSS V7
F50 VSS VSS W20
F54 VSS VSS W22
F58 VSS VSS Y10
F61 VSS VSS Y59
G18 VSS VSS Y63
G22 VSS VSS
G3 VSS
G5 VSS V58
G6 VSS VSS AH46
G8 VSS VSS V23
B B
H13 VSS VSS E62 VSS_SENSE
VSS VSS_SENSE VSS_SENSE <48>
AH16
VSS
100R2F-L1-GP-U
1
HASWELL-6-GP-U
Layout Note:
R901
@ 1. Place close to CPU
2. VCC_SENSE/ VSS_SENSE
2
impedance=50 ohm
3. Length match<25mil
A A
CPU (VSS)
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
D D
1D35V_S3
SC2D2U6D3V2MX-GP SC10U6D3V3MX-GP
SC2D2U6D3V2MX-GP SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
Layout Note:
1
1
C1001
C1002
C1003
C1004
C1005
C1006
DY DY DY As close to CPU as possible
2
2
C1017
C1018
C1019
C1020
1
1
C DY DY C
2
Layout Note:
Direct tie to CPU VccIn/Vss balls
B B
A A
CPU (Power CAP1)
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
MAX: 1.92A
1.838A 41mA 42mA
D D
1D05V_HSIO +V1.05DX_MODPHY_PCH 1D05V_HSIO +V1.05S_ASATA3PLL
1D05V_HSIO +V1.05S_AUSB3PLL
Short Pad
1 2 L1102 1 @ 2 0_0603_1% +V1.05S_ASATA3PLL
R1101 @ 0_0805_1% L1101 1 @ 2 0_0603_1% +V1.05S_AUSB3PLL
1
C1102
C1101
Short Pad
SC1U10V2KX-1GP
SC1U10V2KX-1GP
1
C1105
C1106
C1107
Short Pad
SC1U10V2KX-1GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
1
1
C1103
C1104
C1123
DY DY
SC1U10V2KX-1GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
2
2
DY DY
2
2
2
CAP need close to pin K9 L10 CAP need close to pin B18 CAP need close to pin B11
57mA 62mA 185mA
1D05V_S0 +V1.05S_APLLOPI 1D05V_S0 +V1.05S_AXCK_DCB

3D3V_S5_PCH +V3.3A_PSUS
L1103 1 2 IND-2D2UH-196-GP +V1.05S_AXCK_DCB
C R1102 1 @ 2 0_0603_1% +V1.05S_APLLOPI R1103 1 @ 2 0_0603_1% C
1
C1111
C1108
C1112
C1125
Short Pad Short Pad
SC1U10V2KX-1GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
1
1
C1109
C1110
C1124
DY DY DY
SC1U10V2KX-1GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
DY DY
2
2
2
CAP need close to pin AA21 CAP need close to pin AC9 CAP need close to pin J18
31mA 658mA 1.632A 1mA
1D05V_S0 +1.05M_ASW 1D05V_S0 +V1.05S_CORE_PCH

1D05V_S0 IND-2D2UH-196-GP +V1.05S_AXCK_LCPLL RTC_AUX_S5
L1104 R1104 1 @ 2 0_0603_1% 1
Short Pad
2
1 2 R1105 @ 0_0805_1% C1120 C1121
C1118
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
Short Pad
1
1
C1116
C1117
C1122
C1115
C1119
DY
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
1
1
C1113
C1114
DY DY
SC1U10V2KX-1GP
SC10U10V5KX-2GP
DY
2
2
B B
2
CAP need close to pin A20 CAP need close to pin AE9 CAP need close to pin AE8 J11 CAP need close to pin AG10
A A

CPU (Power CAP2)
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = DIMM1

SA0_DIMA
SA1_DIMA Note:
SA0 DIM0 = 0, SA1_DIM0 = 0
X01_0808
1
@ @
R1202 R1201
SO-DIMMA SPD Address is 0xA0
DM1 SO-DIMMA TS Address is 0x30
Short Pad
Short Pad
0_0402_1%
0_0402_1%
<5> M_A_A[15:0]
M_A_A0 98 NP1
A0 NP1
2
M_A_A1 97 NP2
M_A_A2 96 A1 NP2
M_A_A3 95 A2 110
A3 RAS# M_A_RAS# <5>
M_A_A4 92 113 M_A_WE# <5>
M_A_A5 91 A4 WE# 115
A5 CAS# M_A_CAS# <5>
M_A_A6 90
M_A_A7 86 A6 114
A7 CS0# M_A_DIMA_CS#0 <5>
M_A_A8 89 121 M_A_DIMA_CS#1 <5>
M_A_A9 85 A8 CS1#
M_A_A10 107 A9 73
A10/AP CKE0 M_A_DIMA_CKE0 <5>
M_A_A11 84 74 M_A_DIMA_CKE1 <5>
M_A_A12 83 A11 CKE1
M_A_A13 119 A12 101
A13 CK0 M_A_DIMA_CLK_DDR0 <5> 1D35V_S3
M_A_A14 80 103 M_A_DIMA_CLK_DDR#0 <5>
M_A_A15 78 A14 CK0#
D 79 A15 102 D
<5> M_A_BS2 A16/BA2 CK1 M_A_DIMA_CLK_DDR1 <5>
104
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U6D3V3MX-GP
CK1# M_A_DIMA_CLK_DDR#1 <5>
109
<5> M_A_BS0 108 BA0 11
C1220
C1221
C1222
ST330U2VDM-4-GP
TC1201
<5> M_A_BS1 BA1 DM0 28
<5> M_A_DQ[63:0] DM1
1
M_A_DQ13 5 46
M_A_DQ8 7 DQ0 DM2 63
C1207
C1208
C1209
M_A_DQ14 15 DQ1 DM3 136 DY DY DY
2
M_A_DQ10 17 DQ2 DM4 153
Layout Note:
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
M_VREF_CA_DIMMA M_A_DQ9 4 DQ3 DM5 170
M_A_DQ12 6 DQ4 DM6 187
Place these caps DQ5 DM7
M_A_DQ15 16
close to VREF_CA M_A_DQ11 18 DQ6 200
DQ7 SDA PCH_SMBDATA <13,18,55,62,96>
M_A_DQ29 21 202
23 DQ8 SCL PCH_SMBCLK <13,18,55,62,96>
M_A_DQ28
M_A_DQ30 33 DQ9 198 3D3V_S0
DQ10 EVENT#
1
M_A_DQ31 35
C1211
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C1201 C1218 C1202 M_A_DQ25 22 DQ11 199
C1212
C1213
DQ12 VDDSPD
1
M_A_DQ24 24
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
2
M_A_DQ27 34 DQ13 197 SA0_DIMA C1210

DQ14 SA0 DY
1
M_A_DQ26 36 201 SA1_DIMA
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
2
2
M_A_DQ44 39 DQ15 SA1 C1203
M_A_DQ41 41 DQ16 77
DY
SCD1U16V2KX-3GP
2
M_A_DQ43 51 DQ17 NC#1 122
M_A_DQ47 53 DQ18 NC#2 125 1D35V_S3
M_A_DQ45 40 DQ19 NC#/TEST
M_A_DQ40 42 DQ20 75
M_A_DQ42 50 DQ21 VDD1 76
M_A_DQ46 52 DQ22 VDD2 81
Layout Note: M_A_DQ51 57 DQ23 VDD3 82
Place these caps M_A_DQ50 59 DQ24 VDD4 87 Layout Note:
M_A_DQ49 67 DQ25 VDD5 88
close to VREF_DQ DQ26 VDD6 Place these Caps near DIMM1.
M_A_DQ48 69 93
M_VREF_DQ_DIMMA M_A_DQ52 56 DQ27 VDD7 94
M_A_DQ53 58 DQ28 VDD8 99
M_A_DQ54 68 DQ29 VDD9 100
M_A_DQ55 70 DQ30 VDD10 105
M_A_DQ0 129 DQ31 VDD11 106
M_A_DQ1 131 DQ32 VDD12 111
M_A_DQ2 141 DQ33 VDD13 112
DQ34 VDD14
1
M_A_DQ6 143 117

C1204 C1206 M_A_DQ5 130 DQ35 VDD15 118
C1205
DY
SC2D2U10V3KX-1GP
M_A_DQ4 132 DQ36 VDD16 123

SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
2
M_A_DQ3 140 DQ37 VDD17 124

M_A_DQ7 142 DQ38 VDD18
M_A_DQ21 147 DQ39 2
M_A_DQ20 149 DQ40 VSS 3
M_A_DQ17 157 DQ41 VSS 8
M_A_DQ16 159 DQ42 VSS 9
M_A_DQ18 146 DQ43 VSS 13
0D675V_S0 M_A_DQ19 148 DQ44 VSS 14
M_A_DQ22 158 DQ45 VSS 19
M_A_DQ23 160 DQ46 VSS 20
M_A_DQ36 163 DQ47 VSS 25
M_A_DQ33 165 DQ48 VSS 26
M_A_DQ34 175 DQ49 VSS 31
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
M_A_DQ38 177 DQ50 VSS 32 1D35V_S3

C1214
C1215
C1216
DQ51 VSS
1
M_A_DQ37 164 37
C
DY
Layout Note: M_A_DQ32 166 DQ52 VSS 38 C
M_A_DQ35 174 DQ53 VSS 43
Place these caps
2
M_A_DQ39 176 DQ54 VSS 44 Q1202

close to VTT1 and M_A_DQ62 181 DQ55 VSS 48 2N7002K_SOT23-3
DQ56 VSS
1
VTT2. M_A_DQ58 183 49 5V_S5
M_A_DQ60 191 DQ57 VSS 54 D
M_A_DQ61 193 DQ58 VSS 55 2
M_A_DQ63 180 DQ59 VSS 60 1D35V_S3 G
M_A_DQ59 182 DQ60 VSS 61 S
DQ61 VSS
1
M_A_DQ56 192 65
3
M_A_DQ57 194 DQ62 VSS 66 R1208
DQ63 VSS 71 220KR2J-L2-GP M_A_B_DIMM_ODT R1206 1 2 66D5R2F-GP M_A_DIMA_ODT0
<5> M_A_DQS#[7:0] VSS
M_A_DQS#1 10 72
M_A_DQS#3 27 DQS0# VSS 127 R1207 1 2 66D5R2F-GP M_A_DIMA_ODT1
2
M_A_DQS#5 45 DQS1# VSS 128
DQS2# VSS
2
G
M_A_DQS#6 62 133
DQS3# VSS R1205
M_A_DQS#0 135 134 Short Pad Vth = 1V max. R1209 1 2 66D5R2F-GP M_B_DIMB_ODT0 <13>
M_A_DQS#2 152 DQS4# VSS 138 1 2 DDR_PG_CTRL_R 3 1 DDR_VTT_PG_CTRL
M_A_DQS#4 169 DQS5# VSS 139 <4> DDR_PG_CTRL @ R1210 1 2 66D5R2F-GP
D
DQS6# VSS M_B_DIMB_ODT1 <13>
1
M_A_DQS#7 186 144 @
DQS7# VSS 145 0_0402_1% R1204
<5> M_A_DQS[7:0] VSS Q1201
M_A_DQS1 12 150 2M_0402_1%
M_A_DQS3 29 DQS0 VSS 151
Q1201 must use Vth=1V. MESS138W-G_SOT323-3 DY DDR_VTT_PG_CTRL <47>
2
DQS7 VSS 172
M_A_DIMA_ODT0 116 VSS 173
M_A_DIMA_ODT1 120 ODT0 VSS 178
ODT1 VSS 179
126 VSS 184
M_VREF_CA_DIMMA VREF_CA VSS
1 185
Layout Note: M_VREF_DQ_DIMMA VREF_DQ VSS 189
30 VSS 190
All VREF traces should<13,4> DDR3_DRAMRST# RESET# VSS 195
have width=20mil; VSS 196
spacing=20 mil 203 VSS 205
0D675V_S0 VTT1 VSS
1
204 206
C1217 VTT2 VSS
SCD1U16V2KX-3GP
2
DY DDR3-204P-108-GP-U
CONN@
close to dimm
B B
A A

DDR3L_SODIMM1
A00
5 4 3 2 1
5 4 3 2 1
Main Func = DIMM2

X01_0808
DM2
<5> M_B_A[15:0]
M_B_A0 98 NP1
M_B_A1 97 A0 NP1 NP2
M_B_A2 96 A1 NP2 3D3V_S0
M_B_A3 95 A2 110
A3 RAS# M_B_RAS# <5>
M_B_A4 92 113
A4 WE# M_B_WE# <5>
M_B_A5 91 115
M_B_CAS# <5>
1
M_B_A6 90 A5 CAS#
M_B_A7 86 A6 114 R1302
A7 CS0# M_B_DIMB_CS#0 <5>
M_B_A8 89 121 10KR2J-3-GP
A8 CS1# M_B_DIMB_CS#1 <5>
M_B_A9 85
M_B_A10 107 A9 73
M_B_DIMB_CKE0 <5>
2
M_B_A11 84 A10/AP CKE0 74
D M_B_DIMB_CKE1 <5> D
M_B_A12 83 A11 CKE1
M_B_A13 119 A12 101
A13 CK0 M_B_DIMB_CLK_DDR0 <5>
M_B_A14 80 103 SA1_DIMB
A14 CK0# M_B_DIMB_CLK_DDR#0 <5>
M_B_A15 78
79 A15 102 SA0_DIMB
<5> M_B_BS2 A16/BA2 CK1 M_B_DIMB_CLK_DDR1 <5>
104
CK1# M_B_DIMB_CLK_DDR#1 <5>
109
1
<5> M_B_BS0 108 BA0 11
<5> M_B_BS1 BA1 DM0 @
28
<5> M_B_DQ[63:0]
M_B_DQ8 5 DM1 46 0_0402_1% Note:
M_B_DQ14 7 DQ0 DM2 63 R1301 SO-DIMMB SPD Address is 0xA4
M_VREF_CA_DIMMB Layout Note: M_B_DQ10 15 DQ1 DM3 136
Short Pad SO-DIMMB TS Address is 0x34
2
M_B_DQ11 17 DQ2 DM4 153
Place these caps DQ3 DM5
M_B_DQ12 4 170
close to VREF_CA M_B_DQ9 6 DQ4 DM6 187
M_B_DQ13 16 DQ5 DM7
M_B_DQ15 18 DQ6 200
21 DQ7 SDA 202 PCH_SMBDATA <12,18,55,62,96>
M_B_DQ28
PCH_SMBCLK <12,18,55,62,96>
1
M_B_DQ29 23 DQ8 SCL

C1308 C1306 C1309 M_B_DQ26 33 DQ9 198 3D3V_S0
M_B_DQ27 35 DQ10 EVENT#
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
2
M_B_DQ25 22 DQ11 199

M_B_DQ24 24 DQ12 VDDSPD
1
M_B_DQ30 34 DQ13 197 SA0_DIMB
M_B_DQ31 36 DQ14 SA0 201 SA1_DIMB C1311
M_B_DQ40 39 DQ15 SA1 DY SCD1U16V2KX-3GP
2
M_B_DQ41 41 DQ16 77
M_B_DQ46 51 DQ17 NC#1 122
M_B_DQ42 53 DQ18 NC#2 125 1D35V_S3
M_B_DQ45 40 DQ19 NC#/TEST
M_B_DQ44 42 DQ20 75
M_B_DQ47 50 DQ21 VDD1 76
M_B_DQ43 52 DQ22 VDD2 81
M_B_DQ56 57 DQ23 VDD3 82
M_B_DQ57 59 DQ24 VDD4 87
M_VREF_DQ_DIMMB Layout Note: M_B_DQ59 67 DQ25 VDD5 88
M_B_DQ58 69 DQ26 VDD6 93
Place these caps DQ27 VDD7
M_B_DQ61 56 94
close to VREF_DQ M_B_DQ60 58 DQ28 VDD8 99
M_B_DQ63 68 DQ29 VDD9 100
M_B_DQ62 70 DQ30 VDD10 105
C C
M_B_DQ4 129 DQ31 VDD11 106
DQ32 VDD12
1
M_B_DQ1 131 111

M_B_DQ3 141 DQ33 VDD13 112
C1305
C1302 C1310
DY
SC2D2U10V3KX-1GP
M_B_DQ7 143 DQ34 VDD14 117

SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
2
M_B_DQ5 130 DQ35 VDD15 118

M_B_DQ0 132 DQ36 VDD16 123
M_B_DQ2 140 DQ37 VDD17 124
M_B_DQ6 142 DQ38 VDD18
M_B_DQ32 147 DQ39 2
M_B_DQ37 149 DQ40 VSS 3 1D35V_S3
M_B_DQ38 157 DQ41 VSS 8
M_B_DQ34 159 DQ42 VSS 9
M_B_DQ33 146 DQ43 VSS 13
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U6D3V3MX-GP
M_B_DQ36 148 DQ44 VSS 14
0D675V_S0 M_B_DQ39 158 DQ45 VSS 19
C1314
C1320
C1316
M_B_DQ35 160 DQ46 VSS 20
DQ47 VSS
1
M_B_DQ17 163 25
M_B_DQ16 165 DQ48 VSS 26
C1321
C1318
C1315
M_B_DQ18 175 DQ49 VSS 31
DY DY
2
M_B_DQ19 177 DQ50 VSS 32
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
M_B_DQ20 164 DQ51 VSS 37
C1307
C1303
C1304
DQ52 VSS
1
M_B_DQ21 166 38
DY
Layout Note: M_B_DQ23 174 DQ53 VSS 43
M_B_DQ22 176 DQ54 VSS 44
Place these caps
2
M_B_DQ52 181 DQ55 VSS 48

close to VTT1 and M_B_DQ49 183 DQ56 VSS 49
VTT2. M_B_DQ48 191 DQ57 VSS 54
M_B_DQ53 193 DQ58 VSS 55
C1317
SC1U10V2KX-1GP
SC1U10V2KX-1GP
M_B_DQ51 180 DQ59 VSS 60
C1312
C1313
DQ60 VSS
1
M_B_DQ55 182 61
M_B_DQ54 192 DQ61 VSS 65 C1319
M_B_DQ50 194 DQ62 VSS 66
DY
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
2
2
DQ63 VSS 71
<5> M_B_DQS#[7:0] VSS
M_B_DQS#1 10 72
M_B_DQS#3 27 DQS0# VSS 127
B M_B_DQS#6 186 DQS6# VSS 144 B
<5> M_B_DQS[7:0]
DQS7# VSS 145 Layout Note:
M_B_DQS1 12 VSS 150
DQS0 VSS
Place these Caps near SO-DIMMB.
M_B_DQS3 29 151
M_B_DQS5 47 DQS1 VSS 155
DQS7 VSS 172
116 VSS 173
<12> M_B_DIMB_ODT0 120 ODT0 VSS 178
<12> M_B_DIMB_ODT1 ODT1 VSS 179
126 VSS 184
M_VREF_CA_DIMMB VREF_CA VSS
1 185
M_VREF_DQ_DIMMB VREF_DQ VSS 189
Layout Note: 30 VSS 190
<12,4> DDR3_DRAMRST# RESET# VSS 195
All VREF traces should VSS 196
have width=20mil; 203 VSS 205
0D675V_S0 VTT1 VSS
1
spacing=20 mil 204 206

C1301 VTT2 VSS
DY SCD1U16V2KX-3GP
2
DDR3-204P-259-GP
CONN@
close to dimm
A A

DDR3L_SODIMM2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
5 4 3 2 1
5 4 3 2 1
D D
C
(Blanking) C
B B
A A
(Reserved)_SODIMM _SODIMM4
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = PCH

PCH strap pin:
Port B Detected
Low = Disable Port B (default)

DDPB_CTRLDATA High = Enable Port B
*
* Low = Disable Port C (default)
D DDPC_CTRLDATA High = Enable Port C D
The internal pull-down is disabled after PLTRST# deasserts
3D3V_S0
1
1
HSW_ULT_DDR3L
CPU1I 9 OF 19 RE1 RE2
2.2K_0402_5% 2.2K_0402_5%
HDMI
2
2
<52> L_BKLT_CTRL B8 B9
EDP_BKLCTL DDPB_CTRLCLK PCH_HDMI_CLK <54>
<24> L_BKLT_EN A9 C9
EDP_BKLEN DDPB_CTRLDATA PCH_HDMI_DATA <54>
<52> EDP_VDD_EN C6 eDP SIDEBAND D9
10K_0402_5% EDP_VDDEN DDPC_CTRLCLK D11
1 2 DDPC_CTRLDATA
RE3 DGPU_HOLD_RST# EE Note:
RE4 1 2 @ DGPU_PW R_EN If layout is on constraint, please reserve TP for DDPC_CTRLCLK.
<20> PIRQA# U6
10K_0402_5% PIRQB# P4 PIRQA#/GPIO77 C5
<18> PIRQB# PIRQB#/GPIO78 DDPB_AUXN PCH_DPB_AUXN <55>
<20> PIRQC# PIRQC# N4 B6 CRT
R1509 1 2 DGPU_PW ROK PIRQD# N2 PIRQC#/GPIO79 DISPLAY DDPC_AUXN B5
C 100KR2J-1-GP TP1501 1 PCI_PME# AD4 PIRQD#/GPIO80 DDPB_AUXP A6 PCH_DPB_AUXP <55> C
TPAD14-OP-GP PME# PCIE DDPC_AUXP
UMA@
<19,20> MCP_GPIO55 MCP_GPIO55 U7
L1 GPIO55
<82,83> DGPU_PW R_EN GPIO52
<73> DGPU_HOLD_RST# L3 C8
R5 GPIO54 DDPB_HPD A8 HDMI_CRT_DET <54,55>
3D3V_S0 <24,82,83> DGPU_PW ROK GPIO51 DDPC_HPD
CPU_ID L4 D6 EDP_HPD <52>
GPIO53 EDP_HPD
1
1 R1516 2 DGPU_HOLD_RST#
@ 10K_0402_5% EC1501 EC1502
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
2
2
1 R1517 2 DGPU_PW R_EN @EMI@ @EMI@
10K_0402_5% HASW ELL-6-GP-U
3D3V_S0 @
RN1505 GPIO38 GPIO37

1 8 KB_DET# KB_DET# <20,62>
BIOS strap pin:
2 7 DBC_EN DBC_EN <20,52>
3 6 CLK_PCIE_LAN_REQ4# <18,30> BIOS VRAM Size Strap pin PROJECT_ID2 PROJECT_ID1
4 5 PIRQD#
Iris2 0 0
SRN10KJ-6-GP
3D3V_S0 3D3V_S0 3D3V_S0 Van Gogh 0 1
B B
Tulip 1 0
1
1
TL@ VG@ BDW @
R1513 R1510 R1512
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
Tulip Van Gogh BDW
2
2
PROJECT_ID2 PROJECT_ID2 <20> PROJECT_ID1 PROJECT_ID1 <19> CPU_ID
1
1
VG@ TL@ HSW @
R1514 R1511 R1515 CPU detect pin
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
Iris2 / Van Gogh Iris2 / Tulip HSW
2
2
A A

CPU (PCI/CRT/DDI)
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = PCH

CPU1K HSW_ULT_DDR3L 11 OF 19 USB 2.0 Table
Pair Device
F10 AN8
<73> CPU_RXN_C_dGPU_TXN0 PERN5_L0 USB2N0 USB_PN0 <34>
E10 AM8
<73> CPU_RXP_C_dGPU_TXP0 PERP5_L0 USB2P0 USB_PP0 <34>
SCD1U16V2KX-3GP 0 USB3.0 port1
<73> dGPU_RXN_C_CPU_TXN0 C1606 1 2 DIS@ dGPU_RXN_CPU_TXN0 C23 AR7
USB_PN1 <34>
C1605 1 2 DIS@ dGPU_RXP_CPU_TXP0 C22 PETN5_L0 USB2N1 AT7
<73> dGPU_RXP_C_CPU_TXP0 PETP5_L0 USB2P1 USB_PP1 <34>
SCD1U16V2KX-3GP 1 USB2.0 Port2 (Debug Port/IOBD)
F8 AR8
D <73> CPU_RXN_C_dGPU_TXN1 PERN5_L1 USB2N2 USB_PN2 <34> D
E8 AP8
SCD1U16V2KX-3GP 2 USB2.0 Port3 (IOBD)
<73> dGPU_RXN_C_CPU_TXN1 C1608 1 2 DIS@ dGPU_RXN_CPU_TXN1 B23 AR10 USB_PN3 1
PETN5_L1 USB2N3 TP1601 TPAD14-OP-GP
<73> dGPU_RXP_C_CPU_TXP1 C1607 1 2 DIS@ dGPU_RXP_CPU_TXP1 A23 AT10 USB_PP3 1
PETP5_L1 USB2P3 TP1602 TPAD14-OP-GP
SCD1U16V2KX-3GP 3 X
H10 GPU AM15
G10 AL15
SCD1U16V2KX-3GP 4 CAMERA
<73> dGPU_RXN_C_CPU_TXN2 C1610 1 2 DIS@ dGPU_RXN_CPU_TXN2 B21 AM13
USB_PN5 <58>
C1609 1 2 DIS@ dGPU_RXP_CPU_TXP2 C21 PETN5_L2 USB2N5 AN13
SCD1U16V2KX-3GP 5 WLAN
E6 AP11
F6 AN11
SCD1U16V2KX-3GP 6 Touch Panel
<73> dGPU_RXN_C_CPU_TXN3 C1612 1 2 DIS@ dGPU_RXN_CPU_TXN3 B22 AR13
USB_PN7 <32>
C1611 1 2 DIS@ dGPU_RXP_CPU_TXP3 A21 PETN5_L3 USB2N7 AP13
SCD1U16V2KX-3GP 7 Card Reader
G11
<58> PCIE_PRX_W LANTX_N3 PERN3
F11 G20
<58> PCIE_PRX_W LANTX_P3 PERP3 USB3RN1 USB3_PRX_CTX_N0 <34>
SCD1U16V2KX-3GP H20
C1601 1 2 PCIE_PTX_W LANRX_N3 C29 USB3RP1 USB3_PRX_CTX_P0 <34>
<58> PCIE_PTX_W LANRX_N3_C PETN3 WLAN
<58> PCIE_PTX_W LANRX_P3_C C1602 1 2 PCIE_PTX_W LANRX_P3 B30 PCIE USB C33
USB3_PTX_CRX_N0 <34>
SCD1U16V2KX-3GP PETP3 USB3TN1 B34
USB3TP1 USB3_PTX_CRX_P0 <34>
F13
<30> PCIE_PRX_LANTX_N4 PERN4
G13 E18
<30> PCIE_PRX_LANTX_P4 PERP4 USB3RN2
SCD1U16V2KX-3GP LAN F18
C1603 1 2 PCIE_PTX_LANRX_N4 B29 USB3RP2
<30> PCIE_PTX_LANRX_N4_C PETN4
<30> PCIE_PTX_LANRX_P4_C C1604 1 2 PCIE_PTX_LANRX_P4 A29 B33
SCD1U16V2KX-3GP PETP4 USB3TN2 A33
G17 USB3TP2
F17 PERN1/USB3RN3
C PERP1/USB3RP3 C
C30 Layout Note:

C31 PETN1/USB3TN3 AJ10 USB_COMP 1 2 1. USB_COMP using 50 ohm single-ended impedance
PETP1/USB3TP3 USBRBIAS# AJ11 R1602
USBRBIAS 2. Isolation Spacing :15mil
F15 AN10 22D6R2F-L1-GP 3. Total trace length<500mil
G15 PERN2/USB3RN4 RSVD#AN10 AM10
PERP2/USB3RP4 RSVD#AM10
B31
A31 PETN2/USB3TN4
PETP2/USB3TP4 AL3 USB_OC#0_1
OC0/GPIO40# USB_OC#0_1 <18,35>
AT1 USB_OC#2_3
OC1/GPIO41# USB_OC#2_3 <35>
AH2 USB_OC#4_5
+V1.05S_AUSB3PLL OC2/GPIO42# USB_OC#4_5 <20>
R1601 E15 AV3 USB_OC#6_7
3KR2F-GP E13 RSVD#E15 OC3/GPIO43#
1 2 PCIE_RCOMP A27 RSVD#E13
B27 PCIE_RCOMP
PCIE_IREF
3D3V_S5_PCH
RN1601
USB_OC#2_3 8 1
HASW ELL-6-GP-U USB_OC#6_7 7 2
6 3
Layout Note: @
<18> MCP_GPIO73 5 4
1. PCIE_RCOMP/ PCIE_IREF trace width=12~15mil <17> PM_SUSW ARN#_R
2. Isolation Spacing: 12mil
3. Total trace length<500mil SRN10KJ-6-GP
#515621
B B
PCIE Table
Port Device Share BUS
1 N/A USB3.0_3
2 N/A USB3.0_4
3 WLAN
4 LAN
GPU GPU GPU GPU
5(L0~L3) GPU
6(L3) HDD SATA0
6(L2) ODD SATA1
6(L0~L1) N/A
GPU GPU GPU GPU
A A

PCH (PCIE/USB)
A00
5 4 3 2 1
5 4 3 2 1
Main Func = PCH
RE5 2 1 10K_0402_5% PM_RSMRST#

D
RE6 2 1 10K_0402_5% PM_PCH_PW ROK PCH strap pin: D
@ On Die DSW VR Enable R1720 RTC_AUX_S5

R1717 2 1 10KR2J-3-GP SYS_PW ROK 330KR2J-L1-GP
DSW ODVREN 1 2
Low = Disable
DSWVRMEN 1 2
High = Enable (default) DY
* R1721
This signal has no integrated pull-up/pull-down. 330KR2J-L1-GP
3D3V_S0
1
R1701
10KR2J-3-GP
CPU1H HSW_ULT_DDR3L 8 OF 19
2
SYSTEM POWER MANAGEMENT R1705: DY for OBFF disable

PM_SUSACK#_R AK2 AW7 DSW ODVREN R1704 0R2J-2-GP
XDP_DBRESET# AC3 SUSACK# DSWVRMEN AV5 PCH_DPW ROK 1 NODS3@2 PM_RSMRST#
<96> XDP_DBRESET# SYS_RESET# DPWROK
<24,96> SYS_PW ROK SYS_PW ROK AG2 AJ5 PCH_W AKE# R1705 1 2 0R2J-2-GP PCIE_W AKE# <24,30>
SYS_PWROK WAKE#
<24,26,36> PCH_PW ROK R1706 1 @ 2 0_0402_1% PM_PCH_PW ROK AY7
PCH_PWROK
Short Pad R1707 1 @ 2 0_0402_1% MPW ROK AB5 @
AG7 APWROK V5
Short Pad PCI_PLTRST# PM_CLKRUN# R1709 1 2 0_0402_1% PM_CLKRUN#_EC <24>
C PLTRST# CLKRUN#/GPIO32 AG4 PM_SUS_STAT#1 C
SUS_STAT#/GPIO61 AE6 SUS_CLK_PCH
Short
TP1702 Pad
1 R1710 2 0R2J-2-GP
SUSCLK/GPIO62 SUS_CLK <24>
AP5 PM_SLP_S5# 1 EMI@
PM_RSMRST# AW6 SLP_S5#/GPIO63 TP1703
PM_SUSW ARN#_R AV4 RSMRST#
<16> PM_SUSW ARN#_R PM_PW RBTN# AL7 SUSWARN#/SUSPWRDNACK#/GPIO30 AJ6 PM_SLP_S4#
<24,96> PM_PW RBTN# PWRBTN# SLP_S4# PM_SLP_S4# <24,47>
<24,76> AC_PRESENT AC_PRESENT AJ8 AT4 PM_SLP_S3# PM_SLP_S3# <24,36,45,46,47>
BATLOW # AN4 ACPRESENT/GPIO31 SLP_S3# AL5 PM_SLP_A# 1
<20> BATLOW # 1 PCH_SLP_S0# AF3 BATLOW#/GPIO72 SLP_A# AP4 PM_SLP_SUS# TP1704
SLP_S0# SLP_SUS# PM_SLP_SUS# <24,38>
TP1706 1 PCH_SLP_W LAN# AM5 AJ7 PM_SLP_LAN# 1
AC_PRESENT TP1705 SLP_WLAN#/GPIO29 SLP_LAN# TP1707
EC1707
1
@EMI@ @
R1713 1 2 PCI_PLTRST#
SCD1U16V2KX-3GP
<24,30,36,52,58,65,73,96> PLT_RST#
Short Pad 0_0402_1% HASW ELL-6-GP-U
2
R1715 C1701 @
100KR2J-1-GP SC220P50V2KX-3GP
@ @
2
R1708
2
PM_SUSW ARN#_R 1 2 PM_SUSACK#_R

3D3V_S5 0R2J-2-GP NODS3@ PCH_DPW ROK R1718 1 2 0R2J-2-GP KBC_DPW ROK <24>
DS3@
2
RE8 1 210K_0402_5% MCP_GPIO12 MCP_GPIO12 <20>
RE7 1 210K_0402_5% AC_PRESENT DS3@ R1725
<24> PM_SUSACK# RE9 1 0_0402_5%
2 PM_SUSACK#_R 100KR2F-L1-GP
<24> PM_SUSW ARN# RE10 1 0_0402_5%
2 PM_SUSW ARN#_R DS3@
B DS3@ B
1
R1703
1 2 PCH_W AKE#
1KR2J-1-GP
(CRB#514469) 3D3V_AUX_S5 R1727
3D3V_S5_PCH 100KR2J-1-GP 3D3V_S0
1 2 R1714
NODS3@ 8K2R2F-1-GP
2
1 2 PM_SUS_STAT# PM_CLKRUN# 1 2
R1724 10KR2J-3-GP R1726
@ 10KR2J-3-GP
SUS_CLK_PCH
1KR2J-1-GP
Q1701
1
R1702
2
XDP_DBRESET# 4 3 PM_RSMRST# 1 2 RSMRST#_KBC <24>
SYS_PW ROK R1728 EC1701
PLT_RST# 3V_5V_POK# 5 2 3V_5V_POK_C 1 2 3V_5V_POK <44> SC4D7P50V2BN-GP
1
PCH_PW ROK NODS3@ @EMI@
KBC_DPW ROK 6 1 0R2J-2-GP
2N7002KDW -GP R1729 1 2 PM_SLP_SUS#

0R2J-2-GP DS3@
1
@EMI@ @EMI@ @EMI@ @EMI@ @EMI@

EC1706 EC1702 EC1703 EC1704 EC1705
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
2
2nd = 84.2N702.E3F
A A
3rd = 75.00601.07C
4th = 84.DMN66.03F

PCH (PM)
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = PCH
C1801
D 0_0402_1% R1810 D
XTAL24_IN 1 @ 2 XTAL24_IN_R 2 1
Short Pad
3D3V_S0 SC15P50V2JN-2-GP
1
RN1801
1 8 MCP_GPIO76 MCP_GPIO76 <20> X1801
1
2 7 PIRQB# PIRQB# <15> XTAL-24MHZ-81-GP
3 6 CLK_PCIE_REQ# R1802
4 5 1MR2J-1-GP
HSW_ULT_DDR3L
CPU1F 6 OF 19
4
SRN10KJ-6-GP
C1802
2
XTAL24_OUT 2 1
C43 A25 XTAL24_IN

C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT SC15P50V2JN-2-GP
CLK_PCIE_REQ# U2 CLKOUT_PCIE_P0 XTAL24_OUT +V1.05S_AXCK_LCPLL
PCIECLKRQ0#/GPIO18 K21
B41 RSVD#K21 M21
A41 CLKOUT_PCIE_N1 RSVD#M21 C26 XCLK_BIASREF R1803 1 2 3KR2F-GP
CLK_PCIE_REQ# Y5 CLKOUT_PCIE_P1 DIFFCLK_BIASREF
PCIECLKRQ1#/GPIO19 C35 MCP_TESTLOW1 RE12 1 2 10K_0402_5%
C41 CLOCK TESTLOW_C35 C34 MCP_TESTLOW2 RE11 1 2 10K_0402_5%
<58> CLK_PCIE_WLAN_N3 CLKOUT_PCIE_N2 TESTLOW_C34
B42 AK8 MCP_TESTLOW3 10K_0402_5%1
10K_0402_5% 2 RE13
<58> CLK_PCIE_WLAN_P3
<20,58> CLK_PCIE_WLAN_REQ3# CLK_PCIE_WLAN_REQ3# AD1 CLKOUT_PCIE_P2
PCIECLKRQ2#/GPIO20
WLAN SIGNALS TESTLOW_AK8
TESTLOW_AL8
AL8 MCP_TESTLOW4 10K_0402_5%
10K_0402_5%1 2 RE14
CLK_PCI_LPC_R R1813 1 2 0R2J-2-GP CLK_DP2VGA <55>
<30> CLK_PCIE_LAN_N4 B38 AN15 CLK_PCI_LPC_R R1804 1 DB@ 2 33R2J-2-GP CLK_PCI_LPC <65>
C37 CLKOUT_PCIE_N3 CLKOUT_LPC_0 AP15 CLK_PCI_KBC_R R1805 1 2 33R2J-2-GP
<30> CLK_PCIE_LAN_P4
<15,30> CLK_PCIE_LAN_REQ4# CLK_PCIE_LAN_REQ4# N1 CLKOUT_PCIE_P3
PCIECLKRQ3#/GPIO21
LAN CLKOUT_LPC_1 CLK_PCI_KBC <24> @
B35 PCIE_CLK_XDP_N <96>

A39 CLKOUT_ITPXDP# A35
<73> CLK_PCIE_VGA# CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P PCIE_CLK_XDP_P <96>
B39
C
<73> CLK_PCIE_VGA
<20,73> PEG_CLKREQ# PEG_CLKREQ# U5 CLKOUT_PCIE_P4
PCIECLKRQ4#/GPIO22
GPU C
EC1801
SC10P50V2JN-4GP
B37
CLKOUT_PCIE_N5
1
A37
CLK_PCIE_REQ# T2 CLKOUT_PCIE_P5
PCIECLKRQ5#/GPIO23 @EMI@
2
HASWELL-6-GP-U
3D3V_S5_PCH
@
RN1807
SML1_CLK 8 1
LPC_AD[3..0] HSW_ULT_DDR3L 7 2
<24,65> LPC_AD[3..0]
Based on the swap report. CPU1G 7 OF 19 SML1_DATA
RN1806 SML0_DATA 6 3
LPC_AD2 8 1 LPC_LAD2_PCH LPC_LAD0_PCH AU14 AN2 MCP_GPIO11 SML0_CLK 5 4
LPC_AD1 7 2 LPC_LAD1_PCH LPC_LAD1_PCH AW12 LAD0 SMBALERT#/GPIO11 AP2 SMB_CLK
LPC_AD3 6 3 LPC_LAD3_PCH LPC_LAD2_PCH AY12 LAD1 LPC
SMBCLK AH1 SMB_DATA SRN2K2J-4-GP
LPC_AD0 5 4 LPC_LAD0_PCH LPC_LAD3_PCH AW11 LAD2 SMBUS SMBDATA AL2 CARD_PWR_EN
LPC_LFRAME#_PCH AV12 LAD3 SML0ALERT#/GPIO60 AN1 SML0_CLK
SRN0J-7-GP-U @ LFRAME# SML0CLK AK1 SML0_DATA RN1809
SML0DATA
<24,65> LPC_FRAME# R1801 1 2 0_0402_1% AU4 MCP_GPIO73 MCP_GPIO73 <16> SRN10KJ-6-GP
SML1ALERT#/PCHHOT#/GPIO73 AU3 SML1_CLK CARD_PWR_EN 8 1
Short Pad SML1CLK/GPIO75 AH3 SML1_DATA
SML1_CLK <24,26,76>
7 2
SML1DATA/GPIO74 SML1_DATA <24,26,76> <16,35> USB_OC#0_1
<24,25> SPI_CLK_R 33R2J-2-GP 1 2 R1806 PCH_SPI_CLK AA3 <20,24> EC_SCI# 6 3
0_0402_1% 1 @ 2 R1807 PCH_SPI_CS0# Y7 SPI_CLK AF2 TP_CL_CLK 1 TP1801 MCP_GPIO11 5 4
<24,25> SPI_CS0#_R SPI_CS0# CL_CLK
Short Pad Y4 AD2 TP_CL_DATA1 TP1802
AC2 SPI_CS1# SPI C-LINK
CL_DATA AF4 TP_CL_RST# 1 TP1803
0_0402_1% 1 @ 2 R1808 PCH_SPI_SI AA2 SPI_CS2# CL_RST#
<24,25> SPI_SI_R SPI_MOSI RE15
<24,25> SPI_SO_R 0_0402_1% 1 @ 2 R1809 PCH_SPI_SO AA4
SPI_MISO RE16
0_0402_1% 1 @ 2 R1811 PCH_SPI_DQ2 Y6 SMB_CLK 1 2
<25> SPI_WP# SPI_IO2
0_0402_1% 1 @ 2 R1812 PCH_SPI_DQ3 AF1 SMB_DATA 1 2
<25> SPI_HOLD# SPI_IO3
B B
2.2K_0402_5%
2.2K_0402_5%
3D3V_S5 3D3V_S0
HASWELL-6-GP-U
RE17
RE18
2
@ 1 2 3D3V_S0
R1815 R1814 1 2
1KR2J-1-GP 1KR2J-1-GP 10K_0402_5%
10K_0402_5%
2N7002KDW-GP
1
SMB_DATA 6 1
PCH_SMBDATA <12,13,55,62,96>
PCH_SPI_DQ3
5 2
PCH_SPI_DQ2 2nd = 84.2N702.E3F
3rd = 75.00601.07C 4 3
4th = 84.DMN66.03F
Q1801
PCH_SMBCLK <12,13,55,62,96>
SMB_CLK
A A

CPU (PCI-E/SMBUS/CLOCK/CL)
A00
5 4 3 2 1
5 4 3 2 1
Main Func = PCH

RTC_X1
1 2 RTC_X2
R1915 10MR2J-L-GP
X1901
1 4
D
RTC_AUX_S5 D
2
2 3 C1904
C1903 SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
1
XTAL-32D768KHZ-65-GP
PCH strap pin:
1
RTC_AUX_S5 R1903 R1901
Integrated SUS 1V VRM Enable @ R1913 330KR2J-L1-GP 1MR2J-1-GP
1 2 PCH_INTVRMEN
Low = External VRs
2
INTVRMEN 330KR2J-L1-GP
High = Internal VRs*
2
2
RE19 RE20 CPU1E HSW_ULT_DDR3L 5 OF 19
20K_0402_5% 20K_0402_5%
<24> RTCRST_ON
RTC_X1 AW5
1
1
RTCX1
1
RTC_X2 AY5
R1902 2 SM_INTRUDER# AU6 RTCX2 J5
INTRUDER# SATA_RN0/PERN6_L3 SATA3_PRX_HDDTX_N0 <56>
G
10KR2J-3-GP PCH_INTVRMEN AV7 H5 SATA3_PRX_HDDTX_P0 <56>

SRTC_RST# AV6 INTVRMEN RTC
SATA_RP0/PERP6_L3 B15 SATA3_PTX_HDDRX_N0 <56>
3 1 RTC_RST# AU7 SRTCRST# SATA_TN0/PETN6_L3 A15 SATA3_PTX_HDDRX_P0 <56>
HDD
2
RTCRST# SATA_TP0/PETP6_L3
S
2
J8
SC1U10V2KX-1GP
SATA_RN1/PERN6_L2 SATA_PRX_ODDTX_N1 <56>
1
G1901 H8
C1901
SATA_PRX_ODDTX_P1 <56>
Q1901 SATA_RP1/PERP6_L2 ODD
1
C1902 A17 SATA_PTX_ODDRX_N1 <56>
2N7002K_SOT23-3 SATA_TN1/PETN6_L2
GAP-OPEN
SC1U10V2KX-1GP B17 SATA_PTX_ODDRX_P1 <56>
2
C SATA_TP1/PETP6_L2 C
2
HDA_BITCLK AW8 J6
HDA_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
(#514849) HDA_RST# AU8 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 B14
HDA_SDIN0 AY10 HDA_RST#/I2S_MCLK# AUDIO SATA SATA_TN2/PETN6_L1 C15
<27> HDA_SDIN0 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1
AU12
HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
1TP_HDA_DOCK_EN# AW10 HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 E5
Layout: Place at the open door area. TP1902
HDA_DOCK_EN#/I2S1_TXD# SATA_RP3/PERP6_L0
AV10 C17
AY8 HDA_DOCK_RST#/I2S1_SFRM# SATA_TN3/PETN6_L0 D17
R1907 1 2 33R2J-2-GP HDA_BITCLK I2S1_SCLK SATA_TP3/PETP6_L0
<27> HDA_CODEC_BITCLK
<27> HDA_CODEC_SYNC R1908 1 @ 2 0_0402_1% HDA_SYNC V1 EC_SMI# EC_SMI# <24>

SATA0GP/GPIO34 U1 +V1.05S_ASATA3PLL
R1911
Short
1 @
Pad2 0_0402_1% HDA_RST# SATA1GP/GPIO35 V6 MCP_GPIO36
SATA_ODD_PRSNT# <56>
PCH strap pin: <27> HDA_CODEC_RST#
Short Pad
SATA2GP/GPIO36 AC1
SATA3GP/GPIO37 PROJECT_ID1 <15>
TP1901 1 PCH_JTAG_TRST# AU62
PCH_JTAG_TCK AE62 PCH_TRST# A12 SATA_IREF 0_0402_1% 1 @ 2 R1904
R1912 1 2 33R2J-2-GP HDA_SDOUT PCH_JTAG_TDI AD61 PCH_TCK SATA_IREF L11
Flash Descriptor Security Overide/ <27> HDA_CODEC_SDOUT PCH_TDI RSVD#L11 Short Pad
PCH_JTAG_TDO AE61 K10
Intel ME Debug Mode R1909 1 2 1KR2J-1-GP PCH_JTAG_TMS AD62 PCH_TDO JTAG
RSVD#K10 C12 SATA_RCOMP 1 2
<24> ME_UNLOCK PCH_TMS SATA_RCOMP
Low = Default * AL11 U3 SATA_LED# SATA_LED# <24,61>
AC4 RSVD#AL11 SATALED# R1906
HDA_SDOUT High = Enable RSVD#AC4
XDP_TCK_JTAGX AE63 3KR2F-GP
AV2 JTAGX
The internal pull-down is disabled after RSVD#AV2
PLTRST# deasserts
B Layout Note: B
HASW ELL-6-GP-U 4mil trace at break-out and 3
1D05S_VCCST 12-15mil trace with <0.2 ohms
@ and length total <= 500mils.
2 @ 1 PCH_JTAG_TDI
R1916 51R2J-2-GP 3D3V_S0
2 @ 1 PCH_JTAG_TDO
R1917 51R2J-2-GP RN1902
2 @ 1 PCH_JTAG_TMS SATA_ODD_PRSNT# 4 5
R1918 51R2J-2-GP EC_SMI# 3 6
2 @ 1 XDP_TCK_JTAGX MCP_GPIO55 2 7
<15,20> MCP_GPIO55
R1919 1KR2J-1-GP MCP_GPIO36 1 8
SRN10KJ-6-GP
Unused SATA[3:0]GP pins must be terminated to either
3.3V rail or GND using 8.2K to 10K on the 3D3V_S0
motherboard. Either pull-up or pull-down is acceptable. X01_0808 R1905
EC1901 @EMI@
1 2 HDA_CODEC_BITCLK SATA_LED# 2 1
1 @ 2 PCH_JTAG_TCK
R1920 51R2J-2-GP
SC10P50V2JN-4GP For EMI Reserved 10KR2J-3-GP
HDA_CODEC_RST# EC1902 1 2 SCD1U16V2KX-3GP
@EMI@
RTC_RST# EC1903 1 2 SCD1U16V2KX-3GP
A A
@EMI@

CPU (RTC/SATA/IHDA/JTAG)
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = PCH 1D05S_VCCST
1
HSW_ULT_DDR3L 10 OF 19
CPU1J R2018
3D3V_S5 1KR2J-1-GP
RE21
2 RE22 R2027
2
1 BATLOW# @
BATLOW# <17>
2 1 MCP_GPIO27 MCP_GPIO76 P1 D60 PCH_THERMTRIP 1 2 0R2J-2-GP
<18> MCP_GPIO76 BMBUSY#/GPIO76 THRMTRIP# H_THERMTRIP# <36>
MCP_GPIO8 AU2 V4 H_RCIN#
10K_0402_5% GPIO8 RCIN#/GPIO82 H_RCIN# <24>
MCP_GPIO12 AM7 T4 INT_SERIRQ
10K_0402_5% <17> MCP_GPIO12 LAN_PHY_PWR_CTRL/GPIO12 SERIRQ INT_SERIRQ <24>
MCP_GPIO15 AD6 CPU/ AW15 PCH_OPIRCOMP 1 2
3D3V_S5_PCH Y1 GPIO15 MISC PCH_OPI_RCOMP AF20
T3 GPIO16 RSVD#AF20 AB21 R2003
<20,56>
<25>
SATA_ODD_DA#
RTC_DET#
RTC_DET# AD5 GPIO17 RSVD#AB21 49D9R2F-GP Layout Note:
R2015 MCP_GPIO27 AN5 GPIO24
GPIO27
1.Referenced "continuous" VSS plane only.
10KR2J-3-GP 1 2 MCP_GPIO8 MCP_GPIO28 AD7
MCP_GPIO26 AN3 GPIO28 2.Avoid routing next to clock pins or noisy
D D
R2010 GPIO26 R6 signals.
1 2 MCP_GPIO46 MCP_GPIO56 AG6 GSPI0_CS#/GPIO83 L6
10KR2J-3-GP
GPIO56 GSPI0_CLK/GPIO84
3. Trace width: 12~15mil
MCP_GPIO57 AP1 N6
MCP_GPIO58 AL4 GPIO57 GSPI0_MISO/GPIO85 L8 LPSS_GSPI0_MOSI_BBS0_R SATA_ODD_PWRGT 4. Isolation Spacing: 12mil
<56>
WLAN_PLT_RST# AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 5. Max length: 500mil
MCP_GPIO44 AK4 GPIO59 GPIO GSPI1_CS#/GPIO87 L5
0_0402_1% 1 @ 2 R2029 GPU_EVENT_MCP# AB6 GPIO44 GSPI1_CLK/GPIO88 N7
<76> GPU_EVENT# GPIO47 GSPI1_MISO/GPIO89
U4 K2
Short Pad BOARD_ID2 Y3 GPIO48 GSPI_MOSI/GPIO90 J1
KB_DET# <15,62>
GPIO49 UART0_RXD/GPIO91 KB_LED_BL_DET <62>
BOARD_ID3 P3 K3
GPIO50 UART0_TXD/GPIO92 DBC_EN <15,52> 3D3V_S0
HSIOPC Y2 J2 RN2002
<21> HSIOPC HSIOPC/GPIO71 UART0_RTS#/GPIO93 PANEL_SIZE_ID <52>
MCP_GPIO13 AT3 SERIAL IO G1 SRN10KJ-6-GP
TP2002 MCP_GPIO14 AH4 GPIO13 UART0_CTS#/GPIO94 K4 8 1
TPAD14-OP-GP 1CAMERA_PWR_EN AM4 GPIO14 UART1_RXD/GPIO0 G2 <18,58> CLK_PCIE_WLAN_REQ3# H_RCIN# 7 2
0_0402_1% 1 @ 2 R2028 GC6_FB_EN_MCP AG5 GPIO25 UART1_TXD/GPIO1 J3 6 3
<24,75,76,83> GC6_FB_EN GPIO45 UART1_RST#/GPIO2 <20,56> SATA_ODD_DA#
Short Pad MCP_GPIO46 AG3 J4 INT_SERIRQ 5 4
GPIO46 UART1_CTS#/GPIO3 BLUETOOTH_EN <58>
F2 I2C0_SDA
EC_SWI# AM3 I2C0_SDA/GPIO4 F3 I2C0_SCL
<24> EC_SWI# GPIO9 I2C0_SCL/GPIO5
EC_SCI# AM2 G4 I2C1_SDA
<18,24> EC_SCI# GPIO10 I2C1_SDA/GPIO6 I2C1_SDA <62>
HDD_DEVSLP P2 F1 I2C1_SCL
<56> HDD_DEVSLP DEVSLP0/GPIO33 I2C1_SCL/GPIO7 I2C1_SCL <62> 3D3V_S0
C4 E3
PROJECT_ID2 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 COLOR_ENGINE 1
<15> PROJECT_ID2 DEVSLP1/GPIO38 SDIO_CMD/GPIO65
N5 D3 LPSS_SDIO_D0_CMNHDR TP2003
HDA_SPKR V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4 VRAM_ID1 TPAD14-OP-GP
<27> HDA_SPKR SPKR/GPIO81 SDIO_D1/GPIO67 C3 VRAM_ID2 I2C0_SDA 2 RE24 110K_0402_5%
3D3V_S5_PCH SDIO_D2/GPIO68 E2 I2C0_SCL 2 RE23 110K_0402_5%
SDIO_D3/GPIO69
HSIOPC R2007 1 2100KR2J-1-GP
2
HASWELL-6-GP-U
R2013
10KR2J-3-GP @ 3D3V_S0
@
RE25
1
R2021 1 2
0_0402_1% 1 @ 2 R2001 MCP_GPIO58 0R2J-2-GP I2C1_SDA 2 RE26 1
0_0402_1% 1 @ 2 R2002 MCP_GPIO44 I2C1_SCL 2 1
0_0402_1% 1 @ 2 R2004 MCP_GPIO56
0_0402_1% 1 @ 2 R2009 MCP_GPIO26 D2001 10K_0402_5%
1 2 INT_TP#_C 10K_0402_5%
<24,62> INT_TP#
MCP_R
RB751V-40H-GP
C 0_0402_1% 1 @ 2 R2016 MCP_GPIO14 C
0_0402_1% 1 @ 2 R2017 MCP_GPIO28
0_0402_1% 1 @ 2 R2020 MCP_GPIO13

@
0_0402_1% 1 @ 2 R2022 MCP_GPIO57 R2019 1 2
<15,19> MCP_GPIO55
0R2J-2-GP
MCP_GPIO46 R2030 1 @ 2
0_0402_1% Short Pad
3D3V_S5_PCH @
RN2012 MCP_GPIO8 R2031 1 2
SRN10KJ-6-GP 0R2J-2-GP 3D3V_S0 3D3V_S0
1 8 EC_SWI#
2 7 WLAN_PLT_RST#
1
3 6
USB_OC#4_5 <16>
4 5 RTC_DET# 4G@ R2033 2G@ R2023
PCH strap pin: 10KR2J-3-GP 10KR2J-3-GP
3D3V_S0 NO REBOOT
2
3D3V_S0
RN2011 1KR2J-1-GP VRAM_ID2 VRAM_ID1
SRN10KJ-6-GP
* Low = Enable (Default) R2006
1 8 PIRQA# HDA_SPKR 1 2 HDA_SPKR
PIRQA# <15> High = Disable
1
2 7 PEG_CLKREQ# R2024 1G@
PEG_CLKREQ# <18,73>
3 6 PIRQC# @ R2034 1G@ 2G@ R2034 4G@ R2024
PIRQC# <15>
4 5 BLUETOOTH_EN The internal pull-down is disabled after 10KR2J-3-GP 10KR2J-3-GP
PLTRST# deasserts
2
10K_0402_5%
PCH strap pin: 10K_0402_5%
SD028100280
3D3V_S0 SD028100280
Top-Block Swap Override mode
1
GPIO68 GPIO67
R2011 BIOS strap pin:
SDIO_D0 High = Enable "Top-Block swap" mode @ 1KR2J-1-GP
/ GPIO66 Low = Disable "Top-Block swap" mode (Default) BIOS VRAM Size Strap pin VRAM_ID2 VRAM_ID1
*
B 2 LPSS_SDIO_D0_CMNHDR B
The internal pull-down is disabled after PLTRST# deasserts 1G 0 0
Need SW double confirm if that's needed Top-Block swap

2G 0 1
PCH strap pin: 4G 1 0

3D3V_S5_PCH
3D3V_S0 TLS Confidentiality
1
1
BIOS strap pin: R2005 GPIO15

* Low = Disable Intel ME Crypto TLS (Default) @
R2014
1KR2J-1-GP
High = Enable Intel ME Crypto TLS
10KR2J-3-GP
BIOS UMA/DIS Strap pin BOARD_ID2 DIS@
2
The internal pull-down is disabled after MCP_GPIO15

2
RSMRST# deasserts.
UMA 0 BOARD_ID2
1
DIS 1
R2008 PCH strap pin:
10KR2J-3-GP 3D3V_S0
UMA@ Boot BIOS Strap Bit BBS
2
Boot BIOS * Low = SPI (Default) R2012

High = LPC @ 1KR2J-1-GP
Destination
3D3V_S0
2
The internal pull-down is disabled after PLTRST# deasserts LPSS_GSPI0_MOSI_BBS0_R

1
N16V@
BIOS strap pin: R2025 Need double confirm, GPIO table set to GPI if that's needed PH or PL
10KR2J-3-GP
BIOS UMA/DIS Strap pin BOARD_ID3
2
N15V-GM 0 BOARD_ID3
A A
1
N16V-GM 1 N15V@
R2026
10KR2J-3-GP
2

CPU (GPIO/CPU)
A00
5 4 3 2 1
5 4 3 2 1
Main Func = PCH

3D3V_S5_PCH
DSW
R2102
+3.3A_DSW _PRTCSUS 1 @ 2 0_0603_1%
1
+V1.05DX_MODPHY_PCH Short Pad Intel Recommend
D C2109 D
HSW_ULT_DDR3L
CPU1M 13 OF 19
2
SC1U10V2KX-1GP
K9
1D05V_S0 L10 VCCHSIO
M9 VCCHSIO RTC_AUX_S5
R2105 1 @ 2 0_0402_1% +V1.05S_AIDLE N8 VCCHSIO HSIO RTC AH11
P9 VCC1_05 VCCSUS3_3 AG10
Short Pad B18 VCC1_05 VCCRTC AE7 +VCCRTCEXT 1 2
+V1.05S_AUSB3PLL VCCUSB3PLL DCPRTC
1
C2105
SC1U10V2KX-1GP
+V1.05S_ASATA3PLL B11 C2110
VCCSATA3PLL SCD1U16V2KX-3GP 3D3V_S5
@
2
1 TP_VCCAPLLOPI_VAL Y20 SPI Y8
AA21 RSVD#Y20 OPI
VCCSPI
+V1.05S_APLLOPI VCCAPLL
1
W21
TP2102 VCCAPLL AG14 C2147
TPAD14-OP-GP VCCASW AG13 1D05V_S0
2
VCCASW SCD1U16V2KX-3GP
1 +V1.05A_VCCUSB3SUS J13 USB3
3D3V_S5_PCH +V3.3A_1.5A_HDA DCPSUS3 J11
VCC1_05 +V1.05S_CORE_PCH Broadwell(#514849): No series resistors (0 ohm).
R2108 H11 Haswell(#486713):Series resistor:5 ohm.
1 @ 2 0_0603_1% TP2107 +V3.3A_1.5A_HDA AH14 HDA VCC1_05 H15
TPAD14-OP-GP VCCHDA VCC1_05 AE8 R2110 C2114
VCC1_05
SC1U10V2KX-1GP
Short Pad AF22 5D1R2F-GP SC1U10V2KX-1GP
VCC1_05
C2116
1 +V1.05A_USB2SUS AH13 VRM AG19 +PCH_VCCDSW 1 2 PCH_VCCDSW _R 1 2
DCPSUS2 CORE DCPSUSBYP#AG19 AG20 BDW/HSW
2
DCPSUSBYP#AG20 AE9
VCCASW +1.05M_ASW
TP2108 AF9
3D3V_S5 +V3.3A_DSW _P 3D3V_S0 TPAD14-OP-GP AC9 VCCASW AG8 C2101
+V3.3A_PSUS VCCSUS3_3 VCCASW
C AA9 GPIO/LPC AD10 +V1.05A_SUS_PCH 1 TP2106 +V3.3A_DSW _P 1 2 +PCH_VCCDSW C
R2101 1 @ 2 0_0402_1% +V3.3A_DSW _P AH10 VCCSUS3_3 DCPSUS1#AD10 AD8 TPAD14-OP-GP
+V3.3A_DSW _P VCCDSW3_3 DCPSUS1#AD8
Short Pad R2112 1 @ 2 0_0402_1% +V3.3S_PCORE V8 SCD47U6D3V2KX-GP
W9 VCC3_3 3D3V_S0
Short Pad VCC3_3
1
1
C2123 J15 1D5V_S0 WistronSKB: match Intel design_20130417
C2136 THERMAL SENSOR VCCTS1_5 K14
DY SC10U6D3V3MX-GP VCC3_3 K16 (#489999_2013WW15)
SCD1U16V2KX-3GP
2
2
VCC3_3
SC1U10V2KX-1GP
C2128
+V1.05S_AXCK_DCB J18
1D05V_S0 +V1.05S_SSCF100 K19 VCCCLK SERIAL IO U8 +V3.3S_1.8S_LPSS_SDIO
2
A20 VCCCLK VCCSDIO T9
+V1.05S_AXCK_LCPLL VCCACLKPLL VCCSDIO
R2117 1 @ 2 0_0402_1% +V1.05S_SSCF100 +V1.05S_SSCF100 J17
R21 VCCCLK
Short Pad +V1.05S_SSCFF VCCCLK
C2137
T21 LPT LP POWER

VCCCLK
1
SC1U10V2KX-1GP
TP2103 TPAD14-OP-GP 1 TP_V1.05S_SSCF100 K18 SUS OSCILLATOR AB8 +V1.05A_AOSCSUS 1 TP2109

TP2104 TPAD14-OP-GP 1 TP_V1.05S_AXCK_DCB M20 RSVD#K18 DCPSUS4 TPAD14-OP-GP
TP2101 TPAD14-OP-GP 1 TP_V1.05S_SSCFF V21 RSVD#M20 TP2105
2
AE20 RSVD#V21 AC20 TP_V1.05S_APLLOPI 1 TPAD14-OP-GP

+V3.3A_PSUS VCCSUS3_3 RSVD#AC20
AE21 AG16 1D05V_S0
VCCSUS3_3 USB2 VCC1_05 AG17
VCC1_05
SC1U10V2KX-1GP
C2135
2
HASW ELL-6-GP-U
1D05V_S0 +V1.05S_SSCFF
@
B R2118 1 @ 2 0_0402_1% +V1.05S_SSCFF B
Short Pad
C2138
1
1D05V_S0 1D05V_HSIO
SC1U10V2KX-1GP
Short Pad
2
1 2
R2122 @ No support
0_0805_1% High Speed IO
+V3.3S_1.8S_LPSS_SDIO 3D3V_S0
R2103 1 @ 2 0_0402_1%
Short Pad
1
1D05V_HSIO
C2104
U2101 SC1U10V2KX-1GP
2
5V_S5 1 4 R2114
2 VDD S 5 HSIO_OUT 1 0R5J-5-GP
2
1D05V_S0 D S
R2123 3
1 2 HSIOPC_R 7 D 6
<20> HSIOPC ON GND DY
DY
SLG59M1470VTR_FC-TDFN9_1P5X2
1
0R2J-2-GP @
DY C2142
1
SC10U10V5KX-2GP
@
2
DY C2141
SC4D7U6D3V3KX-GP
A A
2

CPU (POWER1)
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = PCH
D D
HSW_ULT_DDR3L
CPU1Q 17 OF 19
DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3

DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 TP_DC_TEST_A4 1 TP2202
TP2201 1TP_DC_TEST_AY60 AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60 TP_DC_TEST_A60 1 TP2203
DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61
TP2204 1TP_DC_TEST_B2 B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62 TP_DC_TEST_A62 1 TP2205
DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1 TP_DC_TEST_AV1 1 TP2206
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 TP_DC_TEST_AW1 1 TP2207
DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW62
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 TP_DC_TEST_AW63 1 TP2208
C
DAISY_CHAIN_NCTF_AW63 C
HASWELL-6-GP-U
HSW_ULT_DDR3L
CPU1R 18 OF 19
N23
RSVD#N23 R23
RSVD#R23 T23
AT2 RSVD#T23
RSVD#AT2 U10
AU44 RSVD#U10
AV44 RSVD#AU44
D15 RSVD#AV44
RSVD#D15 AL1
RSVD#AL1 AM11
RSVD#AM11 AP7
F22 RSVD#AP7
RSVD#F22 AU10
H22 RSVD#AU10
B RSVD#H22 AU15 B
J21 RSVD#AU15
RSVD#J21 AW14
RSVD#AW14 AY14
RSVD#AY14
HASWELL-6-GP-U
A A

CPU (RSVD)
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = PCH
D D
HSW_ULT_DDR3L HSW_ULT_DDR3L
CPU1N 14 OF 19 CPU1O 15 OF 19
A11 AJ35 AP22 AV59

A14 VSS VSS AJ39 AP23 VSS VSS AV8
A18 VSS VSS AJ41 AP26 VSS VSS AW16
AA1 VSS VSS AJ63 AR11 VSS VSS AW50
AA58 VSS VSS AK23 AR15 VSS VSS AW51
AB10 VSS VSS AK3 AR17 VSS VSS AW59
AB20 VSS VSS AK52 AR23 VSS VSS AW60
AB22 VSS VSS AL10 AR31 VSS VSS AY11
AB7 VSS VSS AL13 AR33 VSS VSS AY16
AC61 VSS VSS AL17 AR39 VSS VSS AY18
AD21 VSS VSS AL20 AR43 VSS VSS AY22
AE10 VSS VSS AL26 AR52 VSS VSS AY30
C AE5 VSS VSS AL29 AT13 VSS VSS AY33 C
AE58 VSS VSS AL31 AT35 VSS VSS AY4
AF11 VSS VSS AL33 AT37 VSS VSS AY51
AF18 VSS VSS AL46 AT49 VSS VSS B20
AG1 VSS VSS AL51 AT61 VSS VSS B24
AG23 VSS VSS AL57 AU1 VSS VSS B32
AG62 VSS VSS AM1 AU20 VSS VSS B40
AG63 VSS VSS AM17 AU22 VSS VSS B44
AH17 VSS VSS AM23 AU24 VSS VSS B48
AH22 VSS VSS AN17 AU30 VSS VSS B60
AH24 VSS VSS AN23 AU33 VSS VSS C11
AH38 VSS VSS AN40 AV14 VSS VSS C38
B AH44 VSS VSS AN45 AV24 VSS VSS D12 B
AH49 VSS VSS AN46 AV28 VSS VSS D14
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ25 VSS VSS AP10 AV49 VSS VSS D29
VSS VSS VSS VSS
HASW ELL-6-GP-U
@
HASW ELL-6-GP-U
A A

CPU(VSS)
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = KBC R2446 53@ R2446 55@ R2446 52@ R2446 51@ R2446 03@ R2446 01@ R2446 04@ R2446 02@
10K_0402_1% 13.7K_0402_1% 17.8K_0402_1% 22.1K_0402_1% 137K_0402_1% 154K_0402_1% 200K_0402_1% 232K_0402_1%

SD034100280 SD034137280 SD034178280 SD034221280 SD034137380 SD034154380 SD034200380 SD034232380
VBAT 3D3V_AUX_KBC
VBAT
VBAT PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE MODEL_ID_DET(GPIO07) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
R2402 M00 (SA) 100.0K 10.0K 3.0V 53@ Van Gogh-HSW-OPS 100.0K 10.0K(64.10025.6DL) 3.0V
VBAT 1 @ 2 0_0603_1% R2446 55@ Van Gogh-HSW-UMA 100.0K 13.7K(64.13725.6DL) 2.902V
1
R2404 X00 (SB) 100.0K 20.0K 2.75V 64K9R2F-1-GP 52@ Van Gogh-BDW-OPS 100.0K 17.8K(64.17825.6DL) 2.801V
2
Short Pad 64.9K_0402_1% 51@ Van Gogh-BDW-UMA 100.0K 22.1K(64.22125.6DL) 2.702V
R2403 X01 (SC) 100.0K 33.0K 2.48V @ TBD 100.0K 27.0K(64.27025.6DL) 2.598V
2D2R3-1-U-GP TBD 100.0K 32.4K(64.32425.6DL) 2.492V
X02 (SD) 100.0K 47.0K 2.24V TBD 100.0K 37.4K(64.37425.6DL) 2.402V
2
3D3V_AUX_KBC_VCC TBD 100.0K 43.2K(64.43225.6DL) 2.304V
1
PCB_VER_AD A00 (1) 100.0K 64.9K 2.0V MODEL_ID_DET TBD 100.0K 49.9K(64.49925.6DL) 2.201V
Iris2-HSW-OPS 100.0K 57.6K(64.57625.6DL) 2.093V
1
Reserved 100.0K 76.8 1.87V Iris2-HSW-UMA 100.0K 64.9K(64.64925.6DL) 2.001V
2
C2402 @ R2406 @ R2407 Iris2-BDW-OPS 100.0K 73.2K(64.73225.6DL) 1.905V
2
D 1D05V_S0 @ @ 100KR2F-L1-GP Reserved 100.0K 100.0K 1.65V C2403 100KR2F-L1-GP Iris2-BDW-UMA 100.0K 82.5K(64.82525.6DL) 1.808V D
SC2D2U10V3KX-1GP
@
C2405
SCD1U16V2KX-3GP C2406
SC2D2U6D3V2MX-GP C2411
TBD 100.0K 93.1K(64.93125.6DL) 1.709V
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1
1
1
R2401 1 @ 2 0_0402_1% EC_VTT Reserved 100.0K 143.0K 1.358V TBD 100.0K 107K(64.10735.6DL) 1.594V
2
Short Pad C2404 TBD 100.0K 120K(64.12035.6DL) 1.499V
1
Reserved 100.0K 174.0K 1.204V 03@ Tulip-HSW-OPS 100.0K 137K(64.13735.6DL) 1.392V
SCD1U16V2KX-3GP
2
C2401 01@ Tulip-HSW-UMA 100.0K 154K(64.15435.6DL) 1.299V
Reserved 100.0K 215.0K 1.048V EC_AGND 04@ Tulip-BDW-OPS 100.0K 200K(64.20035.6DL) 1.099V
SCD1U16V2KX-3GP
2
EC_AGND 02@ Tulip-BDW-UMA 100.0K 232K(64.23236.6DL) 0.994V
Layout Note:
Need very close to EC
EC_AGND
KBC24
19 54 KROW[0..7] <62>
KROW0
46 VCC KBSIN0/GPIOA0/N2TCK 55 KROW1
76 VCC KBSIN1/GPIOA1/N2TMS 56 KROW2
3D3V_S0 88 VCC KBSIN2/GPIOA2 57 KROW3 ECSCI#_KBC 0_0402_1% 1 @ 2 R2408
VCC KBSIN3/GPIOA3 EC_SCI# <18,20>
115 58 KROW4 Short Pad 2
VCC KBSIN4/GPIOA4 59 KROW5 ECSMI#_KBC 0_0402_1% 1 @ R2409
KBSIN5/GPIOA5 EC_SMI# <19>
102 60 KROW6 Short Pad 2
AVCC KBSIN6/GPIOA6 61 KROW7 ECSWI#_KBC 0_0402_1% 1 @ R2410
KBSIN7/GPIOA7 EC_SWI# <20>

4 Short Pad
VDD KCOL[0..16] <62>
1
@ <42,43> AD_IA EC_VTT 12 53 KCOL0

C2413 VTT KBSOUT0/GPOB0/SOUT_CR/JENK# 52 KCOL1
SC2D2U10V3KX-1GP C2414 KBSOUT1/GPIOB1/TCK 51 KCOL2
2
1 2 SCD1U16V2KX-3GP 97 KBSOUT2/GPIOB2/TMS 50 KCOL3

EC_AGND GPIO90/AD0 KBSOUT3/GPIOB3/TDI
PCB_VER_AD 98 49 KCOL4
99 GPIO91/AD1 KBSOUT4/GPOB4 48 KCOL5 3D3V_S5 3D3V_AUX_KBC
<42> PSID_EC GPIO92/AD2 KBSOUT5/GPIOB5/TDO
<17,26,36> PCH_PWROK
100 47 KCOL6
108 GPIO93/AD3 KBSOUT6/GPIOB6/RDY# 43 KCOL7 3D3V_AUX_KBC
<17,38> PM_SLP_SUS# GPIO05/AD4 KBSOUT7/GPIOB7
BMON
96 42 KCOL8
GPIO04/AD5 KBSOUT8/GPIOC0
2
ALL_SYS_PWRGD assert, <19,61> SATA_LED# R2405 1 @ 2 0_0402_1% SATA_LED#_R 95 41 KCOL9
MODEL_ID_DET 94 GPIO03/EXT_PURST#/AD6KBSOUT9/GPOC1/SDP_VIS# 40 KCOL10 R2452 R2453 @ BAT_SCL 2 1
delay 10ms; PCH_PWROK assert. Short Pad GPIO07/AD7/VD_IN2 KBSOUT10/P80_CLK/GPIOC2 39 KCOL11 BAT_SDA 4.7K_0402_5% 2 1RE27
<61> SATA_LED#_R 1KR2J-1-GP 1KR2J-1-GP
KBSOUT11/P80_DAT/GPIOC3 38 KCOL12 4.7K_0402_5% RE28
101 KBSOUT12/GPO64/TEST# 37 KCOL13
<26> FAN1_DAC_1
1
105 GPIO94/DA0 KBSOUT13/GP(I)O63/TRIST# 36 KCOL14
<43> AD_IA_HW GPIO95/DA1 KBSOUT14/GP(I)O62/XORTR#
<20,75,76,83> GC6_FB_EN @1 R2451 2 GC6_FB_EN_KBC 106 35 KCOL15
0R2J-2-GP 107 GPIO96/DA2 KBSOUT15/GPIO61/XOR_OUT 34 KCOL16 ECRST# R2418 1 2 10KR2J-3-GP
<48,7> IMVP_PWRGD GPIO97/DA3 GPIO60/KBSOUT16/DSR1# 33 TP_ON# <62>
GPIO57/KBSOUT17/DCD1#
BAT_SCL 70 LPC_AD[3..0] <18,65>
<42,43> BAT_SCL GPIO17/SCL1/N2TCK
BAT_SDA 69 126 LPC_AD0
<42,43> BAT_SDA 67 GPIO22/SDA1/N2TMS LAD0/GPIOF1 127 LPC_AD1
<18,26,76> SML1_CLK GPIO73/SCL2/N2TCK LAD1/GPIOF2
R2417 68 128 LPC_AD2
<18,26,76> SML1_DATA GPIO74/SDA2/N2TMS LAD2/GPIOF3 3D3V_AUX_KBC
<52> LCD_TST
1 @ 2 0_0402_1% 119 1 LPC_AD3
<30> PM_LAN_ENABLE GPIO23/SCL3/N2TCK LAD3/GPIOF4
Short Pad 120 2 CLK_PCI_KBC <18>
<19> RTCRST_ON GPIO31/SDA3/N2TMS LCLK/GPIOF5
PROCHOT_EC 24 3 LPC_FRAME# <18,65> R2416 AC_IN# R2413 1 @ 2 100KR2J-1-GP
LCD_TST_EN 28 GPIO47/SCL4A/N2TCK LFRAME#/GPIOF6 7 PLT_RST#_EC 0_0402_1% 1 @ 2 BAT_IN# R2414 1 2 10KR2J-3-GP
<52> LCD_TST_EN GPIO53/SDA4A/N2TMS LRESET#/GPIOF7 PLT_RST# <17,30,36,52,58,65,73,96>
<62> TP_LOCK#
1 R2450 2 TP_LOCK#_C 26 Short Pad
0R2J-2-GP ECSWI#_KBC 123 GPIO51/TA3/N2TCK
GPIO67/SOUT1/N2TMS
2
PTP@
90 EC_SPI_CS#_C 2 R2419 R2419
1 33R2J-2-GP @
C GPIOC6/F_CS0# SPI_CS0#_R <18,25> C
92 EC_SPI_CLK_C 2 R2420 R2420
1 33R2J-2-GP C2415
72 GPIOC7/F_SCK 109 SPI_CLK_R <18,25>
<62> TPCLK CAP_LED# <62> SC220P50V2KX-3GP
1
71 GPIO37/PSCLK1 GPIO30/F_WP#/RTS1# 80 BAT_IN#
<62> TPDATA GPIO35/PSDAT1 GPIO41/F_WP#/PSL_GPIO41 BAT_IN# <42,43>
10 87 EC_SPI_DI_C 2 R2422 1 33R2J-2-GP 3D3V_S0
<36> ALL_SYS_PWRGD GPIO26/PSCLK2 GPIOC5/F_SDIO/F_SDIO0 SPI_SI_R <18,25>
<42> PWR_CHG_AD_OFF
11 86 EC_SPI_DO_C 2 R2423 1 33R2J-2-GP
GPIO27/PSDAT2 GPIOC4/F_SDI/F_SDIO1 SPI_SO_R <18,25>
AD_IA_HW2
25 91 PM_SUSACK# <17>
27 GPIO50/PSCLK3 GPIO81/F_WP#/F_SDIO2 77 SUSCLK_KBC 1 R2441 2 @ FAN_TACH1 R2415 1 2 10KR2J-3-GP
<52> BLON_OUT GPIO52/PSDAT3 GPIO00/32KCLKIN/F_SDIO3 SUS_CLK <17>
0_0402_1% 3D3V_AUX_S5 TOUCH_PANEL_INTR# R2443 1 @ 2 10KR2J-3-GP
DIS@ <26> FAN_TACH1 31
GPIO56/TA1 PSL_IN1#/GPI70
73 PSL_IN1#
Layout Note: Power Switch Logic(PSL)
R2437 <17,96> PM_PWRBTN# 117 93 PSL_IN2# Touch Panel PH internally.
GPIO20/TA2/IOX_DIN_DIO
PSL_IN2#/GPI06/EXT_PURST#
2
<15,82,83> DGPU_PWROK
1 2 DGPU_PWROK_KBC 63 74 PSL_OUT# Need very close to EC
64 GPIO14/TB1 PSL_OUT#/GPIO71 R2425
<17,36,45,46,47> PM_SLP_S3# GPIO01/TB2
0R2J-2-GP 330KR2J-L1-GP
29 ECSCI#_KBC 3D3V_S5
32 ECSCI#/GPIO54 85 ECRST# R2427
<52> EC_BRIGHTNESS
1
118 GPIO15/A_PWM EXT_RST# 122 0_0402_1% 1 @ 2 PSL_IN2#
<27> KBC_BEEP GPIO21/B_PWM KBRST#/GPIO86 H_RCIN# <20> <61> KBC_PWRBTN#
<61> BATT_WHITE_LED#
62 Short Pad LID_CLOSE# R2421 1 2100KR2J-1-GP
65 GPIO13/C_PWM 75 R2428 C2416
<76> OVER_CURRENT_P8# GPIO32/D_PWM VSBY 3D3V_AUX_S5
<62> KB_BL_CTRL
22 114 EC_VBKUP 1 @ 2 0_0402_1% RTC_AUX_S5 SC1U10V2KX-1GP USB_PWR_EN# R2412 1 @ 2100KR2J-1-GP
16 GPIO45/E_PWM/DTR1#_BOUT1 VBKUP 44 KBC_VCORF 1 2 R2430
<61> CHG_AMBER_LED# GPIO40/F_PWM/1_WIRE/RI1# VCORF
<17> KBC_DPWROK 81 13 PECI 1 2 <43> AC_IN# 0_0402_1% 1 @ 2 PSL_IN1# TP_LOCK#_C R2426 1 PTP@ 2100KR2J-1-GP
GPIO66/G_PWM/PSL_GPIO66 PECI H_PECI <4>
1 R2449 2 VD1_EN# 66 125 INT_SERIRQ <20> R2429 Short Pad
GPO33/H_PWM/VD1_EN# SERIRQ/GPIOF0
C2422
SC100P50V2JN-3GP
1KR2J-1-GP 6 ECSMI#_KBC @ 43R2J-GP
GPIO24
1
<26,42> VD_IN1
104 15 RSMRST#_KBC <17>
GPIO80/VD_IN1 GPIO36/TB3/CTS1#
<26> VD_OUT1#
110 21 PM_SLP_S4# <17,47>
2
112 GPIO82/IOX_LDSH/VD_OUT1 GPIO44/SCL4B 20
<17,76> AC_PRESENT GPIO84/IOX_SCLK/VD_OUT2 PSL_IN4#/GPI43 BOOST_MODE# <43>
ALL_SYS_PWRGD de-assert, 17 LID_CLOSE# <61>
PSL_IN3#/GPI42 23
delay 100ms; SYS_PWROK assert. GPIO46/SDA4B/CIRRXM ME_UNLOCK <19>
84
<17,96> SYS_PWROK
<35> USB_PWR_EN#
83 GPIO77/SPI_MISO 113 PCIE_WAKE# <17,30>
Layout Note:
82 GPIO76/SPI_MOSI GPIO87/CIRRXM/SIN_CR 14
LVDS backlight Control from PS8625 <58> WIFI_RF_EN GPIO75/SPI_SCK GPIO34/SIN1/CIRRXL S5_ENABLE <36> Need very close to EC 3D3V_AUX_S5 3D3V_AUX_S5
<17> PM_SUSWARN# 79
@ R2411 GPIO02/SPI_CS#
2
1 2 0R2J-2-GP 5
<24,52> TOUCH_PANEL_INTR# TOUCH_PANEL_INTR_KBC# 124 GND 18 R2431 C2417 1 2 SCD1U16V2KX-3GP
R2448 1 @ 2 0_0402_1% TP_WAKE_KBC# 121 GPIO10/LPCPD# GND 45
<20,62> INT_TP# 330KR2J-L1-GP
111 GPIO85/GA20 GND 78
Short Pad <58> E51_TxD
L_BKLT_EN_EC 9 GPIO83/SOUT_CR GND 89 D2401
R2432
1
GPIO65/SMI# GND
3
S
116
GND
2
G
<17> PM_CLKRUN#_EC
8 LID_CLOSE# 1 2 TOUCH_PANEL_INTR# <24,52> PSL_OUT# 1 2 KBC_ON#_GATE_L 1 2 KBC_ON#_GATE 2
30 GPIO11/CLKRUN# 103 EC_AGND R2434 @
<27> AMP_MUTE# GPIO55/CLKOUT/IOX_DIN_DIO AGND R2433 Q2402 D
0R2J-2-GP
1
1
1KR2J-1-GP 20KR2F-L-GP NTK3139PT1G_SOT723-3
@ RB751V-40-H-GP
NPCE285PA0DX-GP
0_0402_1%
1
R2435
<15> L_BKLT_EN R2444 1 @ 2 0_0402_1% L_BKLT_EN_EC Short Pad
2
3D3V_AUX_KBC
Short Pad
eDP backlight Control from PCH
KBC24 change to B2 version : 071.00285.0A0G
1
R2447
100KR2J-1-GP 3D3V_AUX_KBC
EC_AGND
Layout Note:
2
1
B R2436 B
Connect GND and AGND planes via either 10KR2J-3-GP

EC_GPIO47 High Active
2
0R resistor or connect directly. 3D3V_AUX_S5
2
R2424 @
R2438 0R2J-2-GP 3 1 S5_ENABLE
1
0R2J-2-GP 1 2 ECRST#
D
1 2 R2439
100K_0402_5% Q2403
@ 2N7002K_SOT23-3
C2418
2
SC1U10V2KX-1GP
PROCHOT_EC @
R2440
H_PROCHOT#_EC 1 @ 2 H_PROCHOT# <4,42,43,48> <26,36,76> PURE_HW_SHUTDOWN#
2 3
2
1
Short Pad Q2404

2
@ R2442 MMBT3906WT1G
1
0_0402_1%
1
G
100KR2J-1-GP C2421 @
SC47P50V2JN-3GP
3 1
2
2
S
Q2401
2N7002K_SOT23-3
A A

KBC Nuvoton NPCE285PA0DX
A00
5 4 3 2 1
5 4 3 2 1
Main Func = SPI Flash
SPI Flash ROM(8M) for PCH 3D3V_S5 3D3V_S5
1
D @ C2501 D
SC10U10V5KX-2GP C2502
1
SCD1U16V2KX-3GP
2
R2501 RE29 RE30
4K7R2J-2-GP 4.7K_0402_5% Single SPI shared flash connection (SPI Quad I/O mode)
4.7K_0402_5%
1
2
SPI25 3D3V_S5
<18,24> SPI_CS0#_R 1 BIOS 8

2 CS# VCC 7
<18,24> SPI_SO_R DO/IO1 HOLD#/IO3 SPI_HOLD# <18>
3 6 SPI_CLK_R <18,24>
<18> SPI_W P# WP#/IO2 CLK
4 5 SPI_SI_R <18,24>
1 GND DI/IO0
1
@EMI@ W 25Q64FVSSIQ-GP @EMI@ @EMI@
EC2502 EC2501 EC2503
SC4D7P50V2BN-GP SC4D7P50V2BN-GP SC10P50V2JN-4GP
2
2
C C
Source QUAD/DUAL fast read DUAL fast read
72.25Q64.K01 O O
72.25647.00A O O
Refer to "NCPE985x/ NPCE995x board design reference guide"
072.25B64.0001
O O
Main Func = RTC

+RTC_VCC 3D3V_AUX_S5 RTC_AUX_S5
B AFTP2502 1 +RTC_VCC B
@
D2501
RTC1
2
R2502 1
1KR2J-1-GP
2 1 2 1 RTC_PW R 3
- +
1
C2503 @
BAS40C-2-GP SCD47U6D3V2KX-GP
2
LOTES_AAA-BAT-054-K01
CONN@
1
R2504
2
A 10MR2J-L-GP A
G
2
3 1 RTC_DET# <20>
S
Q2505 Security Classification Compal Secret Data Compal Electronics, Inc.

2N7002K_SOT23-3 Issued Date 2015/01/20 Deciphered Date 2015/12/31 Title
Flash/RTC
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = Thermal Sensor
Fan controller1
5V_S0
@ R2605 FAN261
0R2J-2-GP
3D3V_S0 3D3V_S0 1 2 FON# 1 8
SC4D7U6D3V3KX-GP
2 FON# GND 7
C2611
D 5V_S0 VIN GND D
FAN_VCC1 3 6
SCD1U16V2KX-3GP
VOUT GND
1
4 5
C2605
<24> FAN1_DAC_1 VSET GND
2
1
1
AP2113MTR-G1-GP
RE31 RE32
3D3V_S0 Layout Note:
2.2K_0402_5%
2.2K_0402_5%
2N7002KDW -GP
2
Need 10 mil trace width. FAN1
6 1 THM_SML1_DATA
<18,24,76> SML1_DATA 5
GND2
C2601
5 2 4
SC10U6D3V3MX-GP
GND1
1
@ 4 3 @ R2606 3
C2602 1
0_0402_1% 2 FAN_TACH1_C 2 3
<24> FAN_TACH1 2
SCD1U16V2KX-3GP Q2601 FAN_VCC1 1
2
C2603
THM_SML1_CLK D2601 ACES_50224-0030N-001
SC2200P50V2KX-2GP
1
@ CONN@
RB551V30-GP
1
1
C2604 @ @
SC4D7U6D3V3KX-GP
<18,24,76> SML1_CLK Layout Note:
2
Signal Routing Guideline:
2
Trace width = 15mil
NCT7718_DXP
LMBT3904LT1G-GP
Q2603 THM26
1
@ 1 8 THM_SML1_CLK
2 C2606 C2607 2 VDD SCL 7 THM_SML1_DATA
C D+ SDA C
SC470P50V3JN-2GP SC2200P50V2KX-2GP 3 6 ALERT#
T8 ALERT#
2
T_CRIT# 4 D- 5 @ @
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
3
T_CRIT# GND
1
C2608
C2609
NCT7718_DXN
2.System Sensor, Put on palm rest NCT7718W -GP
2
Short Pad @
1
@ AFTP2802 1FAN_TACH1_C
FAN_TACH1 AFTP2801 1FAN_VCC1
0_0402_1% <17,24,36> PCH_PW ROK
@
R2601 FAN_VCC1
Layout Note:
2
2
G
C2812 close U2801 @ EC2602 EC2601
1
@EMI@ @EMI@
THERM_SYS_SHDN# 3 1
SCD1U16V2KX-3GP
SC10P50V2JN-4GP
S PURE_HW _SHUTDOW N# <24,36,76>
2
@ 0_0402_1%
SCD1U16V2KX-3GP
Layout Note: Q2602
C2610
1 @ 2 VD_OUT1#
Both DXN and DXP routing 10 mil trace width and 10 mil spacing. 2N7002K_SOT23-3 R2612
Short Pad
2
3D3V_S0
R2603 1 2 18K7R2F-GP ALERT#
R2604 1 2 2KR2F-3-GP T_CRIT# 3D3V_AUX_KBC

B B
R2607 1 @ 2 2KR2F-3-GP
R2602
THERM_SYS_SHDN# 1 @ 2
VD_OUT1# <24>
0R2J-2-GP
Close to KBC
Close to Thermal sensor VD_IN1 for system thermal sensor
3D3V_AUX_S5 3D3V_AUX_KBC
17.8K_0402_1%
24K9R2F-L-GP
1
1
R2609
R2608
@
2
VD_IN1 <24,42>
1
C2612
1
R2610 SCD1U16V2KX-3GP
NTC-100K-8-GP C2613
2
SC100P50V2JN-3GP
2
A VD_IN1_C 0_0402_1% 1 @ 2 R2611 A

Short Pad

THERMAL NCT7718W/Fan
A00
5 4 3 2 1
5 4 3 2 1
Main Func = Audio
D D
<29> LINE1_VREFO_R MIC2_VREFO <29>
<29> LINE1_VREFO_L AUD_AGND

Reserved for ALC3234 X01_0804 moat
SC2D2U6D3V2MX-GP
<29> AUD_HP1_JACK_L
SC4D7U6D3V3KX-GP
3D3V_S0 25mA +3V_AVDD EC2707 1 ESD@ 2 0_0402_5%
1
<29> AUD_HP1_JACK_R EC2706 1 ESD@ 2 0_0402_5%
0_0402_1% 1 @ 2 R2701 R2711 EC2705 1 ESD@ 2 0_0402_5%
1 C2705
SC1U10V2KX-1GP EC2704 1 ESD@ 2 0_0402_5%
Short Pad C2704
100KR2J-1-GP moat EC2703 1 ESD@ 2 0_0402_5%
C2702
1
1 2
2
1
C2701
SC4D7U6D3V3KX-GP +5V_AVDD 5V_S0
2
Close pin36 AUD_AGND
2
R2703
1
C2703 +3V_AVDD 1 @ 2 0_0603_1%
AUD_VREF
LDO1_CAP
+5V_AVDD
1.5A
CPVEE
SC1U10V2KX-1GP R2706
CBN
5V_S0 +5V_PVDD C2710
AUD_AGND Short Pad
1
C2711 1 2
Short Pad 0R5J-5-GP
Layout Note:
SCD1U16V2KX-3GP
SC4D7U6D3V3KX-GP
1 2
2
R2702 @ 0_0805_1% Place close to Pin 26
36
35
34
33
32
31
30
29
28
27
26
25
C2706 C2707 C2708 C2709 HDA27
1
1
Short Pad
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
CPVEE
HPOUT-L/PORT-I-L
LINE1-VREFO-L
MIC2-VREFO
LDO1-CAP
AVDD1
AVSS1
CPVDD
CBN
HPOUT-R/PORT-I-R
LINE1-VREFO-R
VREF
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1 2
R2704 @ 0_0805_1%
2
CBP 37 24 AUD_AGND AUD_AGND Layout Note:

CBP LINE2_L/PORT-E-L
Tied at point only under
38 23
AUD_AGND AVSS2 LINE2_R/PORT-E-R +RTC_VCC 3D3V_S5 Codec or near the Codec
C2712 1 2 SC10U6D3V3MX-GP LDO2_CAP 39 22 moat
AUD_AGND LDO2-CAP LINE1_L/PORT-C-L LINE1_L <29>
40 21 R2713 1 @ 2 R402-PAD-H16-GP
Layout Note: Layout Note: +3V_1D5V_AVDD AVDD2 LINE1_R/PORT-C-R LINE1_R <29>
Close pin41 Close pin46 41 20 V3D3_STB R2712 1 2 R402-PAD-H16-GP
+5V_PVDD PVDD1 NC#20
C AUD_SPK_L+ 42 19 MIC_CAP C2713 1 2 SC10U6D3V3MX-GP C
<29> AUD_SPK_L+ SPK-OUT-L+ MIC-CAP AUD_AGND
Layout Note: AUD_SPK_L- 43 18
moat Speaker trace width >40mil @ 2W4ohm speaker power<29> AUD_SPK_L- SPK-OUT-L- MIC2_R/PORT-F-R/SLEEVE SLEEVE <29> Layout Note:
AUD_SPK_R- 44 17 Width>40mil, to improve Headpohone Crosstalk noise
<29> AUD_SPK_R- SPK-OUT-R- MIC2_L/PORT-F-L/RING RING2 <29>
3D3V_S0 1D5V_S0 +3V_1D5V_AVDD AUD_SPK_R+ 45 16
Change it to sharp will be better.
<29> AUD_SPK_R+ SPK-OUT-R+ MONO-OUT Add 2 vias (>0.5A) when trace layer change.
R2705 1 @ 2 0_0402_1%
+5V_PVDD
46 15 JDREF R2707 1 @ 2 20KR2F-L-GP AUD_AGND
PVDD2 SPDIFO/FRONT_JD/JD3/GPIO3
GPIO0/DMIC-DATA
Short Pad
1
GPIO1/DMIC-CLK
R2710 1 2 0R2J-2-GP R2708 1 @ 2 0_0402_1% EAPD# 47 14
@ C2715 <24> AMP_MUTE# PDB MIC2/LINE2_JD/JD2 +3V_AVDD
Short Pad 48 13 1 2
SDATA-OUT
SC4D7U6D3V3KX-GP COMBO-GPI AUD_SENSE_A AUD_SENSE
R2722
2
SPDIF-OUT/GPIO2 HP/LINE1_JD/JD1 AUD_SENSE <29>
LDO3-CAP
SDATA-IN
R2709
DVDD-IO
PCBEEP
RESET#
Close pin40 49 200KR2F-L-GP AUD_SENSE_A 2 1
GND Layout Note:
DVDD
SYNC
DVSS
BCLK
AUD_AGND Place close to Pin 13 100KR2J-1-GP
ALC3234-CG-GP moat
10
11
12
+3V_AVDD
AUD_PC_BEEP
moat
LDO3_CAP
TP2702 1
Azalia I/F EMI +3V_AVDD
DMIC_DATA_R
C2718
C2719
C2717
1
EC2701
SC10P50V2JN-4GP
C2716
SC4D7U6D3V3KX-GP
SCD1U16V2KX-3GP
1
1
HDA_CODEC_SDOUT @EMI@
2
HDA_CODEC_BITCLK
2
2
EC2708 EC2709
SCD1U16V2KX-3GP
SC4D7U6D3V3KX-GP
1
1
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
@EMI@ @EMI@
2
R2714
0_0402_1% 1 @ 2 DMIC_DATA_R
<52> DMIC_DATA
Short Pad
1 2
0_0402_1% @ R2716 DMIC_CLK_R
<52> DMIC_CLK
Short Pad
0_0402_1%1 @ 2 R2719 CODEC_SDOUT_R
2
B <19> HDA_CODEC_SDOUT B
C2723 @ 0_0402_1%
Short
1 @
Pad
2 R2720 CODEC_BITCLK_R
<19> HDA_CODEC_BITCLK
SC22P50V2JN-4GP Short Pad
1
0_0402_1% 1 @ 2 R2718 HDA_CODEC_SDIN0

<19> HDA_SDIN0
Short Pad
HDA_CODEC_SYNC
Close pin3 <19> HDA_CODEC_SYNC
HDA_CODEC_RST#
<19> HDA_CODEC_RST#
D2701
<20> HDA_SPKR RE33 1 @ 2 0_0402_1% HDA_SPKR_R 3
Short Pad C2720
1 AUD_PC_BEEP_C 1 2AUD_PC_BEEP
<24> KBC_BEEP RE34 1 @ 2 0_0402_1% KBC_BEEP_R 2 SCD1U16V2KX-3GP

Short Pad
1
BAT54C-7-F_SOT23-3
R2717
1KR2J-1-GP
2
A A

Audio Codec ALC3234
A00
5 4 3 2 1
5 4 3 2 1
D D
C (Blanking) C
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = Audio
Layout Note: Speaker

Speaker trace width >40mil @ 2W4ohm speaker power
SPK1
D 0R3J-0-U-GP 2 R2904 1 EMI@ AUD_SPK_R+_C 1 5 D
<27> AUD_SPK_R+ 0R3J-0-U-GP 2 R2903 1 EMI@ AUD_SPK_R-_C 2 1 G5
<27> AUD_SPK_R- 0R3J-0-U-GP 2 R2902 1 EMI@ AUD_SPK_L+_C 3 2
<27> AUD_SPK_L+ 0R3J-0-U-GP 2 R2901 1 EMI@ AUD_SPK_L-_C 4 3
<27> AUD_SPK_L- 4 CONN Pin Net name
6 Pin1 SPK_R+
G6
ACES_50224-0040N-001_4P Pin2 SPK_R-
3
CONN@
EMI@ EMI@ EMI@ EMI@ Pin3 SPK_L+
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
EC2901
EC2902
EC2903
EC2904
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
1
1
Pin4 SPK_L-
DA13 DA14
2
@ESD@ @ESD@
1
AUD_SPK_L-_C 1 AFTP2901
AUD_SPK_L+_C 1 AFTP2902
AUD_SPK_R-_C 1 AFTP2903
AUD_SPK_R+_C 1 AFTP2904
C C
Universal Jack (Moved to I/O Board)

RE35 1 2 2.2K_0402_5%
<27> MIC2_VREFO RE36 1 2 2.2K_0402_5%
<27> RING2 0R3J-0-U-GP 2 R2906 1 EMI@ RING2_R

R2908 1 2 10R2F-L-GP AUD_HP1_JACK_L1 0R3J-0-U-GP 2 R2907 1 EMI@ AUD_PORTA_L_R_B RING2_R <63>
<27> AUD_HP1_JACK_L AUD_PORTA_L_R_B <63>
C2907 1 2 LINE1-L_C R2922 1 2 1KR2J-1-GP
<27> LINE1_L SC4D7U6D3V3KX-GP R2912 1 2 4K7R2J-2-GP JACK_PLUG
<27> LINE1_VREFO_L JACK_PLUG <63>
R2910 1 2 10R2F-L-GP AUD_HP1_JACK_R1 0R3J-0-U-GP 2 R2909 1 EMI@ AUD_PORTA_R_R_B AUD_PORTA_R_R_B <63>
<27> AUD_HP1_JACK_R C2908 1 2 LINE1-L_R R2921 1 2 1KR2J-1-GP 0R3J-0-U-GP 2 R2911 1 EMI@ SLEEVE_R
<27> LINE1_R SC4D7U6D3V3KX-GP R2913 1 2 4K7R2J-2-GP SLEEVE_R <63>
<27> LINE1_VREFO_R
R2920
EC2908
EC2907
R2919
EC2906
EC2905
1
1
<27> SLEEVE
1
@ @
2 @EMI@ @EMI@ @EMI@ @EMI@
2
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
2
2
10KR2J-3-GP
10KR2J-3-GP
B B
AUD_AGND AUD_AGND
R2923
JACK_PLUG 10 mils 1 @ 2 0_0603_1% 10 mils
AUD_SENSE <27>
Short Pad
1
@
C2901
SC10U6D3V3MX-GP
2
AUD_AGND
A A

SPEAKER/AUDIO JACK
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = LAN
Layout:
For RTL8111G(S) C3021: colse to Pin8
* Place C3021 to C3024 close to each VDD10 pin--3, 8, 22, 30 C3022 close to Pin30
For RTL8106E
* Place C3021,C3022 close to each VDD10 pin-- 8, 30
1000@
C3023: close to Pin3
LAN_SW@
LAN CHIP (10/100/1000M & 10/100M co-lay)
REGOUT 1 R3001 2 VDD10
8111G/LAN_SW
C3002,R3001:
D
Only for
8111G LAN_SW 8111G/LAN_SW D
0R3J-0-U-GP
C3019 SCD1U16V2KX-3GP
RTL8111 LDO mode. LAN_SW@ R3032 C3014
C3002 L3001
LAN_SW 2K49R2F-GP LAN_TXP_C_PCH_RXP4 1 2 SCD1U16V2KX-3GP
SC4D7U6D3V3KX-GP C3012
PCIE_PRX_LANTX_P4 <16>
1
1
1 2 RTL8111GUS-CG RTL8111G-CGT RTL8106EUS-CG RTL8106E-CGT 1 2 LAN_TXN_C_PCH_RXN4 1 2 SCD1U16V2KX-3GP
PCIE_PRX_LANTX_N4 <16>
8111G IND-4D7UH-242-GP C3016
LAN_SW PCIE_PTX_LANRX_P4_C
SCD1U16V2KX-3GP
PCIE_PTX_LANRX_P4_C <16>
2
2
1000@ 71.08111.W03 71.08111.U03 71.08106.003 071.08106.0003 PCIE_PTX_LANRX_N4_C
PCIE_PTX_LANRX_N4_C <16>
LAN_SW@
SWR mode LDO mode SWR mode LDO mode CLK_PCIE_LAN_P4 <18>
CLK_PCIE_LAN_N4 <18>
LAN_SW@
3D3V_LAN_S5
LAN_SW@
LANXOUT
10/100/1000M 10/100/1000M 10/100M 10/100M
LANXIN
VDD10
LED0 1 TP3003 TPAD14-OP-GP
RSET
LED1 1 TP3002 TPAD14-OP-GP
Layout: LED2 1 TP3001 TPAD14-OP-GP
LOM30 1000@
For RTL8111G(S)
* Place C3007 and C3008 close to each VDD33 pin-- 11, 32 100@
32
31
30
29
28
27
26
25
For RTL8106E LOM30
* Place C3003 and C3008 close to each VDD33 pin-- 23, 32
AVDD33
AVDD10
CKXTAL2
CKXTAL1
LED0
(GPO) LED1/GPO
(LED1) LED2
RSET
33
GND
RTL8111G-CG QFN 32P E-LAN CTRL
3D3V_LAN_S5 VDDREG
R3006
SA00005V700 C3018 1 2
40 mils 1 @ 2 0_0603_1% 1
(NC) REGOUT
24 REGOUT SC1U10V2KX-1GP
LAN_SW@ <31> LAN_MDI0P 2 MDIP0 23 VDDREG C3025 1 2 SCD1U16V2KX-3GP
(DVDD33) VDDREG
1
C3007 C3008 LAN_SW@ <31> LAN_MDI0N VDD10 3 MDIN0 22 VDD10 3D3V_S0

Short Pad AVDD10 (NC) (NC) DVDD10
1
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
100@ C3003 4 21 PCIE_WAKE#

8111G/LAN_SW LAN_SW LAN_SW <31> LAN_MDI1P MDIP1 LANWAKE# PCIE_WAKE# <17,24>
SCD1U16V2KX-3GP
C3008: close to Pin32 5 20 ISOLATE# 2 1

8106E
2
1
LAN_SW@ C3009 C3010 <31> LAN_MDI1N 6 MDIN1 ISOLATE# 19 PLT_RST#_LAN R3014
SCD1U16V2KX-3GP
MDIP2 (NC) (071.08106.0003)
2
<31> LAN_MDI2P PERST#
1
7 18 LAN_TXN_C_PCH_RXN4 1KR2J-1-GP
C3003: close to Pin23 <31> LAN_MDI2N MDIN2 (NC) HSON
SC4D7U6D3V3KX-GP
VDD10 8 17 LAN_TXP_C_PCH_RXP4 R3015
2
AVDD10 HSOP 15KR2J-1-GP
AVDD33 (NC)
MDIP3 (NC)
MDIN3 (NC)
REFCLK_N
REFCLK_P
CLKREQ#
X5R
2
HSIN
HSIP
C C
RTL8106E-CG_QFN32 Manual: 071.08106.0003
9
10
11
12
13
14
15
16
RTL8111G-CGT (71.08111.U03/LDO Mode): 10/100/1000M < 252 mW.
3D3V_LAN_S5 RTL8106E-CG (071.08106.0003): 10/100M <70mW.
3D3V_LAN_S5
<31> LAN_MDI3P 3D3V_S5
<31> LAN_MDI3N
1
1
C3004 C3005 3D3V_LAN_S5 R3033

RE37 RE38 CLK_LAN_REQ4#_R PCIE_WAKE# 1 2
1
10K_0402_5% 10K_0402_5% @ @ PCIE_PTX_LANRX_P4_C
PCIE_PTX_LANRX_N4_C 10KR2J-3-GP
CLK_PCIE_LAN_P4
2Q402_1 2
2
2
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
CLK_PCIE_LAN_N4
@ Layout: 3D3V_LAN_S5
Q3003 LMBT3904LT1G-GP 3D3V_LAN_S5
3 1 PLT_RST#_LAN
<17,24,36,52,58,65,73,96> PLT_RST# C3005: close to Pin11
1
@
R3016 C3011 R3003
1 @ 2 0_0402_1% LANXOUT 1 2 10KR2J-3-GP
1
Short Pad @
12P_0402_50V R3004
2
3D3V_LAN_S5 rise time must be controlled 10KR2J-3-GP
CLK_LAN_REQ#_EN
between 0.5 mS and 100 mS.
2
4
3
3D3V_S5 3D3V_LAN_S5 X3001
Q3004 XTAL-25MHZ-181-GP
NTK3139PT1G_SOT723-3
85mA
S
3 1
2
@
Q3002 LMBT3904LT1G-GP
1
1 3 CLK_LAN_REQ4#_R
G
<15,18> CLK_PCIE_LAN_REQ4#
2
1
B C3013 R3021 B
1
10KR2J-3-GP C3015 C3017

SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP
SC1U10V2KX-1GP C3001 R3005 1 @ 2 0_0402_1%

R3022 DY
2
@ LANXIN 1 2
Short Pad
2
1 2 PM_LAN_ENABLE_R
10P_0402_50V
LAN_ENABLE_R_C
20KR2J-L2-GP
<24> PM_LAN_ENABLE
1
R3023
2
100KR2J-1-GP
G
2
3 1
1.0V Source
S
R3001 C3002 C3023 C3024 C3007 L3001 C3012 C3019 C3009 C3010 C3003
Q3001
2N7002K_SOT23-3
RTL8111G-CGT LDO X
(71.08111.U03) O O O O O X X X X X
RTL8111GUS-CG
SWR X X O O O O O O O O X
(71.08111.W03)/
RTL8106EUS-CG
(71.08106.003)
A RTL8106E-CG A
LDO X X X X X X X X X X O
(071.08106.0003)

LAN RTL8106
A00
5 4 3 2 1
5 4 3 2 1
Main Func = LAN
LAN TransFormer (10/100/1000M & 10/100M co-lay)

EU3101
LAN_MDI0P 1 9 LAN_MDI0P
D D
LAN_MDI0N 2 8 LAN_MDI0N
MCT1 LAN_MDI1P 4 7 LAN_MDI1P

MCT3
MCT2 LAN_MDI1N 5 6 LAN_MDI1N
MCT0
<30> LAN_MDI3N XF3102

1 2 3
EC3108 SC10P50V2JN-4GP 6 7 MDO3-
@EMI@ 5 TD- TX- 8 MDO3+
TD+ TX+
2
2
2
2
R3104
R3103
R3102
R3101
<30> LAN_MDI3P 4 9 MCT0 @ESD@
1 2 TDCT TXCT
EC3107 SC10P50V2JN-4GP EU3102
@EMI@ 3 10 MCT1 LAN_MDI2P 1 9 LAN_MDI2P
RDCT RXCT
75_0603_5%
75_0603_5%
75_0603_5%
75_0603_5%
<30> LAN_MDI2N 2 11 MDO2-
1
1
1
1
1 2 1 RD- RX- 12 MDO2+ LAN_MDI2N 2 8 LAN_MDI2N
EC3106 SC10P50V2JN-4GP RD+ RX+
@EMI@ LAN_MDI3P 4 7 LAN_MDI3P
MCT
<30> LAN_MDI2P NS14-1 LF 10/100 BASE-TX
1 2 1000@ LAN_MDI3N 5 6 LAN_MDI3N
EC3105 SC10P50V2JN-4GP
@EMI@
1
C3101 3
SC100P3KV8JN-2-GP
2
LANGND @ESD@
C C
<30> LAN_MDI1N XF3101

1 2
EC3104 SC10P50V2JN-4GP 1 12 MDO1-
@EMI@ 2 RD+ RX+ 11 MDO1+
3 RD- RX- 10 MCT2 LANGND
<30> LAN_MDI1P RDCT RXCT
1 2
EC3103 SC10P50V2JN-4GP
@EMI@ 4 9 MCT3 RJ45
5 TDCT TXCT 8 MDO0-
LOM_TCT
<30> LAN_MDI0N TD+ TX+

1 2 6 7 MDO0+
EC3102 SC10P50V2JN-4GP TD- TX-
@EMI@
<30> LAN_MDI0P NS14-1 LF 10/100 BASE-TX
1 2 MDO0+ 1 10
EC3101 SC10P50V2JN-4GP TX0+ GND
@EMI@ MDO0- 2 9
TX0- GND
MDO1+ 3
RX1+
1
C3106
SCD01U50V2KX-1GP MDO2+ 4
TX2+
Layout note: Layout note:
2
MDO2- 5
30 mil spacing between MDI differential pairs. 30 mil spacing between MDI differential pairs. TX2-
MDO1- 6
RX1-
Follow Reference Schematic 0.01uF~0.4uF
MDO3+ 7
TX3+
MDO3- 8
B TX3- B
SANTA_130456-661
CONN@
A A

XFOM&RJ45
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = Card Reader

The maximum range of the PMOS output current in RTS5170 (Card Reader IC) is 400mA
3D3V_S0 3D3V_CARD_S0
D D
C3206
SDREFG 1 2
1
C3205
SC4D7U6D3V3KX-GP
SCD1U16V2KX-3GP
C3201 SC1U10V2KX-1GP
C3203
1 2 V18
2
SC1U10V2KX-1GP
For EMI
Layout: close to U3201
EMI@
24
23
4
7
U3201 EC3201 1 2
3V3_IN
V18
CARD_3V3
SDREG
XD_D7
XD_CD#
SC10P50V2JN-4GP
R3202 0_0402_1%
<33> SD_WP 1 @ 2 SD_WP_5170 8 15 SD_CLK_5170 R3201 1 EMI@ 2 SD_CLK <33>
9 SP1 SP8 16 33R2J-2-GP
Short Pad 10 SP2 SP9 18
<33> SD_D1 SP3 SP10 SD_CMD <33>
<33> SD_D0 11 19
C 12 SP4 SP11 20 C
SP5 SP12 SD_D3 <33>
<33> SD_CD# 13 21 SD_D2 <33>
14 SP6 SP13 22
SP7 SP14
GPIO0
RREF
GND
DM
DP
RTS5170-GR-GP
2
3
17
25
RREF
USB_PN7_R
1
USB_PP7_R CR_GPIO0 1 TP3201 3D3V_CARD_S0
R3203
6K2R2F-GP
1
C3202 @
SCD1U16V2KX-3GP
DY C3204
B SCD01U50V2KX-1GP B
2
R3204
0R2J-2-GP EMI@
1 2
TR3201
<16> USB_PN7 3 4 USB_PN7_R
3 4
<16> USB_PP7 2 1 USB_PP7_R

2 1
WCM-2012HS-900T_4P
@EMI@
R3205
0R2J-2-GP
1 2
EMI@
A A

Card Reader-RTS5170
A00
5 4 3 2 1
5 4 3 2 1
Main Func = Card Reader
3D3V_CARD_S0
D D
3D3V_CARD_S0
CARD1
C3301 400mA
1
1
SCD1U16V2KX-3GP
@ 4 NP1
SC4D7U6D3V3KX-GP
C3303 VDD NP1 NP2

C3302
SC10U10V5KX-2GP NP2
2
2 <32> SD_CMD 2
5 CMD 12
<32> SD_CLK CLK 12
<32> SD_CD# R3301 1 @ 2 0_0402_1% SD_CD_R# 10 13
11 CD 13 14
<32> SD_WP Short Pad WP 14 15
7 15
<32> SD_D0 DAT0
<32> SD_D1 8
9 DAT1 3
<32> SD_D2 DAT2 VSS
<32> SD_D3 1 6
CD/DAT3 VSS
CARDBUS11P-SKT-8-GP
C CONN@ C
For EMI Reserved SD_CMD 1 AFTP3302

SD_CLK 1 AFTP3303
SD_CD_R# 1 AFTP3304
SD_WP SD_WP 1 AFTP3305
SD_D0 1 AFTP3306
SD_D1 1 AFTP3307
SD_D0 SD_D2 1 AFTP3308
SD_D3 1 AFTP3309
3D3V_CARD_S0 1 AFTP3310
SD_CD_R#
SD_CMD
SD_D3
B SD_D2 B
SD_D1
EC3301
EC3302
EC3303
EC3304
EC3305
EC3306
EC3307
SC4D7P50V2BN-GP
SC4D7P50V2BN-GP
SC4D7P50V2BN-GP
SC4D7P50V2BN-GP
SC4D7P50V2BN-GP
SC4D7P50V2BN-GP
SC4D7P50V2BN-GP
1
1
@EMI@
@EMI@
@EMI@
@EMI@
@EMI@
@EMI@
@EMI@
2
A A

Card Reader-RTS5170
A00
5 4 3 2 1
5 4 3 2 1
Main Func = USB3.0 Port1

USB2.0 Port2 and USB2.0 Port3 are on IOBD USB3.0 Port1
R3403
2 1
@EMI@ USB1
0R2J-2-GP U3402 1 2 USB_PN0_C
USB30_VCCC VBUS D-
TR3404 USB3_PRX_CTX_N0_C 1 1 10 9USB3_PRX_CTX_N0_C 3 USB_PP0_C
2 1 USB_PN0_C D+
<16> USB_PN0
D USB3_PRX_CTX_P0_C 2 2 9 8USB3_PRX_CTX_P0_C USB3_PRX_CTX_N0_C 5 D
STDA_SSRX-
3
USB3_PRX_CTX_P0_C 6 7
3 4 4 4 STDA_SSRX+ GND_DRAIN
USB_PP0_C USB3_PTX_CRX_N0_C 7 7USB3_PTX_CRX_N0_C
3
<16> USB_PP0 ESD@
USB3_PTX_CRX_N0_C 8
5 5 STDA_SSTX- AZC199-02SPR7G_SOT23-3
HCM2012GA900AE_4P USB3_PTX_CRX_P0_C 6 6USB3_PTX_CRX_P0_C USB3_PTX_CRX_P0_C 9 10
STDA_SSTX+ GND EU3403
1
EMI@ 11
3 3 12 GND 4
1
13 CHASSIS#12 GND
R3404 8 CHASSIS#13
2 1
@EMI@ L05ESDL5V0NA-4_SLP2510P8-10-9 SKT-USB13-111-GP
ESD@
0R2J-2-GP
CONN@
USB2.0/3.0 filter use SM070003Q00
USB30_VCCC 1 AFTP3401
C3404 EMI@
R3408 R3410
EMI@
1 2 USB3_PTX_CRX_P0_R 2 1 USB3_PTX_CRX_P0_C <16> USB3_PRX_CTX_P0 2 1 USB3_PRX_CTX_P0_C
<16> USB3_PTX_CRX_P0
SCD1U16V2KX-3GP
0R2J-2-GP 0R2J-2-GP
TR3402 TR3403
2 1 2 1
C C
3 4 3 4
S COM FI_ CHILISIN CMMI21T-670Y-N S COM FI_ CHILISIN CMMI21T-670Y-N

@EMI@ @EMI@
C3403 EMI@
R3409 R3411
EMI@
1 2 USB3_PTX_CRX_N0_R 2 1 USB3_PTX_CRX_N0_C <16> USB3_PRX_CTX_N0 2 1 USB3_PRX_CTX_N0_C
<16> USB3_PTX_CRX_N0
SCD1U16V2KX-3GP
0R2J-2-GP 0R2J-2-GP
USB2 (USB2.0) CMC

R3412
1 2
@EMI@
B
3
0R2J-2-GP
TR3405
4 USB_PN1_C
USB ESD Diode B
<16> USB_PN1 USB_PN1_C <63>

EU3404 USB20_VCCA
<16> USB_PP1 2 1 USB_PP1_C
USB_PP1_C <63>
USB_PP1_C 1 6 USB_PN1_C
HCM2012GA900AE_4P I/O1 I/O4
EMI@ 2 5
GND VDD
R3413
USB_PP2_C 3 4 USB_PN2_C
I/O2 I/O3
1
1 2 C3406
@EMI@ Layout Note:
Close to CON1 AZC099-04S-1-GP SCD1U16V2KX-3GP @
2
0R2J-2-GP @ESD@
USB3 (USB2.0) CMC Layout Note:

R3414 Close to CON1
1 2
0R2J-2-GP @EMI@
TR3406
<16> USB_PN2 2 1 USB_PN2_C
USB_PN2_C <63>
<16> USB_PP2 3 4 USB_PP2_C

USB_PP2_C <63>
A HCM2012GA900AE_4P A
EMI@
R3415
1 2
@EMI@ Layout Note:
Close to CON1
0R2J-2-GP Security Classification Compal Secret Data Compal Electronics, Inc.
USB3.0 CONN
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1

USB3.0 Port1 Layout Note: Close USB1
D D
USB30_VCCC
2A
USB30_VCCC
5V_S5
U3504 DY
C3508
C3507
1
1
5 1 TC3501 @
SC1U10V2KX-1GP
IN OUT 2 C3512 C3513
GND SC100U6D3V6MX-GP
1
4 3
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
<24,35> USB_PW R_EN# USB_OC#0_1 <16,18,35>
2
C3510 EN FLG
SCD1U16V2KX-3GP
Active Low
SC1U10V2KX-1GP
2
SY6288D20AAC_SOT23-5

C C

B B
USB2.0 Port3 (IO Board)
USB20_VCCA
5V_S5 2A
Support 2A USB20_VCCA Layout Note: Close CON1
U3505
C3517
C3518
SC1U10V2KX-1GP
1
1
5 1 @
IN OUT 2 C3515
4 GND 3
DY
SC22U6D3V5MX-2GP
2
2
<24,35> USB_PW R_EN# EN FLG USB_OC#2_3 <16>
SCD1U16V2KX-3GP
Active Low
1
1
@
C3504 SY6288D20AAC_SOT23-5
0_0402_1%
2
R3501
SCD1U16V2KX-3GP
Short Pad
2
USB_OC#0_1 <16,18,35>
A A

USB Power SW
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = Power Plane & Sequence
Power Good
3D3V_S0
ROSA Run Power
1
D D
R3601
1KR2J-1-GP
@
<47> 1D35V_VTT_PW RGD R3610 1 2 0_0402_1%
2
Short
@
Pad
<46,7> 1D05V_VTT_PW RGD R3611 1 2 0_0402_1% ALL_SYS_PW RGD <24>
3D3V_AUX_S5
Short Pad
1 2 PS_S3CNTRL
DY
R3607 @
100KR2J-1-GP
D G S
X01_0721
6
@ Q3601 5V_S5
U3601 5V_S0
2N7002KDW -GP DY
1 13 5V_S0
1
2nd = 84.2N702.E3F S G 2 VIN1#1 VOUT1#13 14 3D3V_S0

D VIN1#2 VOUT1#14
3rd = 75.00601.07C 5V_S0 Comsumption
3D3V_S5 6 8
4th = 84.DMN66.03F @ 7 VIN2#6 VOUT2#8 9 Peak current 5A
1 2 3V5V_S0_ON VIN2#7 VOUT2#9
<17,24,45,46,47> PM_SLP_S3#
R3609 0_0402_1% 12 3V5V_CT1
<17,24,26> PCH_PW ROK Short Pad 4
VBIAS
SS1
SS2
10 3V5V_CT2 3D3V_S0
1
C C
C3601
SC470P50V2KX-3GP
C3602
SC470P50V2KX-3GP
C3605
SC10U6D3V3MX-GP
C3603
SC10U10V5KX-2GP
3D3V_S0 Comsumption
1
3 11
Peak current 2.5A
2
5 EN1 GND 15
EN2 GND
2
EM5209VF DFN 14P DUAL LOAD SW
@
R3608
1D05V_S0 1 DY 2 H_THERMTRIP# <20>
1KR2J-1-GP
B B
@ Q3602
MMBT2222A-3-GP
3
<4> H_THERMTRIP_EN H_THERMTRIP_EN 2
DY
1
@
R3606
C3604 @
1
1 2 SCD1U16V2KX-3GP
<17,24,30,52,58,65,73,96> PLT_RST# DY
DY
2
4K7R2J-2-GP
1
R3605 @
DY 2K2R2J-2-GP
2
D3602
2 1 PURE_HW _SHUTDOW N# <24,26,76>
<44> 3V_5V_EN
BAS16_SOT23-3
1
@ 1 2 S5_ENABLE <24>
R3602
DY R3603
200KR2F-L-GP
1KR2J-1-GP
A A
2
Check R3603 is 1k or 2k.

Power Plane Enable
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = DIMM1

Main Func = DIMM2
Layout Note:
Place Close DIMM1
D D
DDR_VREF_S3 1D35V_S3
1
@ R3710
0R2J-2-GP R3701
1K8R2F-GP
DY
2R2F-GP
2
R3702
1 2
Layout Note: <5> DDR_W R_VREF01 M_VREF_DQ_DIMMA
Place Close DIMMs
1
DDR_VREF_S3 C3702 R3709
1D35V_S3 SCD022U16V2KX-3GP 1K8R2F-GP
2
+V_VREF_PATH1
2
1
1
1
R3704 @ R3711
0R2J-2-GP R3706 24D9R2F-L-GP
1K8R2F-GP
SA_DIMM_VREFDQ DY
2
2
2
2R2F-GP
1 R3708 2
C DIMM1 M_VREF_CA_DIMMA +V_SM_VREF_CNT <5>
C
1
C3701
SCD022U16V2KX-3GP Layout Note:
2
1
Place Close DIMM2
R3703 +V_VREF_PATH3
1
1K8R2F-GP
R3707
24D9R2F-L-GP DDR_VREF_S3 1D35V_S3
2
2
1
1
@ R3712
0_0402_1% 0R2J-2-GP R3716
R3705 1K8R2F-GP
Short Pad
DY
SA_DIMM_VREFDQ
2
2
R3713
1 2
DIMM2 M_VREF_CA_DIMMB <5> DDR_W R_VREF02
2R2F-GP
M_VREF_DQ_DIMMB
1
C3703 R3714
SCD022U16V2KX-3GP 1K8R2F-GP
2
+V_VREF_PATH2
2
1
R3715
B 24D9R2F-L-GP B
2
A A

S3 Reduction Circuit
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = Power Plane & Sequence

NODS3@
3D3V_S5 3D3V_S5_PCH
R3801
1 2
D NON DS3 D
0R5J-5-GP
3D3V_S5
DS3@ C3801
1
3D3V_S5_PCH
SC1U10V2KX-1GP
DS3 2
U3801 DS3@
1 8
2 GND DS3OUT#8 7
C 3 IN#2 OUT#7 6 C
<17,24> PM_SLP_SUS# 1 DS3 2 DS3_PWRCTL 4 IN#3 OUT#6 5
DS3@ R3802 EN OC# C3802 DS3@
1
0R2J-2-GP
SC1U10V2KX-1GP
SY6288C10CAC-GP
DS3
2
RdsON: 100m ohm
DS3
B B
A A

DSW
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
A A

(Reserved) 1D05_M
A00
LA-B483P
5 4 3 2 1
(Blanking)

Reserved
A00
LA-B483P
5 4 3 2 1
D D
C
(Blanking) C
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = ADT Input 5V_S5
1
PR4202
1
3D3V_S5
15K_0402_1%
PR4203
3
E
PQ4202 10K_0402_1%
2
B
PQ3802_1 2 3D3V_S5
LMBT3904LT1G_SOT23-3
2
1
2
C
1
PR4209 PSID_DISABLE#_R_C
PR4204
100K_0402_1%
Layout Note: 2.2K_0402_1%
2
@ D4203
G
2
PSID Layout width > 25mil
2
PQ4201 PR4205 BAV99W-7-F 3P
@ PR4217 3 FDV301N-G_SOT23-3
D
X01_0814-1 PS_ID_R 2 1 PS_ID_R2
1
PS_ID 1
33_0402_1%
2
PSID_EC [24]
D
S
0_0603_5%
Reserve for 68.00084.771
2
JGND @ EL4204 @ PR4206 @
0_0805_5% PD4204 33_0402_1%
1 2 PESD24VS2UT_SOT23-3 1 2
@ EL4203
0_0805_5%
1
1 2
Pin Definition: TBD
DCIN1 60ohm@100MHz
8
GND 7 DCR=0.02 ohm
GND Max current = 6000mA
6 PU4201
6 5 +DC_IN AD+
5
4
4 X01_0729 AON7403L_DFN8-5
3 1
3
0.01U_0402_50V7K
0.01U_0402_50V7K
2 2 @ @
1
2 1 @ PD4201 3 5
PC4203
EC4201 EC4202
0.01U_0402_50V7K
PC4205
PC4204
2
2
1
10U_0805_25VAK
@ PC4201
PC4206
2
2
10U_0805_25VAK
10U_0805_25VAK
PR4214 SMBFJ24A_SMB-FL2 PC4202 PR4207

ACES_50458-00601-001 @ EL4201 3.3K_1206_5% 0.1U_0603_50V7K 1U_0603_25V6K 200K_0603_5%
1
@ @ 0_0805_5%
1
2
1 2
3
PQ3809_D
PQ4205
1
Id=-9.6A
LMUN5236T1G NPN SOT323-3

JGND JGND AD_OFF_L 2 PR4208
Qg=-25nC
1
47K_0603_5%
@ EL4202 @ Rdson=18~30mohm
0_0805_5% PQ4206
2
1 2 2N7002KW_SOT323-3 TR LMUN5113T1G PNP SOT323
1 3 2 AD_OFF_R
PQ4204
Reserve for 68.00084.771
D
1
C C
X01_0815 PWR_CHG_AD_OFF_R
3
G
2
2 1
@ PR4210 0_0402_5%
[24] PWR_CHG_AD_OFF
B B
A A

DCIN
A00
5 4 3 2 1
5 4 3 2 1
Main Func = M-BAT Input

D D
BT+
1
EC4304 @ EC4303
2
Batt Connecter
0.1U_0402_25V6
0.1U_0603_50V7K @ PD4302
@ SSM14PT_SMA2
2
BATT1
10
9 GND
8 GND
8
X01_0811
4 5 7
3 6 PBAT_SMBCLK1 6 7
[24,44] BAT_SCL 6
2 7 R4302 100_0402_1% PBAT_SMBDAT1 5
[24,44] BAT_SDA 5
1 8 2 1 PBAT_PRES1# 4
[24,44] BAT_IN# 4
2 1 SYS_PRES1# 3
100_0804_8P4R_5% 2 3
RN4301 @ R4301 1 2
0_0402_5% 1
SUYIN_200277GR008M270ZR
C C
1
EC4301 EC4305
1
EC4302
15P_0402_50V8J
X01_0804
10P_0402_50V8J
10P_0402_50V8J
2
2
2
@ @
Placement: Close to Batt Connector
BAT_SDA
BAT_SCL
1 BAT_IN#
1
D4302 D4303 D4301
BAV99W -7-F 3P BAV99W -7-F 3P BAV99W -7-F 3P

B B
2
3
3D3V_AUX_KBC
A A

BATT CONN
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = Charger
D D
AD+_TO_SYS DCBATOUT
PU4402 PR4402 PU4403
0.01_1206_1% BT+
AON7403L_DFN8-5 AON7403L_DFN8-5
AD+
1 1 4 1
2 2
5 3 2 3 3 5
AD+ CHARGER_SRC DCBATOUT
2
@ PG4412
Battery type 4 series 3 series 2 series PR4403 Id= -10A
4
100K_0402_5% Qg= -22nC 2 1
Rdson=15~18mohm
1
PAD-OPEN 4x4m
1
PR4407 309kohm 287kohm 287kohm
1
470K_0402_1% 1 2
PR4404 AD+_G_2 PR4405
3.3K_1206_5% Id= -10A @EMI@ PL4404
2
Qg= -22nC @ PR4406 1UH_6.6A_20%_5X5X3_M
PR4431 47kohm 47kohm 47kohm
2
0_0402_5%
Rdson=15~18mohm
2
PR4401 2 1
DC_IN_D
10K_0402_1%
PQ4402A L2N7002DW1T1G_SC88-6
6 1 PC4402
ACDET 18.178V 17.055V 17.055V
1
1 2
AD+_G_1
0.1U_0402_25V6
PT_1022
2
PWR_CHG_ACOK CHARGER_SRC
5
AD+
2
4 3
2200P_0402_25V7K
PC4404
10U_0805_25VAK
10U_0805_25VAK
2
PQ4402B 1U_0603_25V6K
0.1U_0402_25V6
4.7U_0805_25V6-K
0.1U_0603_50V7K
1
PWR_CHG_ACN
PC4403
PWR_CHG_ACP
PC4406
PC4426
EMI@ EC4401
EMI@ EC4402
2
1
SIS412DN-T1-GE3_POWERPAK8-5
L2N7002DW1T1G_SC88-6
PC4408
PC4409
1U_0603_25V6K
1
PR4408 PWR_CHG_REGN
2
5
10_0805_1% CHG_AGND
2PWR_CHG_BTST_R
2
PR4407 1 2 PWR_CHG_VCC @
0.47U_0603_25V7K
309K_0402_1% SD103AWS-V-GS08_SOD323-2
CHG_AGND
PD4401 PC4407
PC4010
1 2
PWR_CHG_BTST 1 2 2 1
PU4405
1
1
PU4401 @ PR4409 1U_0603_25V6K
2
PWR_CHG_IOUT 3D3V_AUX_S5 PWR_CHG_REGN 0_0603_5%
ACP
ACN
0.047U_0402_25V7K
20
CHG_AGND VCC
2
2
3D3V_AUX_KBC
PC4411
PT_1022
3
2
1
PR4411 @ PR4438 PR4430
ST_1201
1
102K_0402_1% 100K_0402_5% 100K_0402_5% PWR_CHG_ACDET 6 17
1
ACDET BTST
1
PR4431
47K_0402_1% PC4412 PWR_CHG_CMPOUT
BQ24737 Charger Current=1.4~3.6A
1
2 1
0.01U_0402_50V7K 16
2
REG
1
2
PR4415 PR4412 PR4432 PR4414 3

4.7K_0402_5% 120K_0402_5% 3.3M_0402_5% CMPOUT 18 PWR_CHG_HIDRV PR4416 BT+
4.7K_0402_5%
PR4413 HIDRV 1 2 0.01_1206_1%
169K_0402_1% 4 PL4401
2
C CMPIN 19 PWR_CHG_PHASE @ PC4413 3300P_0603_50V7K 1 2 BT+_R 1 4 C
2
PWR_CHG_CMPIN PHASE
0.1U_0603_50V7K
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
CHG_AGND @ PR4825 0_0402_5% 5.6UH +-20/ TMPC0603H-5R6MG-D 5A 2 3
CHG_AGND 2 1 9 15
PWR_CHG_BAT_SCL PWR_CHG_LODRV
PC4415
PC4416
PC4417
PC4418
[24,43] BAT_SCL SCL LODRV
PC4419
@ PR4826 0_0402_5%
3D3V_AUX_S5 2 1 PWR_CHG_BAT_SDA 8 EMI@ PR4425
[24,43] BAT_SDA
1
SDA PR4421 @ PC4420 @ @
4.7_0805_5%
PWR_CHG_SNUB
10_0402_5% 0.1U_0402_25V6
PU4406
1
1
13 PWR_CHG_SRP 1 2 4
PWR_CHG_ILIM 10 SRP
ILIM
1
PR4417 12 PWR_CHG_SRN 1 2
100K_0402_5% SRN PR4420
[24] BOOST_MODE# 2 1 11
PWR_CHG_IFAULT 7.5_0402_5%
2
3
2
1
BM#
CHG_AGND
@ PR4418 0_0402_5%
1
1
2
@ PR4423 3D3V_S5 @ PR4439 EMI@ PC4401
10K_0402_1% PR4435 5 7 PWR_CHG_IOUT 1 2 AD_IA [24] 680P_0603_50V8J
2
59K_0402_1% 3D3V_AUX_KBC ACOK# IOUT
100K_0402_5%
8.45K_0402_1%
GND
GND
3D3V_AUX_S5 @ PR4422
1
0_0402_5%
2
1
PT_1022
21
14
@ PR4472
100K_0402_5% @ PG4411
220P_0402_50V7K
CHG_AGND
2
1 2 PWR_CHG_CSOP_1
0.1U_0402_25V6
2
1 2
PC4422
1
PR4424
PC4421
BAT_IN# [24,43] JUMP_43X39
1
CHG_AGND
CHG_AGND
2
1
@ PC4433
CHECK EE 0.47U_0603_16V7K @ PWR_CHG_CSON_1
2
0.1U_0402_25V6
1
PC4423
PQ4406_G CHG_AGND
3D3V_AUX_S5
2
1
2
[4,24,46] H_PROCHOT# CHG_AGND

G
@ PR4474
1 2 PQ4406_D 1 3 100K_0402_5%
EE need pull high and net name
PR4434
D
@ PR4465 100K_0402_5% 3D3V_AUX_S5 PWR_CHG_REGN PR4440

0_0402_5% L2N7002WT1G_SC70-3
Customer Request Close PR4416 160K_0402_1%
2
1
@ PQ4414 @
AD+ PR4419 PR4428 2
PQ4008_5 1 PWR_CHG_CMPOUT
[24] AC_IN#
0.01U_0402_50V7K
100K_0402_1% 100K_0402_1%
PC4428
2
2
6
1
BT+_R
PWR_CHG_ACOK
1
BT+
4
@ PR4469 AC_IN# 2
15V_S5 100K_0402_5% 5
JUMP_43X39
JUMP_43X39
2
2
PG4404
PG4405
2
1
1
@
B PR4436 B
PQ4408A
2
120K_0402_1% PQ4008_3 2 1
PQ4408B 3
1
H_PROCHOT# [4,24,46]
1
@ PR4471 @ @
3 PQ4408_E
0_0402_5% @ PR4467 H_PROCHOT# [4,24,46] @ PR4426 0_0402_5%
1DCBATOUT_R1
1+VCHGR_R 1
2
1M_0402_1%
2
1
@ PR4466
2
@ 0_0402_5%
1N4148WS-7-F_SOD323-2 PQ4409
2PD4403_K
@ PD4404 MMBT3906H_SOT23-3
1
1 2 2 @ PQ4410A L2N7002DW1T1G_SC88-6
PQ4405_3 6 1 PR4448 PR4454
0_0402_5% 10_0402_1%
@ PR4468 @ PR4475 @ @
ST_1201
2
2
0_0402_5% 0_0402_5%
1
2
PQ4408_C 1 PQ4405_2 PQ4405_5 1 2
1
PU4401_5
5
1U_0603_25V6K
@ @ PR4410
1
6.8_0402_5% PWR_CHG_CMPIN
BATTERY MON
PC4434
@ PR4464 4 3 1 2
1
@ PR4476
2
DCBATOUT 3.3_0402_5% 0_0402_5% @ PQ4410B @ PR4446 @ PC4424 PR4429

PQ4405_6
1 2BOOST_MON_1 1 2PU4401_6 0.1U_0402_25V7K 309K_0402_1%

2
[24] BMON
1
L2N7002DW1T1G_SC88-6 PU4401_4
1
@ PR4452 20K_0402_5%
PC4427
1U_0603_25V6K
2
@ PR4470 0_0402_5%
PWR_CHG_CMPIN_R
PWR_CHG_ACOK 100K_0402_5%
2 EC code only BQ24707
1
4
2
Out
IN-
IN+
@ PR4473
100K_0402_5% X01_0808 H_PROCHOT# AD_IA_HW AD_IA_HW2
CHECK EE @ PU4407 PQ4401
2
INA199A1DCKR_SC70-6 L2N7002WT1G_SC70-3
GND
follow customer circuits.
REF
35W 0 0
V+
1 3
S
CHG_AGND
3D3V_S5
3
45W 1 0
G
2
DCBATOUT 65W 0 1
[24] AD_IA_HW2
1
PC4431
ST_1201
1U_0603_25V6K
AD_IA_HW [24]
2
G
@
3 1
D
L2N7002WT1G_SC70-3
PWR_CHG_CMPIN_RR
CHG_AGND PQ4407
A A
ST_1201
1
PR4427
78.7K_0402_1%
2
PWR_CHG_CMPIN

CHARGER BQ24770
A00
Date: Thursday, January 22, 2015 Sheet 44 of 102
5 4 3 2 1
A B C D E
Main Func = 3D3V_5V
PWR_5V_VCLK
1000P_0402_50V7K
3D3V_AUX_S5
1U_0603_25V6K
1U_0603_25V6K
1
PC4521
@ PC4514
@ PC4532
1
1
4 4
2
2
2
@
@ PR4501
BST15V_2
0_0402_5%
BST15V_1
BAT54SW-7-F_SOT323-3
BAT54SW-7-F_SOT323-3
1
1
1 2 PWR_5V_EN1_R 1 2 PWR_5V_EN1 @ PD4503 @ PD4502
@ PR4530 @ PR4504
2
0_0402_5% 0_0402_5%
@ PR4505
0_0402_5%
3
5V_PWR
15V_S5
1
1 2 PWR_3D3V_EN2 BOOST_10V 15V_PWR
[36] 3V_5V_EN
1U_0603_25V6K
0.1U_0603_50V7K
0.1U_0603_50V7K
@ PR4506
1
PC4515
PC4534
@ PC4533
0_0402_5%
@ PD4501
BZT52-B20S_SOD323-2
2
@ @
2
@ PG4525
1 2 DCBATOUT
PAD-OPEN 4x4m
DCBATOUT_3V5V
@EMI@ PL4503
DCBATOUT FBMJ4516HS720NT_2P
2 1
10U_0805_25VAK
0.1U_0603_50V7K
0.1U_0603_50V7K
4.7U_0805_25V6-K
1
PC4509
10U_0805_25VAK
EMI@ PC4525
PC4528
DCBATOUT_3V5V
1
PC4519
PC4531
2
3 @ 3
10U_0805_25VAK
0.1U_0603_50V7K
4.7U_0805_25V6-K
5
2
EMI@ PC4530
PC4529
PC4527
Design Current=3.3A
PU4504
12
4.95A<OCP>5.94A
1
PU4503
PU4501
PC4535 PR4528 4 @
VIN
0.1U_0603_50V7K 2.2_0603_5% Design Current=6.85A
2 1PWR_3D3V_VBST2_1 2 1PWR_3D3V_VBST2 PR4524 PC4516
10.275A<OCP>12.33A
1
2
3
2.2_0603_5% 0.1U_0603_50V7K
9 17 PWR_5V_VBST1 2 1 PWR_5V_VBST1_1 2 1
3
2
1
VBST2 VBST1
3D3V_PWR PL4502 PWR_3D3V_DRVH2 10 16 PWR_5V_DRVH1 PL4501 5V_PWR
3.3UH_6.3A_20%_7X7X3_M DRVH2 DRVH1 2.2UH_7.8A_20%_7X7X3_M
1 2 PWR_3D3V_LL2 8 18 PWR_5V_LL1 1 2
SW2 SW1
1
PWR_3D3V_DRVL2 11 15 PWR_5V_DRVL1
5
2
DRVL2 DRVL1
5
1 @EMI@ PR4533 1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7_0805_5% 14 PWR_5V_VO1 @EMI@ PR4529
SIS780DN-T1-GE3 1N
1
2
VO1
+ PT4502 + PT4501
PC4517
PWR_3D3V_SNUB
4.7_0805_5%
2
220U_6.3V_M PWR_3D3V_FB2 4 2 PWR_5V_FB1 220U_6.3V_M

PU4505
PC4518
1PWR_5V_SNUB 1
4 VFB2 VFB1
PU4502
2
1
2 4 2
@
PWR_3D3V_EN2 6 20 PWR_5V_EN1 @
EN2 EN1
3V_FEEDBACK
1
2
3
3
2
1
PWR_3D3V_CS2 5 1 PWR_5V_CS1
CS2 CS1
1
@EMI@ PC4536
1
2
@EMI@ PC4520 TPS51225CRUKR 560P_0603_50V7K
330P_0402_50V7K 19 PWR_5V_VCLK PR4531
2
2
PR4517 VCLK
115K_0402_1%
88.7K_0402_1%
7 21
2
1
PGOOD GND
VREG3
VREG5
1
@ PR4535
1
0_0402_5%
@ PR4525
3
13
1
2 3D3V_S5 5V_PWR_2 0_0402_5% 2

2
2
PR4512 3D3V_PWR_2
6.49K_0402_1% PR4527
2
1
PWR_3D3V_FB2_R PWR_5V_FB1_R 15.4K_0402_1%

2
2
2
@ PC4523 @ PR4534
1
1
18P_0402_50V8J 100K_0402_1% @ PC4522

1
PC4526 PC4524 18P_0402_50V8J

2
1
4.7U_0603_6.3V6K 1U_0603_10V6K
2
2
2
[17] 3V_5V_POK
1
PR4523
10K_0402_1% PR4526
9.76K_0402_1%
1
3D3V_PWR_2 3D3V_AUX_S5
2
2 1
@ PR4532
0_0402_5%
@ PG4526 @ PG4527
1 2 3D3V_S5 1 2
3D3V_PWR 5V_PWR 5V_S5
PAD-OPEN 4x4m PAD-OPEN 4x4m

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L
I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L @ PG4517 @ PG4519
1 2 1 2 Inductor: CHIP CHOKE 2.2U PCMC063T-2R2MN 18mohm/20mohm Isat =14Arms 68.2R210.20B
Inductor: CHIP IND 3.3UH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A O/P capCHIP CAP EL 220U 6.3V M6.3*4.4 /Chemi-con/ 18mOhm / 79.22710.3KL
O/P capCHIP CAP EL 220U 6.3V M6.3*4.4 /Chemi-con/ 18mOhm / 79.22710.3KL PAD-OPEN 4x4m PAD-OPEN 4x4m H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037 L/S:SIS780 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037
L/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
1 1

TPS51225_5V/3D3V
A00
A B C D E
5 4 3 2 1
Main Func = CPU_CORE

PT_1022
15W @ PR4614
90.9K_0402_1%
1 2 PW R_VCC_PRGM1
D PR4630 PR4607 D
130_0402_1% 124K_0402_1%
1D05S_VCCST 1 2 PW R_VCC_SDA 1 2 PW R_VCC_PRGM2
PR4620
54.9_0402_1%
1 2 PW R_VCC_SCLK 2 1 PW R_VCC_SDA
[7] H_CPU_SVIDDAT
@ PR4619
@ PR4601 0_0402_5%
75_0402_1%
1 2 PW R_VCC_ALERT# 2 1 PW R_VCC_ALERT#
[7] VR_SVID_ALERT#
@ PR4618
1
0_0402_5%
PC4606 2 1 PW R_VCC_SCLK
0.1U_0402_16V4Z [7] H_CPU_SVIDCLK
2
@ PR4616
0_0402_5%
5V_S0
20
19
18
11
17
PU4601
ALERT#
PRGM2
PRGM1
SCLK
SDA
2
PC4604
1U_0603_25V6K
1
12 13 PW R_VCC_BOOT PW R_VCC_BOOT [47]
C VCC BOOT C
@ PR4621 0_0402_5%
2 1 PW R_VCC_EN 1 14 PW R_VCC_UG PW R_VCC_UG [47]
[7] H_VR_ENABLE VR_ON UG
PT_1022 15W @ PR4610 95.3K_0402_1%

1 2 PW R_VCC_IMON 3 15 PW R_VCC_PHASE PW R_VCC_PHASE [47]
IMON PHASE
PC4609 1000P_0402_50V7K ISL95813HRZ-GP
1 2
PW R_VCC_VRHOT# 4 16 PW R_VCC_LG PW R_VCC_LG [47]
@ PR4602 499_0402_1% VRHOT# LG
1D05V_S0 1 2 PT_1022
@ PR4624 0_0402_5% LL=2mohm
[4,24,44] H_PROCHOT# 2 1 PW R_VCC_COMP 6 7 PW R_VCC_FB 2 1
COMP FB VCC_SENSE [7]
PR4613
PC4611 15W @ PR4603
2 1 PW R_VCC_COMP_RC 2 1 1.27K_0402_1%
6800P_0603_50V7K 2.67K_0402_1% 21
GND
PGOOD
@ PC4610 2 1 PW R_VCC_FB_RC 1 2 1 2
ISUMN
ISUMP
1 2
NTC
RTN
@ PR4606 @ PC4601 PC4613
0.1U_0402_16V4Z 0_0402_5% 0.1U_0402_16V4Z 1000P_0402_50V7K
R4622
10
2K_0402_1%
3D3V_S0 1 2
B @ PR4628 0_0402_5% B
[7,24] IMVP_PW RGD 2 1 PW R_VCC_POK PW R_VCC_ISUMP

PW R_VCC_ISUMP [47]
PR4615
ST_1201 PR4617 27.4K_0402_1% 8.45K_0402_1%
2 1 PW R_VCC_NTC_R 1 2 PW R_VCC_NTC
PW R_VCC_ISUMN
PW R_VCC_ISUMN [47]
PR4604
PR4622 ST_1211 10_0402_5%
2 1 1 2
VSS_SENSE [9]
470K_0402_5%_ TSM0B474J4702RE
B=4500K
close to H/S MOSFET 1 2
PC4612
PR4603 PR4610 PR4614
1000P_0402_50V7K
15W 1.27K 95.3K 90.9K

PR4603 28W @ PR4610 28W @ PR4614 28W @
PT_1023
28W 1.58K 100k 113K
A A
1.58K_0402_1% 100K_0402_5% 113K_0402_1%

ISL95813_CPUCORE(1/2)
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = CPU_CORE

DCBATOUT PW R_DCBATOUT_VCCCORE
PW R_DCBATOUT_VCCCORE DCBATOUT
@ PG4703 JUMP_43X118
EMI@ 1 2 1
PC4704 2 1
PC4701 PC4702 PC4703
+ PT4702
1
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
@
33U_25V_M
0.1U_0603_50V7K
1 2
2
2
[46] PW R_VCC_UG PU4701 @EMI@ PL4703
2
D FBMJ4516HS720NT_2P D
G1
D1
AON6970_DFN5X6D-8-7
PC4706
@ PR4701 0.22U_0603_25V7K
2 1 PW R_VCC_BOOT_RC 1 2 7
D2/S1
[46] PW R_VCC_BOOT
0_0603_5%
For acoustic noice
G2
S2
S2
S2
6
3
[46] PW R_VCC_LG
PL4701 VCC_CORE
0.22UH +-20% PCMB104T-R22MS 35A
PW R_VCC_PHASE 1 4
[46] PW R_VCC_PHASE Shark Bay ULT 15W CPU
2 3
IccMAX=32A
2
TDC=10A
@EMI@ PR4705
35.2A<OCP<41.6A
4.7_0805_5%
Frequency=750KHZ PT_1023
PHASE1G
1PWR_5V_SNUB 1
LL=-2.0 mV/A
ISUM_R_C
PR4709
1
C PR4702 PR4709 28W @ C
3.65K_0402_1%
@EMI@ PC4708 close to CHOKE

15W 340 o-hm
560P_0603_50V7K PR4703
2
PR4704
2
4.42K_0402_1% 432_0402_1%
1 2 PHASE_R_R 1 2
PC4710
28W 432 o-hm
10K_0402_1%_ERTJ0EG103FA
0.1U_0402_25V6
1
B=3370K
2
PR4707 PR4708
PT_1022 11K_0402_1%
20M_0402_5%
1 2 X01_0825
1
2
PR4705 (Cyntec choke) OCP
PC4707
0.047U_0402_25V7K
1 2 15W 340 ohm (64.34005.6DL) 38A
15W @ PR4709
PC4711
0.1U_0402_16V4Z 340_0402_1% 28W 412 ohm (64.41205.6DL) 48A
2 1 1 2 PW R_VCC_ISUMN [46]
PR4705 (Maglayers choke)
PC4709 @
PR4706
0.1U_0402_16V4Z 383 ohm (64.38305.6DL) 38A
0_0402_5% 15W
2 1 ISUM_R_R 2 1
B @ B
28W 464 ohm (64.46405.6DL) 48A
PW R_VCC_ISUMP [46]
22uF/6.3V/0805*13 VCC_CORE
VCC_CORE
330uF/2.5V/6.3*4.5/12mohm*1
EC4701
0.1U_0402_25V6
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
PC4723
PC4725
PC4726
PC4729
PC4730
PC4731
PC4732
PC4733
PC4734
PC4736
PC4741
PC4721
PC4722
PC4724
PC4727
PC4728
PC4735
PC4737
PC4739
PC4740
PC4742
2
1
@
@ @ @ @ @ @ @ @ @ @ @ @ @ @ @
A 1 A
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
PT4701 +
330U_2.5V_M
PC4717
PC4718
PC4719
PC4720
PC4744
2
@ @ @
Change to 79.3371V.6CL Issued Date 2015/01/20 Deciphered Date 2015/12/31 Title
ISL95813_CPUCORE(2/2)
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = 1D05V
D D
@ PG4838 JUMP_43X118
2 1
2 1
@EMI@ PL4802
FBMJ4516HS720NT_2P
1 2 DCBATOUT
10U_0805_25V6K
4.7U_0805_25V6-K
0.1U_0402_25V6
@
1
PC4826
PC4814
PC4825
EMI@
2
2
@ PR4821
PU4808
0_0402_5% 4
2 1
[7,36] 1D05V_VTT_PW RGD
Design Current =4.43A
3
2
1
1D05V_PW R 1D05V_S0
1 2 PU4806 PR4820 PC4822 6.645A<OCP<7.97A
PR4817 PW R_1D05V_PW RGD 1 11 2.2_0603_5% 0.1U_0603_50V7K
PW R_1D05V_TRIP 2 PGOOD GND 10 1
PW R_1D05V_BOOT 2 2
PW R_1D05V_BOOT_R 1 PL4801 1D05V_PW R @ PG4828
133K_0402_1% CS BOOT
(current limit ~ 7.7525A) PW R_1D05V_EN 3 9 PW R_1D05V_UGATE 2.2UH_7.8A_20%_7X7X3_M 1 2
@ PR4819 PW R_1D05V_FB 4 EN UGATE 8 PW R_1D05V_PHASE 1 2 1 2
0_0402_5% PW R_1D05V_CCM 5 FB PHASE 7 JUMP_43X118
RF VCC 5V_S5
2
2 1 6 PW R_1D05V_LGATE @ PG4829
1U_0402_16V6K
[17,24,36,49,51] PM_SLP_S3# LGATE 1 1
1
C
1 1 2 C
1 2
5
PC4815 @EMI@ PR4837 + PT4803
PC4824
1
PR4824 S IC RT8237EZQW (2) W DFN 10P 1U_0402_16V6K 4.7_0805_5% 330U_2.5V_M JUMP_43X118

2
@
PC4821 470K_0402_1%
PWR_1D05V_SNUB1
1000P_0402_50V7K 2 2
2
PU4805
4
3
2
1
1
@EMI@ PC4838
560P_0603_50V7K
18P_0402_50V8J
2
2
1
PR4822
PC4823
10K_0402_1%
2
1
@
PW R_1D05V_FB
I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L
Inductor: CHIP CHOKE 2.2U PCMC063T-2R2MN 18~20mohm Isat =14Arms 68.2R210.20B
O/P cap: CHIP CAP EL 330U 2.5V M6.3*4.4 3.5Arms Chemi-con/ 79.3371V.6CL Vout=0.704V*(R1+R2)/R2
H/S:SIS412DN-T1-GE3 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
2
B B
L/S:SIS412DN-T1-GE3 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037 PR4823
20K_0402_1%
1
A A

RT8237_1D05V
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = VDDQ
D D
@ PG4903 PAD-OPEN 4x4m

2 1
@EMI@ PL4903 DCBATOUT

FBMJ4516HS720NT_2P
5V_S5 2 1
10U_0805_25VAK
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.1U_0603_50V7K
2
2
EMI@ PC4913
3D3V_S0
PC4909
PC4911
PC4912
PC4914
PC4901
1U_0603_25V6K
1
1
PU4902
@ PR4904 4
20K_0402_1%
PR4605_2
PU4901
2
20 12
[36] 1D35V_VTT_PWRGD
3
2
1
@ PR4909 0_0402_5% PGOOD V5IN PR4905 PC4919
2 1DDR_VTT_PG_CTRL_R 17 2.2_0603_5% 0.1U_0603_50V7K Design Current=8.65A
[12] DDR_VTT_PG_CTRL S3 15 PWR_1D35V_VBST 1 2 2 1
VBST 12.98A<OCP>15.57A
2 1 PWR_1D35V_EN 16
[17,24,36,48,51] PM_SLP_S3# @ PR4910 0_0402_5% S5
PWR_1D35V_VREF 6 14 PWR_1D35V_DRVH
VREF DRVH
2
PL4902 1D35V_PWR
PR4903 .68UH_PCMC063T-R68MN_15.5A_20%
10K_0402_1% 13 PWR_1D35V_SW 1 2
SW
5
X01_0814-1PWR_1D35V_REFIN
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
0.1U_0603_50V7K
0.1U_0402_16V4Z
0.01U_0402_50V7K
4.7U_0603_6.3V6K
1
SIS780DN-T1-GE3 1N
PWR_1D35V_VDDQS
C 8 11 PWR_1D35V_DRVL C
PC4903 0.1U_0402_16V4Z
REFIN DRVL
2
10 @EMI@ PR4912
PC4920
PC4921
PC4923
PC4924
PC4925
PC4926
PC4927
PC4928
EC4601
31.6K_0402_1%
PGND
2
PWR_1D35V_MODE 19
PU4903
MODE 2.2_0805_1%
2
4
PR4901
1
1
PWR_1D35V_TRIP 18 9 PWR_1D35V_VDDQS @ @
1K_0402_1%
1
TRIP VDDQSNS
2
1
2 TPS51216_PHS_SET
PR4601_1
PC4902
1 PR4908
3
2
1
VLDOIN
2
PWR_1D35V_VTTREF 5 +0D675V_DDR_P
133K_0402_1%
VTTREF
1
2
0.1U_0402_25V6
3 @
0_0402_5%
VTT
2
10U_0603_6.3V6M
10U_0603_6.3V6M
PC4918 @EMI@ PC4217
PR4902
@ PR4906
1 1 1
PC4915
PC4916
PC4917
0.22U_0402_10V6K 1 330P_0402_50V7K
X01_0812
1
21 VTTSNS
1
GND 4 @ PG4908
2
VTTGND
2
7 2 2 1D35V_PWR 1 2 1D35V_S3
GND 1 2
TPS51716RUKR_QFN20_3X3 JUMP_43X118
1D35V_PWR @ PG4909
1 2
1 2
JUMP_43X118
1
DDR_VREF_S3 PC4904 @ PG4901
1U_0603_10V6K 2 1 PWR_1D35V_EN 2 1
+0D675V_DDR_P 0D675V_S0
2
[17,24] PM_SLP_S4# 2 1
PWR_1D35V_VTTREF 1 2 @ PR4907 JUMP_43X39
2
0_0402_5%
@ PR4911 @ PC4906
0_0603_5% 0.1U_0402_16V4Z
1
B B
State S3 S5 VDDR VTTREF VTT I/P cap: 10U 25V K0805 X5R/ 78.10622.51L
Component
Inductor:CHIP CHOKE 1.5U PCMC063T-1R5MN 14~15mohm Isat =18Arms 68.1R510.10K VRAM 4pcs VRAM 8pcs
S0 Hi Hi On On On
O/P cap:CHIP CAP C 22U 6.3V M0805 X5R / 78.22610.51L value (desugn current=8.65A) (desugn current=10.5A)
S3 Lo Hi On On Off(Hi-Z) H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037 133K 191K
S4/S5 Lo Lo Off Off Off L/S:SIS780 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037 PR4902 64.13335.6DL 64.19135.6DL OCP setting
PC4927 DY Stuff output MLCC
PC4928 DY Stuff output MLCC
A A

TPS51716_VDDQ_VTT
A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = 1D5V
D D
3D3V_S5
1U_0402_16V6K
1
PC5119
C C
Design Current = 20mA
2
1D5V_PWR @PG5105
@ PG5105 1D5V_S0
PU5101
1 5 1 2
VIN VOUT 1 2
2
GND JUMP_43X79
1U_0402_16V6K
[17,24,36,48,49] PM_SLP_S3# 2 1PWR_1D5V_EN 3 4 1
EN NC
PC5120
1U_0402_16V6K
@PR5110
@ PR5110 RT9198-15GBR SOT23 5P
0_0402_5% 1 2
PC5102
2
@
B B
A A

TLV70215_1D5V
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = LCD LCDVDD_LCD LCDVDD INVERTER POWER Main Func = CAM
R5211 @ R5214
1 2 DCBATOUT 1 2 DCBATOUT_LCD
LCD1 0R5J-5-GP 0R5J-5-GP
41 EE note: Never change R5211 to short pad after MP
F5201 800mA
1 1 2
2 LCDVDD_LCD R5213
DCBATOUT_LCD SMD1812P150TF/24 1.5A UL/CSA/TUV C5202
SC1KP50V2KX-1GP
3 DBC_EN_R 1 2 C5205
4 Trace width = 80mil DBC_EN <15,20> @ EE note: Never change R5229 to short pad after MP
C5201
5 C5206
Reserved for one time fuse: 69.43001.201
2
1
2
6 0R2J-2-GP SCD1U50V3KX-GP
7 SC1U10V2KX-1GP 3D3V_S0 3D3V_CAMERA_S0
8 DBC_EN_R 3D3V_S0
1
SCD1U16V2KX-3GP
9 EDP_HPD_CONN
10 R5229
LCD_TST_C
D 11 EDP_AUX 1 2 D
1
12 EDP_AUX#
13 For ESD R5208 0R3J-0-U-GP
1
14 EDP_TX0# @ 10KR2J-3-GP DMIC_CLK_EDP R5207 1 EMI@ 2 33R2J-2-GP @EMI@
DMIC_CLK <27>
15 EDP_TX0 DMIC_DATA_EDP R5215 1 EMI@ 2 33R2J-2-GP EC5210 C5207
DMIC_DATA <27>
16 SC4D7U6D3V3KX-GP
SC33P50V2JN-3GP
R5210
2
17 EDP_TX1# EC5205 EC5206
1
18 EDP_TX1 PANEL_SIZE_ID_CONN 1 @ESD@ 2 PANEL_SIZE_ID
19 PANEL_SIZE_ID <20>
@EMI@ @EMI@
20 LCD_BRIGHTNESS 100R2J-2-GP For AUDIO Grade B or C selection.
2
1
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
21 BLON_OUT_C
22 PANEL_SIZE_ID_CONN R5209
23 @ 0R2J-2-GP
24 Layout Note: Reduce the stubs.
25
2
26 Intel PDG (#514849):
MIC_GND
27 DMIC_CLK_EDP Recommends having a pull-up resistor of 100 kΩ for AUXN
28 DMIC_DATA_EDP
29 and a pull-down resistor of 100 kΩ for AUXP
30 USB_CAMERA_EDP# between the AC capacitor and the connector,
31 USB_CAMERA_EDP to assist source detection by the sink device.
32 EMI@
3D3V_CAMERA_S0
33 R5216 1 2 0R2J-2-GP
34 USB_PN6_TPNL EDP_AUX R5218 1 @ 2 100KR2J-1-GP
35 USB_PP6_TPNL
36 EDP_AUX# R5219 1 @ 2 100KR2J-1-GP TR5209
3D3V_S0
37 TP_RS USB_CAMERA_EDP# 1 2 USB_PN4 <16>
38 TP_RESET 1 2
39
40 USB_CAMERA_EDP 4 3 USB_PP4 <16>
TPAN_VDD 4 3
RN5203
42 1 8 BKLT_CTRL WCM-2012HS-900T_4P
2 7 BLON_OUT_C @EMI@
Layout Note: 3 6 EDP_HPD
4 5 R5217 1 2 0R2J-2-GP
ACES_51540-04001-P01_40P-T
Colse to LCD1. R5222 1 @ 2 0R2J-2-GP
CONN@ EMI@
@ SRN100KJ-5-GP
R5201 1 2 0_0402_1%
Short Pad D5202
RN5201 2 eDP_BKLT_CTRL
C LCD_TST_C 1 8 C
2 7 LCD_TST <24> 1
LCD_BRIGHTNESS BKLT_CTRL
BLON_OUT_C 3 6
4 5 BLON_OUT <24> 3
MIC_GND EDP_HPD_CONN
EDP_HPD <15> EC_BRIGHTNESS <24>
SRN100J-4-GP
BAT54C-7-F_SOT23-3
EC (BIST MODE)
<8> EDP_TX0_DN C5203 1 2 SCD1U16V2KX-3GP EDP_TX0#

3D3V_S0 5V_S0
Main Func = TS
C5210 1 2 SCD1U16V2KX-3GP EDP_TX0 TPAN_VDD
<8> EDP_TX0_DP
1
R5231
0R3J-0-U-GP
R5230
@ 0R3J-0-U-GP
C5211 1 2 SCD1U16V2KX-3GP EDP_TX1#
<8>
<8>
EDP_TX1_DN
EDP_TX1_DP C5213 1 2 SCD1U16V2KX-3GP EDP_TX1 Touch Panel
2
F5203 @
TPAN_VDD_F 1 2 R5205
C5209 1 2 SCD1U16V2KX-3GP EDP_AUX# TP_RS 1 2
<8> EDP_AUX_DN TOUCH_PANEL_INTR# <24>
C5212 1 2 SCD1U16V2KX-3GP EDP_AUX 1.1A_24V_SMD1812P110TF-24
<8> EDP_AUX_DP
1
R5232 2 1 0R3J-0-U-GP 33R2J-2-GP
@ C5208
Brightness @ SC10P50V2JN-4GP
2
R5206 1 2 0_0402_1% eDP_BKLT_CTRL EE note: Never change R5232 to short pad after MP
<15> L_BKLT_CTRL
Short Pad Reserved for one time fuse: 69.43001.201
R5212
TP_RESET 1 @ 2
PLT_RST# <17,24,30,36,58,65,73,96>
LCDVDD
1
@ C5214 0R2J-2-GP
SC10P50V2JN-4GP
2
D5201
2
<15> EDP_VDD_EN
1 LCDVDD_EN EMI@
USB_PN6_TPNL 1 R5203 2 USB_PN6 <16>
B 3 B
<24> LCD_TST_EN
2
3D3V_S0 0R2J-2-GP
R5202 TR5201
BAT54C-7-F_SOT23-3 100KR2J-1-GP 1 2
U5201 1 2
LCDVDD
1
1 5 4 3
2 EN VIN#5 4 3
3 GND 4 WCM-2012HS-900T_4P
VOUT VIN#4 @EMI@
1
C5204
RT9724GB-GP SC4D7U6D3V3KX-GP USB_PP6_TPNL 1 R5204 2 USB_PP6 <16>
2
Layout Note: 0R2J-2-GP

Trace width = 80mil EMI@
A A

LCD/Inverter CONN
A00
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
A A

(Reserved)
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = HDMI HDMI@EMI@

R5401
HDMI@EMI@
R5403
HDMI_CLK#_R 1 2 8.2_0402_1% HDMI_CLK#_R_C HDMI_DATA0#_R 1 2 8.2_0402_1% HDMI_DATA0#_R_C
@EMI@ @EMI@
W CM-2012HS-900T_4P W CM-2012HS-900T_4P
1
C5402 1 2
HDMI SCD1U16V2KX-3GP HDMI_CLK#_R 3 4 HDMI@EMI@ 3 4 HDMI@EMI@
<8> HDMI_CLK# C5403 1 2 SCD1U16V2KX-3GP HDMI_CLK_R 3 4 R5414 3 4 R5416
<8> HDMI_CLK HDMI
150R2J-L1-GP-U 150R2J-L1-GP-U
C5404 1 2
HDMI SCD1U16V2KX-3GP HDMI_DATA0#_R 2 1 2 1
<8> HDMI_DATA0# C5405 1 2 SCD1U16V2KX-3GP HDMI_DATA0_R 2 1 2 1
HDMI
2
<8> HDMI_DATA0 TR5401 TR5402
D D
HDMI_DATA1# C5409 1 2
HDMI SCD1U16V2KX-3GP HDMI_DATA1#_R
R5402 R5404
HDMI_DATA1 C5406 1 2
HDMI SCD1U16V2KX-3GP HDMI_DATA1_R
HDMI_CLK_R 1
HDMI@EMI@ 2 8.2_0402_1% HDMI_CLK_R_C HDMI_DATA0_R 1
HDMI@EMI@ 2 8.2_0402_1% HDMI_DATA0_R_C
HDMI_DATA2# C5407 1 2
HDMI SCD1U16V2KX-3GP HDMI_DATA2#_R
HDMI_DATA2 C5408 1 2
HDMI SCD1U16V2KX-3GP HDMI_DATA2_R
R5405 R5407
HDMI_DATA2#_R 1
HDMI@EMI@ 2 8.2_0402_1% HDMI_DATA2#_R_C HDMI_DATA1#_R 1
HDMI@EMI@ 2 8.2_0402_1% HDMI_DATA1#_R_C
8
7
6
5
8
7
6
5
RN5402 RN5403
SRN470J-3-GP SRN470J-3-GP
HDMI@ HDMI@ @EMI@ @EMI@
W CM-2012HS-900T_4P W CM-2012HS-900T_4P
1
3 4 HDMI@EMI@ 3 4 HDMI@EMI@
1
2
3
4
1
2
3
4
HDMI_PLL_GND 3 4 R5415 3 4 R5417
150R2J-L1-GP-U 150R2J-L1-GP-U
2 1 2 1
2 1 2 1
2
R5418 TR5403 TR5404
1
5V_S0 @ 0R2J-2-GP
D Q5403
2 2N7002K_SOT23-3
1
G HDMI@
R5406 R5408
S
C HDMI_DATA2_R 1 2 8.2_0402_1% HDMI_DATA2_R_C HDMI_DATA1_R 1 2 8.2_0402_1% HDMI_DATA1_R_C C
3
R5413
HDMI@EMI@ HDMI@EMI@
1 2
100KR2J-1-GP
@
5V_HDMI_CRT_S0_R
RE39 2 HDMI@ 1 0_0402_5% HDMI_DATA1#
<55,8> HDMI_CRT_N1 RE40 2 HDMI@ 1 0_0402_5% HDMI_DATA1
<55,8> HDMI_CRT_P1
HDMI CONN
1
C5401
HDMI@
SCD1U16V2KX-3GP
RE41 2 HDMI@ 1 0_0402_5% HDMI_DATA2#
2
<55,8> HDMI_CRT_N0 RE42 2 HDMI@ 1 0_0402_5% HDMI_DATA2
<55,8> HDMI_CRT_P0
JHDMI
HPD_HDMI_CON 19
18 HP_DET
17 +5V
DDC_DATA_HDMI 16 DDC/CEC_GND
DDC_CLK_HDMI 15 SDA
5V_S0 14 SCL
13 Reserved
B HDMI_CLK#_R_C 12 CEC B
CK-
1
11 23
D5401 HDMI_CLK_R_C 10 CK_shield GND3 22
BAW 56W _SOT323-3 HDMI_DATA0#_R_C 9 CK+ GND2 21
HDMI@ 8 D0- GND1 20
HDMI_DATA0_R_C 7 D0_shield GND0
HDMI_DATA1#_R_C 6 D0+
DDC_CLK_PH1 3
DDC_DATA_PH2 2
5 D1-
HDMI_DATA1_R_C 4 D1_shield
HDMI_DATA2#_R_C 3 D1+
2 D2-
HDMI_DATA2_R_C 1 D2_shield
D2+
3D3V_S0 C-K_96067-3K28-192-124
CONN@
2
2
3D3V_S0 HDMI@ R5411
1
RE43 RE44 Q5401 C 150KR2F-L-GP
2.2K_0402_5%
2.2K_0402_5% LMBT3904LT1G-GP 2 HDMI_HPD_B 2 1
B HDMI
1
E
Q5402 R5419
1
1
3
DY R5410
4 3 DDC_CLK_HDMI <15,55> HDMI_CRT_DET 1 HDMI 2 HDMI_HPD_E 200KR2F-L-GP
<15> PCH_HDMI_CLK
1
5 2
2
0R2J-2-GP R5412
HDMI HDMI
6 1 10KR2J-3-GP
A A
2
2N7002KDW -GP
<15> PCH_HDMI_DATA
DDC_DATA_HDMI
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F Issued Date 2015/01/20 Deciphered Date 2015/12/31 Title
HDMI L.Shifter/Conn
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
5V_HDMI_CRT_S0 5V_S0
CRT_R 1
1 AFTP5501 AFTE14P-GP
CRT_G
CRT_B
5V_HDMI_CRT_S0_R For DIODE in case of leakage from HDMI1
CRT_DDCDATA_CON
5V_HDMI_CRT_S0_R 1 AFTP5505 AFTE14P-GP
CRT_DDCCLK_CON
CRT_VSYNC_CON 1 AFTP5506 AFTE14P-GP R5409
HDMI@
1 AFTP5507 AFTE14P-GP 2 1
CRT_HSYNC_CON
AFTP5508 AFTE14P-GP
JCRT 0R3J-0-U-GP
D 6 D
AFTE14P-GP 1 CRT_NC 11 5V_HDMI_CRT_S0_R
AFTP5509 CRT_R 1
7 G 16 F5501 D5501
CRT_DDCDATA_CON 12 17 1 2 1 2
2 G 18
CRT_G G
8 G 19 RB551V-30_SOD323-2
CRT_HSYNC_CON 13 1.1A_6V_SPR-P110 CRT@
CRT_B 3
9
CRT_VSYNC_CON 14
4
10
CRT_DDCCLK_CON 15
5
1
C5519
SCD01U16V2KX-3GP
@ C-K_80461-5K1-152
CONN@
2
CRT RGB
CRT_DDCDATA_CON CRT H/VSYNC
CRT_HSYNC_CON
CRT_VSYNC_CON CRT SMBUS
C5513
SC18P50V2JN-1-GP
CRT_DDCCLK_CON
C5516
SC100P50V2JN-3GP
C5507
SC18P50V2JN-1-GP
1
1
C5511
SC100P50V2JN-3GP
2
L5503
CRT@ @ @ @
DP_CRT_R 1 2 CHILISIN NBQ160808T-800Y-N 0603CRT_R @
CRT@ L5501
DP_CRT_G 1 2 CHILISIN NBQ160808T-800Y-N 0603CRT_G
C C
CRT@ L5502
DP_CRT_B 1 2 CHILISIN NBQ160808T-800Y-N 0603CRT_B
1 R5501
1 R5513
1 R5514
5V_HDMI_CRT_S0
CRT@
C5506
10P_0402_50V
CRT@
C5512
10P_0402_50V
CRT@
C5509
10P_0402_50V
CRT@
C5514
10P_0402_50V
CRT@
C5510
10P_0402_50V
CRT@
C5518
10P_0402_50V
CRT@
1
1
DP_CRT_HSYNC_CON R5511 1 2 33R2J-2-GP CRT_HSYNC_CON
DP_CRT_VSYNC_CON R5507 1 2 33R2J-2-GP CRT_VSYNC_CON

CRT@
CRT@
CRT@
CRT@
2
2
75_0402_1% 2
75_0402_1% 2
75_0402_1% 2
RE45 RE46
2.2K_0402_5%
2.2K_0402_5%
1
1
CRT_DDCDATA_CON
CRT_DDCCLK_CON
Layout note: U5502

All cap need close to chip 2 1 CRT@ AVCC33 24 1 CRT_PCH_HPD CRT_PCH_HPD R5517 1 2 0R2J-2-GP
AVCC_33 HPD HDMI_CRT_DET <15,54>
3D3V_S0 AVCC33 2 1 CRT@ VCCK_12 25 2 CRT@
AVCC_12 SMB_SCL PCH_SMBCLK <12,13,18,62,96>
1
SCD1U16V2KX-3GP C5503 3
2 1 CRT@ 3D3V_S0 5 SMB_SDA PCH_SMBDATA <12,13,18,62,96>
R5510
R5504 SCD1U16V2KX-3GP2 1C5520 3D3V_S0 20 DVCC_33 4
DVCC_33 VGA_SCL CRT_DDCCLK_CON 100KR2J-1-GP
1 @ 2 0_0603_1% SCD1U16V2KX-3GP C5522 CRT@ 6 CRT@
2 1 VCCK_12 19 VGA_SDA CRT_DDCDATA_CON
2
CRT@ SCD1U16V2KX-3GP2 1C5501 VCCK_12
Short Pad
2
C5523 2
SC2D2U10V3KX-1GP 1C5504 VDD_DAC_33 9 7 DP_CRT_VSYNC_CON
CRT@ VDD_DAC_33 VSYNC
SC10U6D3V3MX-GP SCD1U16V2KX-3GP2 CRT@
1C5524 8 DP_CRT_HSYNC_CON
SC10U6D3V3MX-GP CRT@ C5502 HSYNC
1
LDO_EN 21 15 DP_CRT_R
CRT@ LDO_EN RED_P 16
B C5527 1 2 CRT@ SCD1U16V2KX-3GP PCH_DPC_AUXP_U 26 RED_N B
<15> PCH_DPB_AUXP AUX_P
C5528 1 2 CRT@ SCD1U16V2KX-3GP PCH_DPC_AUXN_U 27 12 DP_CRT_G
<15> PCH_DPB_AUXN AUX_N GREEN_P 13
C5529 1 2 CRT@ SCD1U16V2KX-3GP PCH_DPC_P0_U 29 GREEN_N
3D3V_S0 VDD_DAC_33 <54,8> HDMI_CRT_P0 LANE0P
<54,8> HDMI_CRT_N0 C5526 1 2 CRT@ SCD1U16V2KX-3GP PCH_DPC_N0_U 30 10 DP_CRT_B
LANE0N BLUE_P 11
C5530 1 2 CRT@ SCD1U16V2KX-3GP PCH_DPC_P1_U 31 BLUE_N
<54,8> HDMI_CRT_P1 LANE1P
R5503 <54,8> HDMI_CRT_N1 C5525 1 2 CRT@ SCD1U16V2KX-3GP PCH_DPC_N1_U 32 22 POL1_SDA
1 @ 2 0_0603_1% LANE1N POL1_SDA 23 POL2_SCL
POL2_SCL
CRT@ CLK_DP2VGA 17
Short Pad <18> CLK_DP2VGA XI/CKIN
2
C5521 18 14
SC10U6D3V3MX-GP XO GND_DAC
RRX 28 33
1
RRX GND
RTD2168-CGT-GP
CRT@
1
R5505
12KR2F-L-GP
CRT@
2
3D3V_S0
U5504
1 8
2 A0 VCC 7
3 A1 WP 6 POL2_SCL
4 A2 SCL 5 POL1_SDA
3D3V_S0 3D3V_S0 3D3V_S0 VSS SDA
2
CAT24C128WI-GT3-GP
R5509 R5515 R5502
4K7R2J-2-GP 4K7R2J-2-GP CRT@ 4K7R2J-2-GP CRT@ @
@
1
A POL1_SDA POL2_SCL LDO_EN A

2
R5508 R5516 R5512

4K7R2J-2-GP 4K7R2J-2-GP @ 4K7R2J-2-GP @
CRT@
1

DP to VGA Converter
A00
5 4 3 2 1
Main Func = HDD
SATA HDD Connector
5V_S0 5V_HDD_S0 @ 5V_HDD_S0 1
<20> HDD_DEVSLP HDD_DEVSLP R5605 1 2 0_0402_1% HDD_DEVSLP_R AFTP5601 AFTE14P-GP
80 mils Short Pad
1 2
Short Pad
R5601 @ 0_0805_1% Reserve, refer to M15 EE Implementation Requirements HDD1
14
1
1
C5601 C5604 C5605 C5606 12
@ @ @ <19> SATA3_PTX_HDDRX_P0 SCD01U50V2KX-1GP 2 1 C5602 SATA_TXP0_R 11
SC10U10V5KX-2GP
SCD1U16V2KX-3GP
SC10U10V5KX-2GP
SCD1U16V2KX-3GP
<19> SATA3_PTX_HDDRX_N0 SCD01U50V2KX-1GP 2 1 C5603 SATA_TXN0_R 10
2
2
9
SCD01U50V2KX-1GP 1 2 C5616 SATA_RXN0_R 8
<19> SATA3_PRX_HDDTX_N0 SCD01U50V2KX-1GP 1 2 C5615 SATA_RXP0_R 7
<19> SATA3_PRX_HDDTX_P0 6
HDD_DEVSLP_R 5
4
5V_HDD_S0 3
2 HDD2
Layout Note: 12
1 11 GND
Close to HDD1 Place near HDD1 13 GND
EU5602
Layout Note:
ACES_51625-01201-001_12P-T
SATA_TXP0_R 1 1 10 9 SATA_TXP0_R Place close to HDD1 CONN@
SATA_TXN0_R 2 2 9 8 SATA_TXN0_R
SATA_RXP0_R CLRP3 1 @ 2 SHORT PADS SATA_PRX_DTX_P0 10
4 4 10
SATA_RXN0_R 7 7 SATA_RXN0_R SATA_RXN0_R CLRP4 1 @ 2 SHORT PADS SATA_PRX_DTX_N0 9
8 9
5 5 8
SATA_RXP0_R 6 6 SATA_RXP0_R SATA_TXN0_R CLRP1 1 @ 2 SHORT PADS SATA_PTX_DRX_N0 7
SATA_TXP0_R CLRP2 1 @ 2 SHORT PADS SATA_PTX_DRX_P0 6 7
3 3 5 6
HDD_DEVSLP R5608 1 @ 2 0_0402_5% JHDD_P10 4 5
8 3 4
2 3
1 2
5V_HDD_S0 1
@ESD@
ACES_50208-01001-001
Swap based on the swap report. CONN@
Main Func = ODD

SATA Zero Power ODD
3D3V_S0
R5607 2.5A
1 2 SATA_ODD_PW RGT X01_0729
ODD Connector 5V_S0
ZPODD@
100KR2J-1-GP
U5601
2
3 IN#2 OUT#6
6
7
ODD_PW R_5V
ODD_PW R_5V
100 mil 5V_S0

ODD
ODD_PW R_5V
IN#3 OUT#7 8
OUT#8 R5603
C5609 4 C5610 ZPODD@ 1 2
EN/EN#
1
<20> SATA_ODD_PW RGT 1
@ 5 GND 9 0R5J-5-GP
SC10U10V5KX-2GP FLT# GND SC10U10V5KX-2GP
2
ODD@
ODD_PW R_5V ZPODD@
ODD1 Current limit TPS2001CDGNR-GP
22 20
GND2 20 19 Active High
19 18 ZPODD@ 2nd = 74.02311.079
74.02001.079 is OBS
18 17 SATA_ODD_DA#_C 1 R5602 2 0R2J-2-GP typ =>2.5A
17 16
SATA_ODD_DA# <20> Will use 74.06288.079
16 15
15 14 but 74.06288.079 is also OBS
14 13
13 12 we will use 074.06288.0079.
12 11
11 10
10 9
9 8 SATA_ODD_PRSNT#
8 SATA_ODD_PRSNT# <19>
7
7 6 SATA_RXP2_R C5608 1
ODD@ 2 SCD01U50V2KX-1GP
6 SATA_PRX_ODDTX_P1 <19>
1
5 SATA_RXN2_R C5607 1 2 SCD01U50V2KX-1GP SATA_PRX_ODDTX_N1 <19>

5 4 ODD@ R5604
4 3 SATA_TXN2_R C5611 1
ODD@ 2 SCD01U50V2KX-1GP @ 10KR2J-3-GP
3 SATA_PTX_ODDRX_N1 <19>
2 SATA_TXP2_R C5612 1 2 SCD01U50V2KX-1GP SATA_PTX_ODDRX_P1 <19>
2 1 ODD@
2
21 1
GND1
ACES_51519-02001-001
CONN@

HDD/ODD
A00
LA-B483P
5 4 3 2 1
SSID = ESATA
D D
C C
(Blanking)
B B
A A

eSATA
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = WLAN
3D3V_S0 R5801
3D3V_W LAN_S0 EMI@ 0R2J-2-GP
D USB_PN5_R 1 2 D
USB_PN5 <16>
1.1A Short Pad

1 2 TR5801
R5809 @ 0_0805_1% 4 3
4 3
C5801
SCD1U16V2KX-3GP
C5805
C5802
SCD1U16V2KX-3GP
C5806
C5804
SCD1U16V2KX-3GP
C5803
SCD1U16V2KX-3GP
1
1
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
1 2
@ @ @ 1 2
W CM-2012HS-900T_4P
2
2
@EMI@
R5802
W LAN1 EMI@ 0R2J-2-GP
USB_PP5_R 1 2
USB_PP5 <16>
68 69
MTG76 MTG77
3D3V_W LAN_S0
67
66 GND 65
64 3.3VAUX RESERVED 63
62 3.3VAUX RESERVED 61
60 RESERVED GND 59
58 RESERVED RSRVD/PERN1 57
56 RESERVED RSRVD/PERP1 55
54 RESERVED GND 53
52 ALERT RSRVD/PETN1 51
TP5803 1 TPAD14-OP-GP E51_RX2 50 I2C_CLK RSRVD/PETP1 49
I2C_DATA GND TPAD14-OP-GP
C
<24> W IFI_RF_EN R5805 1 @ 2 0_0402_1% W LAN_DISABLE#1 48 47 W LAN_W AKE 1 TP5801 @ C
R5804 1 @ 2 0_0402_1% BLUETOOTH_EN_NGFF 46 W_DISABLE1# PEWAKE0# 45 CLK_PCIE_W LAN_REQ# R5803 1 2 0_0402_1%
<20> BLUETOOTH_EN W_DISABLE2# CLKEQ0# CLK_PCIE_W LAN_REQ3# <18,20>
R5807 1 @ 2 0_0402_1% PLT_RST_NGFF# 44 43 Short Pad
<17,24,30,36,52,65,73,96> PLT_RST# PERST0# GND
42 41 CLK_PCIE_W LAN_N3 <18>
40 SUSCLK REFCLKN0 39
COEX1 REFCLKP0 CLK_PCIE_W LAN_P3 <18>
TP5802 1 TPAD14-OP-GP E51_RX1 38 37
E51_TX1 36 COEX2 GND 35 PCIE_PRX_W LANTX_N3_R R5808 1 @ 2 0_0402_1%
COEX3 PERN0 PCIE_PRX_W LANTX_N3 <16>
34 33 PCIE_PRX_W LANTX_P3_R R5811 1 @ 2 0_0402_1%
RESERVED PERP0 PCIE_PRX_W LANTX_P3 <16>
32 31
TP5804 1 TPAD14-OP-GP E51_TX2 30 RESERVED GND 29
RESERVED PETN0 PCIE_PTX_W LANRX_N3_C <16> EMI request
28 27 PCIE_PTX_W LANRX_P3_C <16>
26 UART_RTS PETP0 25
24 UART_CTS GND
CLK_PCIE_WLAN_N3
CLK_PCIE_WLAN_P3
UART_TX
23
22 SDIO_RESET# 21
20 UART_RX SDIO_WAKE# 19
Reserved for NGFF Debug Card 18
16
UART_WAKE#
GND
SDO_DAT3
SDO_DAT2
17
15
14 LED2# SDO_DAT1 13
3D3V_S5 3D3V_W LAN_S0 12 PCM_OUT SDO_DAT0 11
PCM_IN SDIO_CMD
EC5801
SC33P50V2JN-3GP
EC5802
SC33P50V2JN-3GP
10 9
PCM_SYNC SIDO_CLK
1
@EMI@
@EMI@
R5810 3D3V_W LAN_S0 8 7
1 @ 2 6 PCM_CLK GND 5 USB_PN5_R
0R2J-2-GP 4 LED1# USB_D- 3 USB_PP5_R
2
R5806 2 3.3VAUX USB_D+ 1
1 2 E51_TX1 3.3VAUX GND
B <24> E51_TXD B
@ 0R2J-2-GP DAN05-67406-0100
R5812 CONN@
1 2 E51_TX2
@ 0R2J-2-GP
AFTE14P-GP AFTP5801 1 3D3V_W LAN_S0

1 CLK_PCIE_W LAN_REQ#
Support: Intel Dual Band Wireless-AC 3160
AFTE14P-GP AFTP5802
AFTP5803 1 W LAN_DISABLE#1
AFTE14P-GP 1 BLUETOOTH_EN_NGFF
AFTE14P-GP AFTP5804
AFTP5805 1 PLT_RST_NGFF#
AFTE14P-GP
A A

NGFF_WLAN CONN
A00
LA-B483P
5 4 3 2 1
A B C D E
4 4
3
(Blanking) 3
2 2
1 1

Reserved
A00
LA-B483P
A B C D E
5 4 3 2 1
D D
C C
(Blanking)
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = Power BTN

Power button
PW R2
1
4 6
G6102 G6101 LID_CLOSE#_C 3 4 GND 5
KBC_PW RBTN#_C 2 3 GND
GAP-OPEN GAP-OPEN 2
3D3V_S5 1
1
2
JXT_FP202DH-004M10M
D PW R1 CONN@ D
R6109 100R2J-2-GP 4 6
1 2 LID_CLOSE#_C 3 4 GND 5
<24> LID_CLOSE# 1 2 KBC_PW RBTN#_C 2 3 GND
<24> KBC_PW RBTN# R6102 100R2J-2-GP 1 2
3D3V_S5 1
1
ED6101 JXT_FP202DH-004M10M 3D3V_S5 1 AFTP6103
1
AFTP6101 1 CONN@
@EMI@ EC6101 AZ5725-01F_DFN2 LID_CLOSE#_C 1 AFTP6104
@ESD@
SC1KP50V2KX-1GP
2
2
For EMI Reserved
LID_CLOSE#_C EC6105 1 2 SCD1U16V2KX-3GP
EC6101 must be used 1000pF. EMI@
Main Func = Battery LED

C C
Low actived from KBC GPIO Q6101

5V_S5
Battery LED1(AMBER_LED)
R2
R6105 3 LED1
<24> CHG_AMBER_LED# 1 @ 2CHG_AMBER_LED_R# 2 R6103 470R2J-2-GP
R1
Short Pad 0_0402_1% 1 AMBER_LED_BAT 2 1 BAT_AMBER 1
R6107 2 1 390R2J-3-GP BAT_W HITE 3

DDTA144VCA-7-F-GP
2
1
@EMI@ @EMI@
EC6102 EC6103
SC220P50V2KX-3GP SC220P50V2KX-3GP 12-22A/Y2T7D-C30/2C YELLOW /W HITE
2
Low actived from KBC GPIO Q6102
5V_S5
Battery LED2 (WHITE_LED)
R2
R6104 3
<24> BATT_W HITE_LED# 1 @ 2BATT_W HITE_LED_R# 2
R1
Short Pad 0_0402_1% 1 W HITE_LED_BAT
DDTA144VCA-7-F-GP
B B
Main Func = HDD LED <24> SATA_LED#_R

@
For EMI Reserved
2
G
SATA_LED EC6104 1 2 SCD1U16V2KX-3GP
3D3V_S0 3 1 BATT_W HITE_LED_R#
<19,24,61> SATA_LED#
D
@EMI@
Q6105
Q6103 5V_S0 3D3V_S0 2N7002K_SOT23-3
2
@ 2N7002K_SOT23-3
Q6104 R6110
G
LED@ HDLED1
R2
3 1 2 SATA_LED#_R
3
<19,24,61> SATA_LED# 3 1 SATA_LED#_B 2 R6108 @

R1
1 SATA_LED 1 2 SATA_LED_R 2 1
S
LED@ 10KR2J-3-GP
A A
LED@ LED-W -27-GP-U
DDTA144VCA-7-F-GP 330R2J-3-GP
R6106
2nd = 83.00110.R70
1 2 3rd = 083.11204.0070
LED@
0R2J-2-GP Security Classification Compal Secret Data Compal Electronics, Inc.
SATA HDD LED Issued Date 2015/01/20 Deciphered Date 2015/12/31 Title
LOW actived from PCH GPIO THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LED Bard/Power Button
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = KB Main Func = TPAD 3D3V_S0 3D3V_S5

TP_VDD
1
@ TP_WAKE@
R6217 R6215 TP_VDD Discharge Circuit
0R2J-2-GP 0R2J-2-GP
1
TP_ON#_GATE
Internal Keyboard Connector (DVC40) R6213 @ R6211
2
1 2 100R3J-4-GP
2
0R3J-0-U-GP 3D3V_S0 TP_VDD TP_WAKE@
2
AFTP6202 1 NOTP_WAKE@
KB1 R6212 1 2 3 1 Q6205_Q
30 32 Q6203
D
0R3J-0-U-GP
<15,20> KB_DET# AFTP6221 1 KROW7 29 30 GND 31 NTK3139PT1G_SOT723-3
AFTP6222 1 KROW6 28 29 GND TP_WAKE@
1 27 28 3 1 Q2405
D
AFTP6230 KROW4
AFTP6218 1 KROW2 26 27 2N7002K_SOT23-3
AFTP6214 1 KROW5 25 26
AFTP6227 1 KROW1 24 25 TP_WAKE@ TP_WAKE@
G
D D
2
24
1
AFTP6234 1 KROW3 23 SCD1U16V2KX-3GP
<24> KROW[0..7] 23
AFTP6228 1 KROW0 22 C6204
AFTP6215 1 KCOL5 21 22
2
AFTP6224 1 KCOL4 20 21 1 2 TP_ON#_GATE
<24> KCOL[0..16] 20 <24> TP_ON#
AFTP6213 1 KCOL7 19
AFTP6223 1 KCOL6 18 19
18
R6214 Touch Pad Connector
AFTP6231 1 KCOL8 17 20KR2F-L-GP
AFTP6208 1 KCOL3 16 17
16 TP_WAKE@ TP_VDD
AFTP6206 1 KCOL1 15
1 KCOL2 14 15
AFTP6226
14 TP_VDD
Pin number Pin name
AFTP6207 1 KCOL0 13
1 KCOL12 12 13 C6201
AFTP6233
12 1 VDD
AFTP6225 1 KCOL16 11 2 1
1 KCOL15 10 11
AFTP6229
10 2 DAT(I2C)
AFTP6203 1 KCOL13 9 @ SCD1U16V2KX-3GP
1 KCOL14 8 9 2 1
AFTP6216 TPAD1 3 CLK(I2C)
2
2
AFTP6219 1 KCOL9 7 8 1
1 KCOL11 6 7 I2C1_SDA_R 2 1
AFTP6220
6
RE48 RE47 R6209
2
4 GND
AFTP6232 1 KCOL10 5 10K_0402_5% 10K_0402_5% 4K7R2J-2-GP I2C1_SCL_R 3
1 CAP_LED 4 5 4 3
AFTP6243
4 4 5 ATTN
3 5
1
1
2 3 <20,24> INT_TP# 6 5
2 <24> TP_LOCK# 6 6 GPIO
1 TPDATA_C 7
1 TPCLK_C 8 7
8 7 DAT(PS2)
ACES_51510-0304N-P01 9
RE50 2 33_0402_5%
1 TPCLK_C 10 GND
CONN@ 8 CLK(PS2)
PS2 <24> TPCLK
<24> TPDATA RE49 2 33_0402_5%
1 TPDATA_C GND
JXT_FP202DH-008M10M
CONN@
I2C <20> I2C1_SCL @ RE51 2 33_0402_5%
1 I2C1_SCL_R
<20> I2C1_SDA @ RE52 2 33_0402_5%
1 I2C1_SDA_R 1
AFTP6235
CAP LED Control Q6201

5V_S0
EC6202
SC33P50V2JN-3GP
EC6203
SC33P50V2JN-3GP
EC6204
SC33P50V2JN-3GP
LOW actived from KBC GPIOR6202
1
R2
3 @EMI@
1 @ 2 CAP_LED_R# 2 R6201 EC6201
<24> CAP_LED# 0_0402_1%
R1
1 CAP_LED_Q 1 2 CAP_LED SC33P50V2JN-3GP
Short Pad
2
DDTA144VCA-7-F-GP
1KR2J-1-GP @EMI@ @EMI@ @EMI@ RN6203 and PTP schematic are BOM option for verify I2C leakage issue.
C C
5V_S0
@ TP_VDD
0R2J-2-GP 1 2 R6204 I2C1_SCL_R Short Pad
1
<12,13,18,55,96> PCH_SMBCLK
0R2J-2-GP 1 2 R6210 I2C1_SDA_R @ Need to check if it is Active High or Active Low
SMBUS <12,13,18,55,96> PCH_SMBDATA
@
0_0402_1% and check if there is PH on TPAD side.
@EMI@ @EMI@ R6216
Keyboard Backlight (Reserved) Need to check with SW. TP_VDD
1
1
EC6206
SC33P50V2JN-3GP
EC6205
SC33P50V2JN-3GP
1
1
RE53 RE54
2.2K_0402_5% 2.2K_0402_5% TP side has pull high
5V_S0 +5V_KB_BL
2
Q6204_G
2
2
F6201 @ R6203
1 2 2N7002KDW-GP 2 1 INT_TP#
1
0.5A_6V_SMD0603P050TF KBBL@ I2C1_SCL 1 6 I2C1_SCL_R 10KR2J-3-GP

C6202
1 2 2 5
2
R6205 KBBL@ 0R3J-0-U-GP SCD1U16V2KX-3GP

3 4 I2C1_SDA_R
KB_BL1
KBBL@ Q6204 TP_VDD 1 AFTP6239
R6206 1 TPCLK_C 1 AFTP6238
1 2 KB_LED_DET_C 2 1 TPDATA_C 1 AFTP6236
<20> KB_LED_BL_DET 2
1
3 5 I2C1_SDA I2C1_SCL_R 1 AFTP6237

51KR2J-1-GP @ 4 3 G1 6 I2C1_SDA_R 1 AFTP6240
1
KBBL@ R6207 4 G2 INT_TP# 1 AFTP6241

KB_BL_CTRL#
100KR2J-1-GP C6203 ACES_50524-00401-P01 TP_LOCK# 1 AFTP6242

CONN@
SCD1U16V2KX-3GP
2
B B
KB Backlight Power Consumption: 285mA max.

1
D Q6202
2 KBBL@
<24> KB_BL_CTRL G
1
S
3
R6208 LN2306LT1G_SOT23-3
@ 100KR2J-1-GP
+5V_KB_BL 1
KB_LED_DET_C 1 AFTP6248
2
KB_BL_CTRL# 1 AFTP6246
AFTP6247
For EMI Reserved

KB_BL_CTRL# EC6207 1 2 SCD1U16V2KX-3GP
@EMI@
+5V_KB_BL EC6208 1 2 SCD1U16V2KX-3GP
@EMI@
A A

Keyboard/Touch Pad
A00
5 4 3 2 1
5 4 3 2 1
Main Func = IO Connector
I/O Board Connector

X01_0808
D D
CN6301
24 26
23 24 GND 25
USB_PN1_C 22 23 GND
<34> USB_PN1_C 22
<34> USB_PP1_C USB_PP1_C 21
20 21
USB2 (USB2.0) <34>

<34>
USB_PP2_C
USB_PN2_C
USB_PP2_C
USB_PN2_C
19
18
20
19
18
17
USB3 (USB2.0) 1
R6301 @
2 GND_R1
0R2J-2-GP USB20_VCCA
16
15
17
16
15
14
13 14
USB2 (USB2.0) X01_0731 12 13

12
R6302 0R2J-2-GP 11
USB3 (USB2.0) 1 @
AUD_AGND
2 GND_R2 10
9
11
10
9
AUD_PORTA_L_R_B 8
<29> AUD_PORTA_L_R_B AUD_PORTA_R_R_B 7 8
<29> AUD_PORTA_R_R_B SLEEVE_R 6 7
<29> SLEEVE_R 6
5
Universal Jack <29> RING2_R RING2_R 4
3
5
4
3
<29> JACK_PLUG JACK_PLUG 2
1 2
AUD_AGND 1
ACES_51524-0240N-001
CONN@
C C
1
R6305
@ 2
Pitch: 1mm
Power: 5 pins
0R3J-0-U-GP
GND: 4 pins
AUD_AGND AGND: 2 Pins
RING2_R 1
AFTP6305 AFTE14P-GP
AUD_PORTA_L_R_B 1
AFTP6306 AFTE14P-GP
JACK_PLUG 1
AFTP6307 AFTE14P-GP
AUD_PORTA_R_R_B 1
AFTP6309 AFTE14P-GP
SLEEVE_R 1
B AFTP6310 AFTE14P-GP B
USB20_VCCA 1
AFTP6311 AFTE14P-GP
AUD_AGND 1
AFTP6313 AFTE14P-GP
A A

IO Board Connector
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = Hall Sensor
Move to Power Button Board

D D
C C
(Blanking)
B B
A A
Hall Sensor
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = Debug
D D
Debug Connector
Layout Note:
Place near trace separated point 3D3V_S0
LPC_AD[3..0] RN6501 DB@ DB1

<18,24> LPC_AD[3..0]
SRN0J-7-GP-U 1
LPC_AD0 4 5 LPC_LAD0_R 2 1
LPC_FRAME#_DEBUG 6 5
1 DB@ 2 PLT_RST#_DEBUG 7 6
<18,24> LPC_FRAME# 7
<17,24,30,36,52,58,73,96> PLT_RST# R6501 1 2 0R2J-2-GP 8
R6502 DB@ 0R2J-2-GP 9 8 11
<18> CLK_PCI_LPC 10 9 GND1 12
10 GND2
C C
MOLEX_53398-1071
CONN@
20.D0075.110: Dummy Pad with solder mask is ZZ.00PAD.Y41

DB1 Optional: New one smaller LPC connector is 20.F1180.010.
B B
A A
Dubug connector
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU 3V3_AON_S0

GPU1 N15V@ GPU1 N16V@
PDP-06877-006
R3 R3
1
GC6@
3V3_AON_S0 R7312 From GPIO21 N15V-GM-S-A2 BGA 595P GPU N16V-GM-S-B1 BGA 595P GPU
GC6_20 10KR2J-3-GP D7301
dGPU Reset 2
SA00007BR1L SA000088R1L
R7308 GPU_PEX_RST_HOLD <76>
5
U7301
2
GPU_PEX_RST# 1 2 GPU_PEX_RST_D# 1
VCC
1
<15> DGPU_HOLD_RST# IN1 4 3 SYS_PEX_RST_MON#
2 OUT 0R2J-2-GP
GND
<17,24,30,36,52,58,65,96> PLT_RST# IN2
GC6_20 BAT54A-7-F_SOT23-3
SYS_PEX_RST_MON# <76> GC6@
MC74VHC1G08DFT2G_SC70-5
3
DIS@ To GPIO8 GC6@ 1D05V_VGA_S0
1.05V +/- 30mV
1
D
R7306
3.3A D
R7304 1 2 0R2J-2-GP OPS 100KR2F-L1-GP

@
DY
1
3V3_AON_S0 GPU_PEX_RST# <76>
DIS@ C7312 C7310 OPS C7323 OPS C7326 OPS
SC1U10V2KX-1GP
SC4D7U6D3V3KX-GP
SC10U6D3V3MX-GP
SC22U6D3V5MX-2GP
OPS
2
GPU1A 1 OF 14
1/14 PCI_EXPRESS
2
GK208/GF117/GF119
DIS@
R7303 R7313 AB6 NC
OPS PEX_WAKE#
OPS 10KR2J-3-GP
2
DIS@ NON_GC6 AA22
SYS_PEX_RST_MON# 1 2 GPU_PEX_RST# AC7 PEX_IOVDD AB23
1
0R2J-2-GP PEX_RST# PEX_IOVDD AC24
PEX_IOVDD DIS@
1 3 GPU_CLKREQ# AC6 AD25 DIS@
<18,20> PEG_CLKREQ# PEX_CLKREQ# PEX_IOVDD DIS@ DIS@
AE26
Place close VDD ball Place close Chip
S
AE8 PEX_IOVDD AE27
<18> CLK_PCIE_VGA AD8 PEX_REFCLK PEX_IOVDD
Q7301 <18> CLK_PCIE_VGA#NOGC6@ PEX_REFCLK#
2N7002K_SOT23-3 C7301 1 2SCD1U16V2KX-3GP dGPU_TXP_CPU_RXP0 AC9
<16> CPU_RXP_C_dGPU_TXP0 PEX_TX0
<16> CPU_RXN_C_dGPU_TXN0 C7302 1 2SCD1U16V2KX-3GP dGPU_TXN_CPU_RXN0 AB9
1 2 PEX_TX0#
DY DIS@
DIS@ AG6
<16> dGPU_RXP_C_CPU_TXP0 PEX_RX0
R7305 AG7 AA10
<16> dGPU_RXN_C_CPU_TXN0 PEX_RX0# PEX_IOVDDQ
0R2J-2-GP AA12
C7303 1 2SCD1U16V2KX-3GP dGPU_TXP_CPU_RXP1 AB10 PEX_IOVDDQ AA13
@ <16> CPU_RXP_C_dGPU_TXP1 PEX_TX1 PEX_IOVDDQ
<16> CPU_RXN_C_dGPU_TXN1 C7304 1 2SCD1U16V2KX-3GP dGPU_TXN_CPU_RXN1 AC10 AA16
PEX_TX1# PEX_IOVDDQ AA18
DIS@ PEX_IOVDDQ
DIS@ AF7 AA19
<16> dGPU_RXP_C_CPU_TXP1 PEX_RX1 PEX_IOVDDQ
AE7 AA20
<16> dGPU_RXN_C_CPU_TXN1 PEX_RX1# PEX_IOVDDQ AA21
C7305 1 2SCD1U16V2KX-3GP dGPU_TXP_CPU_RXP2 AD11 PEX_IOVDDQ AB22
<16> CPU_RXP_C_dGPU_TXP2 PEX_TX2 PEX_IOVDDQ
<16> CPU_RXN_C_dGPU_TXN2 C7306 1 2SCD1U16V2KX-3GP dGPU_TXN_CPU_RXN2 AC11 AC23
PEX_TX2# PEX_IOVDDQ AD24
DIS@ PEX_IOVDDQ
DIS@ AE9 AE25
<16> dGPU_RXP_C_CPU_TXP2 PEX_RX2 PEX_IOVDDQ
AF9 AF26
<16> dGPU_RXN_C_CPU_TXN2 PEX_RX2# PEX_IOVDDQ AF27
C7307 1 2SCD1U16V2KX-3GP dGPU_TXP_CPU_RXP3 AC12 PEX_IOVDDQ
C C
<16> CPU_RXP_C_dGPU_TXP3 PEX_TX3
<16> CPU_RXN_C_dGPU_TXN3 C7308 1 2SCD1U16V2KX-3GP dGPU_TXN_CPU_RXN3 AB12
PEX_TX3#
DIS@
DIS@ AG9
<16> dGPU_RXP_C_CPU_TXP3 PEX_RX3
AG10
<16> dGPU_RXN_C_CPU_TXN3 PEX_RX3#
AB13
AC13 PEX_TX4
PEX_TX4#
AF10
AE10 PEX_RX4
PEX_RX4# 3.3V +/- 5%
AD14 3V3_AON_S0
AC14 PEX_TX5 AA8 210mA
PEX_TX5# PEX_PLL_HVDD AA9
AE12 PEX_PLL_HVDD
AF12 PEX_RX5
PEX_RX5# AB8
AC15 PEX_SVDD_3V3
AB15 PEX_TX6
PEX_TX6# Place close Chip
1
C7316 OPS C7324 OPS
OPSC7315
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
AG12
SCD1U25V2KX-GP
GPIO51(PCH) PEX_RX6
GPIO5 AG13
2
PEX_RX6#
AB16
AC16 PEX_TX7
PEX_TX7#
AF13
GPIO0 AE13 PEX_RX7
PEX_RX7#
AD17
PEX_TX8 NC DIS@
AC17
PEX_TX8# NC
DIS@ DIS@
AE15
PEX_RX8 NC
AF15 NC
PEX_RX8#
GPIO45 (PCH) AC18 F2
PEX_TX9 NC VDD_SENSE VGACORE_VDD_SENSE_1 <82>
AB18
GPIO96(KBC) PEX_TX9# NC
POWER IC
AG15 F1
PEX_RX9 NC GND_SENSE VGACORE_GND_SENSE_1 <82>
AG16
PEX_RX9# NC
B GPIO47 (PCH) GPIO51(KBC) B
GPIO6 AB19 NC
AC19 PEX_TX10
PEX_TX10# NC
GPIO54(PCH) AF16
PEX_RX10 NC
AE16
PEX_RX10# NC
GPIO8
AD20
PEX_TX11 NC
AC20
PEX_TX11# NC
GPIO21
AE18
PEX_RX11 NC
AF18
PEX_RX11# NC
AC21
PEX_TX12 NC
AB21 R7307
PEX_TX12# NC
200R2F-L-GP
AG18 AF22 PEXTSTCLK_OUT 1
AG19 PEX_RX12 NC PEX_TSTCLK_OUT AE22 PEXTSTCLK_OUT#
DY 2
PEX_RX12# NC PEX_TSTCLK_OUT#
AD23 1D05V_VGA_S0
AE23 PEX_TX13 NC
NC Place
@ close VDD ball Place close Chip DIS@ 1.05V +/- 30mV
PEX_TX13# L7301
AF19 AA14 VCC1R05VIDEO_PEX_PLLVDD 1 2 150mA
PEX_RX13 NC PEX_PLLVDD
PEX_RST# AE19 NC AA15 TAI-TECH HCB1608KF-121T30 0603
PEX_RX13# PEX_PLLVDD
AF24 C7318
PEX_TX14 NC
1
AE24 C7317 OPS C7319 OPS
PEX_TX14# NC OPS
SC4D7U6D3V3KX-GP
SC1U10V2KX-1GP
SCD1U16V2KX-3GP
AE21
NC R7302
2
AF21 PEX_RX14
PEX_RX14# NC
AD9 TESTMODE 1 OPS 2
AG24 TESTMODE 10KR2F-2-GP
PEX_TX15 NC
AG25 NC
PEX_TX15#
AG21 DIS@
PEX_RX15 NC
AG22
PEX_RX15# NC
OPS R7301
DIS@
GF119 GF117
AF25 PEX_TERMP 1 OPS 2 DIS@ DIS@
GK208
PEX_TERMP 2K49R2F-GP
A N14M-GE-S-A2-GP A
DIS@
N15V-GM-S-A2: JG0YH
N15S-GT is PXP79

GPU(1/5)PEG
A00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
LVDS Interface
GPU1G 7 OF 14
D 4/14 IFPAB GM108 D
GF117 GF119/GK208
GM108 NC AC4 GPU1I 9 OF 14
IFPA_TXC# AC3
NC 6/14 IFPD
GF119/GK208 GF117 IFPA_TXC
AA6 GF119/GK208 GF117
IFPAB_RSET NC GF117 GF119/GK208
Y3 U6
NC IFPA_TXD0# IFPD_RSET NC
Y4
NC IFPA_TXD0 DVI/HDMI DP
IFPAB_PLLVDD V7 GM108
IFPAB_PLLVDD NC
NC
AA2 IFPC_PLLVDD T7 I2CX_SDA IFPD_AUX_I2CX_SDA# P4
IFPA_TXD1# IFPD_PLLVDD NC NC
W7 AA3 NC I2CX_SCL P3
IFPAB_PLLVDD NC NC IFPA_TXD1 IFPD_AUX_I2CX_SCL
R7
IFPD_PLLVDD NC
AA1 R5
NC IFPA_TXD2# NC TXC IFPD_L3#
AB1 R4
NC IFPA_TXD2 NC TXC IFPD_L3
T5
NC TXD0 IFPD_L2#
AA5 T4
NC IFPA_TXD3# NC TXD0 IFPD_L2
AA4
NC IFPA_TXD3
TXD1 U4
NC IFPD_L1#
IFPD NC TXD1 IFPD_L1
U3
AB4
NC IFPB_TXC#
GM108 NC
AB5 V4
IFPB_TXC NC TXD2 IFPD_L0# V3
GF119/GK208 GF117 NC TXD2 IFPD_L0
IFPAB_IOVDD W6 AB2
IFPA_IOVDD NC NC IFPB_TXD4# AB3 GM108
NC IFPB_TXD4
Y6 IFPC_IOVDD R6 D4
IFPB_IOVDD NC IFPD_IOVDD NC NC GPIO17
AD2
NC GF119/GK208 GF117
1
1
IFPB_TXD5# AD3
NC IFPB_TXD5 RE55 RE56
1
1
10K_0402_5%
10K_0402_5%
RE57 RE58 AD1
NC IFPB_TXD6#
10K_0402_5%
10K_0402_5% AE1 N14M-GE-S-A2-GP
NC
2
2
IFPB_TXD6
2
2
NC
AD5
IFPB_TXD7#
NC IFPB_TXD7
AD4 OPS
C C
GM108
NC B3
GPIO14
IFPAB
N14M-GE-S-A2-GP
OPS
GPU1J 10 OF 14
7/14 IFPEF
GF119/GK208
GF117
GM108 DVI-DL DVI-SL/HDMI DP
GM108
HDMI Interface IFPEF_PLLVDD J7

GF119
GF117
GK208 NC
NC
I2CY_SDA
I2CY_SCL
I2CY_SDA
I2CY_SCL
IFPE_AUX_I2CY_SDA#
IFPE_AUX_I2CY_SCL
J3
J2
IFPEF_PLLVDD NC
GPU1H 8 OF 14
5/14 IFPC GM108 J1
IFPC NC TXC TXC IFPE_L3# K1
GF119/GK208 GF117 GM108 NC TXC TXC IFPE_L3
K7
IFPEF_PLLVDD NC
T6 NC GF117 GF119/GK208 K3
IFPC_RSET NC TXD0 TXD0 IFPE_L2# K2
NC TXD0 TXD0 IFPE_L2
DVI/HDMI DP
K6 M3
IFPEF_RSET NC NC TXD1 TXD1 IFPE_L1#
IFPD_PLLVDD M7 NC NC I2CW_SDA IFPC_AUX_I2CW_SDA# N5 M2
IFPC_PLLVDD NC TXD1 TXD1 IFPE_L1
N7 NC I2CW_SCL N4
IFPC_PLLVDD NC IFPC_AUX_I2CW_SCL M1
NC TXD2 TXD2 IFPE_L0# N1
NC TXD2 TXD2 IFPE_L0
N3
NC TXC IFPC_L3#
NC TXC
N2
IFPC_L3 IFPE NC FOR GK208
R3
NC TXD0 IFPC_L2# R2 GM108
NC TXD0 IFPC_L2
B NC C2 B
HPD_E HPD_E GPIO18
TXD1 R1
NC IFPC_L1#
NC TXD1 T1
IFPC_L1 GF117
T3 GF119 GK208
NC TXD2 IFPC_L0# T2 IFPEF_IOVDD H6 NC
NC TXD2 IFPC_L0 IFPE_IOVDD
GF119/GK208
J6 GF117
IFPF_IOVDD NC GM108 DVI-DL DVI-SL/HDMI DP
GM108
IFPD_IOVDD P6 NC C3 NC H4
IFPC_IOVDD NC GPIO15 I2CZ_SDA IFPF_AUX_I2CZ_SDA#
NC I2CZ_SCL H3
IFPF_AUX_I2CZ_SCL
N14M-GE-S-A2-GP
NC TXC J5
IFPF_L3#
1
1
NC TXC J4
RE59 RE60 IFPF_L3
1
1
10K_0402_5%
10K_0402_5% OPS NC TXD3 TXD0 IFPF_L2#
K5
RE61 RE62 NC K4
TXD3 TXD0 IFPF_L2
10K_0402_5%
10K_0402_5%
2
2
NC TXD4 TXD1 L4
IFPF IFPF_L1# L3
NC TXD4 TXD1
2
2
IFPF_L1
NC TXD5
M5
TXD2 IFPF_L0# M4
NC TXD5 TXD2 IFPF_L0
NC FOR GK208
GF117 GM108
NC F7
HPD_F GPIO19
N14M-GE-S-A2-GP
OPS
A A

GPU(2/5)DIGITALOUT
A00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
R7519
DY 1 2 1.35V +/- 3%
GC6_FB_EN <20,24,76,83> 1D35V_VGA_S0
<78,80> FBA_D[0..31]
GPU1B
2 OF 14
0R2J-2-GP
4.88A
R7518 Under GPU
2/14 FBA
FBA_D0 E18 F3 FB_CLAM 1 @
OPS 2 4 OF 14 GPU1D
FBA_D1 F18 FBA_D0 NC FB_CLAMP Near GPU
12/14 FBVDDQ
FBA_D2 E16 FBA_D1
FBA_D2 GF119 GF117/GK208 10KR2J-3-GP
FBA_D3 F17 B26
FBA_D4 D20 FBA_D3 FBVDDQ C25 C7501 C7502 C7525 C7507 C7513 C7514 C7517 C7520
FBA_D4 FBVDDQ
1
FBA_D5 D21 E23 OPS OPS OPS OPS OPS OPS OPS OPS
SC10U10V5KX-2GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
F20 FBA_D5 DIS@ FBVDDQ E26
FBA_D6
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
FBA_D6 FBVDDQ
SC22U6D3V5MX-2GP
FBA_D7 E21 F14
2
FBA_D8 E15 FBA_D7 FBVDDQ F21
FBA_D9 D15 FBA_D8 FBVDDQ G13
FBA_D10 F15 FBA_D9 FBVDDQ G14
FBA_D11 F13 FBA_D10 FBVDDQ G15
FBA_D12 C13 FBA_D11 FBVDDQ G16
FBA_D13 B13 FBA_D12 FBVDDQ G18
FBA_D14 E13 FBA_D13 FBVDDQ G19
FBA_D15 D13 FBA_D14 FBVDDQ G20
B15 FBA_D15 FBVDDQ G21 DIS@
FBA_D16 DIS@ DIS@
FBA_D17 C16 FBA_D16 GM108 FBVDDQ H24 DIS@ DIS@ DIS@ DIS@
FBA_D17 FBVDDQ_AON FBVDDQ
FBA_D18 A13 H26 DIS@
FBA_D19 A15 FBVDDQ_AON FBVDDQ J21
FBA_D20 B18 FBA_D19 K21
FBA_D21 A18 L22
FBA_D22 A19 FBA_D21 FBVDDQ L24
FBA_D23 C19 FBA_D22 FBVDDQ L26
FBA_D24 B24 FBA_D23 FBVDDQ M21
FBA_D25 C23 FBA_D24 FBVDDQ N21
FBA_D26 A25 FBA_D25 FBVDDQ R21
FBA_D27 A24 FBA_D26 FBVDDQ T21
FBA_D28 A21 FBA_D27 FBVDDQ V21
FBA_D29 B21 FBA_D28 FBVDDQ W21
FBA_D30 C20 FBA_D29 FBVDDQ
FBA_D31 C21 FBA_D30
<79,81> FBA_D[32..63] FBA_D31
FBA_D32 R22
FBA_D33 R24 FBA_D32 C27 FBA_CMD0
FBA_D33 FBA_CMD0 FBA_CMD0 <78,80>
FBA_D34 T22 C26 FBA_CMD1 FBA_CMD1 <80>
FBA_D35 R23 FBA_D34 FBA_CMD1 E24 FBA_CMD2
FBA_D35 FBA_CMD2 FBA_CMD2 <78>
FBA_D36 N25 F24 FBA_CMD3 FBA_CMD3 <78,80>
FBA_D37 N26 FBA_D36 FBA_CMD3 D27 FBA_CMD4
FBA_D37 FBA_CMD4 FBA_CMD4 <78,79,80,81>
FBA_D38 N23 D26 FBA_CMD5 FBA_CMD5 <78,79,80,81>
FBA_D39 N24 FBA_D38 FBA_CMD5 F25 FBA_CMD6
FBA_D40 V23 F26 FBA_CMD7 FBA_CMD7 <78,79,80,81>
FBA_D40 FBA_CMD7 1D35V_VGA_S0 1D35V_VGA_S0
FBA_D41 V22 F23 FBA_CMD8 FBA_CMD8 <78,79,80,81>
FBA_D42 T23 FBA_D41 FBA_CMD8 G22 FBA_CMD9
FBA_D43 U22 G23 FBA_CMD10 FBA_CMD10 <78,79,80,81>
FBA_D44 Y24 FBA_D43 FBA_CMD10 G24 FBA_CMD11
FBA_D44 FBA_CMD11 FBA_CMD11 <78,79,80,81> RE63
FBA_D45 AA24 F27 FBA_CMD12 FBA_CMD12 <78,79,80,81>
FBA_D46 Y22 FBA_D45 FBA_CMD12 G25 FBA_CMD13 FBA_CMD13 <78,79,80,81> FBA_CMD22 2 RE64 1
FBA_D46 FBA_CMD13
1
C FBA_D47 AA23 G27 FBA_CMD14 2 1 C7508 C
SCD1U16V2KX-3GP
FBA_D48 AD27 G26 FBA_CMD15 FBA_CMD15 <78,79,80,81> DY
FBA_D49 AB25 FBA_D48 FBA_CMD15 M24 FBA_CMD16 100_0402_5%
FBA_CMD16 <79,81>
2
FBA_D50 AD26 FBA_D49 FBA_CMD16 M23 FBA_CMD17 100_0402_5%
FBA_D50 FBA_CMD17 FBA_CMD17 <81> 1D35V_VGA_S0 RE66
FBA_D51 AC25 K24 FBA_CMD18 FBA_CMD18 <79>
FBA_D52 AA27 FBA_D51 FBA_CMD18 K23 FBA_CMD19 FBA_CMD30 2 RE65 1
FBA_D53 AA26 FBA_D52 FBA_CMD19 M27 FBA_CMD20
FBA_CMD19 <79,81> Under GPU 2 1
FBA_D54 W26 M26 FBA_CMD21 FBA_CMD21 <78,79,80,81> R7505
FBA_D55 Y25 FBA_D54 FBA_CMD21 M25 FBA_CMD22 2 1 FB_CAL_PD_VDDQ D22 100_0402_5%
FBA_D55 FBA_CMD22 FBA_CMD22 <78,79,80,81> OPS FB_CAL_PD_VDDQ 100_0402_5%
FBA_D56 R26 K26 FBA_CMD23 FBA_CMD23 <78,79,80,81>
FBA_D56 FBA_CMD23 RE67
FBA_D57 T25 K22 FBA_CMD24 FBA_CMD24 <78,79,80,81> 40D2R2F-GP @
FBA_D58 N27 FBA_D57 FBA_CMD24 J23 FBA_CMD25 FBA_CMD25 <78,79,80,81> FB_CAL_PU_GND C24 FBA_CMD11 2 RE68 1
FBA_D59 R27 FBA_D58 FBA_CMD25 J25 FBA_CMD26 FB_CAL_PU_GND 2 1
FBA_D59 FBA_CMD26 FBA_CMD26 <78,79,80,81> DIS@
1
FBA_D60 V26 J24 FBA_CMD27 C7509
SCD1U16V2KX-3GP
FBA_D60 FBA_CMD27 FBA_CMD27 <78,79> 100_0402_5%
FBA_D61 V27 K27 FBA_CMD28 FBA_CMD28 <78,79,80,81> FB_CAL_TERM_GND B25 DY
FBA_D62 W27 FBA_D61 FBA_CMD28 K25 FBA_CMD29 FB_CAL_TERM_GND 100_0402_5%
FBA_CMD29 <78,79,80,81> RE70
2
FBA_D63 W25 FBA_D62 FBA_CMD29 J27 FBA_CMD30 FBA_CMD30 <80,81>
FBA_D63 FBA_CMD30 J26 N14M-GE-S-A2-GP FBA_CMD15 2 RE69 1
FBA_CMD31 2 1
FBA_DQM0 D19 FBA_CMD31 1 TP7504 TPAD14-OP-GP
<78,80> FBA_DQM0 FBA_DQM0 100_0402_5%
1
FBA_DQM1 D14
<78,80> FBA_DQM1 FBA_DQM1 1D35V_VGA_S0 100_0402_5%
<78,80> FBA_DQM2
FBA_DQM2 C17
FBA_DQM2 @ R7507 R7506 OPS RE72
FBA_DQM3 C22 OPS OPS
51D1R2F-GP
42D2R2F-GP
<78,80> FBA_DQM3 FBA_DQM4 P24 FBA_DQM3 FBA_CMD24 2 RE71 1 @
<79,81> FBA_DQM4 FBA_DQM5 W24 FBA_DQM4 @ 2 1
2
<79,81> FBA_DQM5 FBA_DQM6 AA25 FBA_DQM5
<79,81> FBA_DQM6 FBA_DQM7 U25 FBA_DQM6 GM108 F22 FBA_DEBUG0 R7501 1 2 60D4R2F-GP 100_0402_5%
<79,81> FBA_DQM7 FBA_DQM7 FBA_CMD34 FBA_DEBUG0 J22 FBA_DEBUG1 R7503 1
DY 2 60D4R2F-GP 100_0402_5%
FBA_CMD35 FBA_DEBUG1 DY RE74
@
FBA_EDC0 E19 @ DIS@ DIS@ FBA_CMD6 2 RE73 1
<78,80> FBA_EDC0 FBA_DQS_WP0
1
FBA_EDC1 C15 2 1 C7510
SCD1U16V2KX-3GP
<78,80> FBA_EDC1 FBA_EDC2 B16 FBA_DQS_WP1 D24 FBA_CLK0P
<78,80> FBA_EDC2 FBA_EDC3 B22 FBA_DQS_WP2 FBA_CLK0 D25 FBA_CLK0N
FBA_CLK0P <78,80> 100_0402_5% OPS
FBA_CLK0N <78,80> RE75
2
<78,80> FBA_EDC3 FBA_EDC4 R25 FBA_DQS_WP3 FBA_CLK0# N22 FBA_CLK1P 100_0402_5%
FBA_CLK1P <79,81>
<79,81> FBA_EDC4 FBA_EDC5 W23 FBA_DQS_WP4 FBA_CLK1 M22 FBA_CLK1N FBA_CLK1N <79,81> FBA_CMD21 2 RE76 1
<79,81> FBA_EDC5 FBA_EDC6 AB26 FBA_DQS_WP5 FBA_CLK1# 2 1
<79,81> FBA_EDC6 FBA_EDC7 T26 FBA_DQS_WP6
<79,81> FBA_EDC7 FBA_DQS_WP7 100_0402_5%
100_0402_5%
RE77
F19 D18
<78,80> FBA_DQS_RN0 C14 FBA_DQS_RN0 FBA_WCK01 C18 FBA_CMD10 2 RE78 1 DIS@
<78,80> FBA_DQS_RN1 A16 FBA_DQS_RN1 FBA_WCK01# D17 2 1
<78,80> FBA_DQS_RN2 A22 FBA_DQS_RN2 FBA_WCK23 D16
<78,80> FBA_DQS_RN3 P25 FBA_DQS_RN3 FBA_WCK23# T24 100_0402_5%
<79,81> FBA_DQS_RN4 FBA_DQS_RN4 FBA_WCK45 RE80
100_0402_5%
1
W22 U24 C7512
SCD1U16V2KX-3GP
<79,81> FBA_DQS_RN5 AB27 FBA_DQS_RN5 FBA_WCK45# V24 FBA_CMD26 2 RE79 1 DY
<79,81> FBA_DQS_RN6 T27 FBA_DQS_RN6 FBA_WCK67 V25 2 1
2
<79,81> FBA_DQS_RN7 FBA_DQS_RN7 FBA_WCK67#
100_0402_5%
RE82
100_0402_5%
F16 62mA FBA_CMD27 2 RE81 1
FB_PLLAVDD 1D05V_VGA_S0
FBA_CMD0 2 1
P22
Under GPU Near GPU FBA_CMD16
FB_PLLAVDD L7501 100_0402_5%
FBA_CMD3
FB_PLLAVDD
H22 35mA FBA_PLL_AVDD 1 2 FBA_CMD19
RE83
100_0402_5%
@
FB_DLLAVDD
OPS FBA_CMD20 FBA_CMD12 2 RE84 1
GF117 GF119/GK208 2 1
C7505 C7506 TAI-TECH HCB1608KF-300T20 0603
100_0402_5%
1
B C7518 B
OPS OPS RE85
100_0402_5%
1
OPS C7522
SC22U6D3V5MX-2GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
2nd = 68.00334.051 FBA_CMD4 2 RE86 1 OPS
2
1
R7508 R7509 R7510 R7511 R7512 2 1
2
30ohm@100MHZ(ESR=0.01ohm)
10KR2F-2-GP
10KR2F-2-GP
10KR2F-2-GP
10KR2F-2-GP
10KR2F-2-GP
TP7503 1 FB_VREF D23 100_0402_5%
FB_VREF_PROBE DIS@ OPS OPS OPS OPS OPS RE88
100_0402_5%
2 RE87 1
@ FBA_CMD25
2
N14M-GE-S-A2-GP Sourcer suggest to change to 2 1
68.00335.051 from 68.00084.H41. 100_0402_5%
1
C7523
SCD1U16V2KX-3GP
RE89
100_0402_5%
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
2 RE90
OPSDIS@
OPS FBA_CMD13 1
2
2 1
100_0402_5%
@ RE92
100_0402_5%
FBA_CMD23 2 RE91 1
2 1
100_0402_5%
1
DIS@C7524
SCD1U16V2KX-3GP
RE93
100_0402_5%
FBA_CMD14 2 RE94 1
DY
2
2 1
100_0402_5%
RE95
100_0402_5%
FBA_CMD28 2 RE96 1
2 1
100_0402_5%
1
@ C7529
SCD1U16V2KX-3GP
RE98
100_0402_5%
FBA_CMD29 2 RE97 1
OPS
2
2 1
100_0402_5%
100_0402_5%
RE100
RE99
FBA_CMD9 2 1
2 1
DIS@
100_0402_5%
1
C7532
SCD1U16V2KX-3GP
100_0402_5%
OPS
2
RE101
FBA_CMD7 2 RE102 1
2 1
100_0402_5%
1
DIS@C7533
SCD1U16V2KX-3GP
100_0402_5%
DY
2
RE103
FBA_CMD8 2 RE104 1
A 2 1 A
100_0402_5%
1
C7534
SCD1U16V2KX-3GP
RE105
100_0402_5%
FBA_CMD5 2 RE106 1
OPS@
2
2 1
100_0402_5%
100_0402_5%
DIS@

GPU(3/5)VRAMI/F
A00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU

30ohm@100MHz
1D05V_VGA_S0 DCR=0.04 ohm
Straps
3V3_AON_S0 Max current = 3000mA
GPU1K 11 OF 14
3/14 DACA GM108 GM108
L7601 52mA
1 2 TAI-TECH HCB1608KF-300T20 0603
GF119/GK208 GF117 GF117 GF119/GK208 RE107
DIS@
RE108
W5 NC NC
B7 I2CA_SCL 2 1 C7605
DACA_VDD I2CA_SCL
1
SCD1U16V2KX-3GP
NC
A7 I2CA_SDA 2 1 C7606 GPU1M 13 OF 14
AE2 I2CA_SDA 3V3_AON_S0
DACA_VREF TSEN_VREF NC 2.2K_0402_5%
DIS@ SC2D2U6D3V2MX-GP 9/14 XTAL_PLL (DS-06814-001)
DIS@
2
AF2 AE3 2.2K_0402_5% GPU_PLL_VDD L6
DACA_RSET NC NC DACA_HSYNC CORE_PLLVDD
AE4 L7602 SP_PLLVDD M6
NC DACA_VSYNC 111mA SP_PLLVDD
1
1 2 N6 NC R7617
AG3 DIS@ CHILISIN PBY160808T-181Y-N 0603 VID_PLLVDD @ 10KR2J-3-GP
NC DACA_RED N6:On co-layout designs,
180ohm@100MHz this ball can be connected GF119/GK208 GF117
AF4 to power rail filter.
DCR=0.3 ohm
2
NC DACA_GREEN C7601 C7603 C7604 C7602
1
NC
AF3 Max current = 300mA
DACA_BLUE
SC10U6D3V3MX-GP
VIDEO_CLK_XTAL_SS A10 C10 N12P_XTAL_OUTBUFF
XTAL_SSIN XTAL_OUTBUFF
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SC4D7U6D3V3KX-GP
DIS@ @ DIS@ DIS@
2
PDP-06877-006
D C11 B10 D
N14M-GE-S-A2-GP XTAL_IN XTAL_OUT
1
N14M-GE-S-A2-GP R7602
1
@ @ 20PF 5% 50V +/-0.25PF 0402 10KR2J-3-GP
DIS@
DIS@ R7601 R7603
10KR2J-3-GP 1MR2J-1-GP
2
27MHZ_IN 1 2 27MHZ_OUT
2
@
X7601
2
1 4 DIS@ R7604
1K3R2J-GP
1
2 3 27MHZ_OUT_R GM:
C7607 = 78.18034.1FL
2
C7608 = 78.18034.1FL
C7607 DIS@ XTAL-27MHZ-85-GP-U DIS@ C7608 R7604 = 63.13234.1DL
12P_0402_50V DIS@ 15P_0402_50V
(RVL-06891-001)N15V-GM-S DDR3L Recommended Memories
1
2ND = 82.30034.651
3V3_AON_S0 Strap STRAP3 STRAP2 STRAP1 STRAP0
3RD = 82.30034.681
1
R7613
10KR2J-3-GP R7645 Hynix 0xC H5TC2G63FFR-11C 1 1 0 0
1 2 DIS@ 10KR2J-3-GP
<73> GPU_PEX_RST#
128Mx16 DDR3L
@
R7652 Micron 0x1 MT41K128M16JT-107G:K 0 0 0 1
2
1 VIDEO_THERM_OVERT# OVERT# 1 2 OVERT_GPU#
TP7606 @ DIS@ 0R2J-2-GP
Samsung 0x5 K4W2G1646E-BY11 0 1 0 1
1
VGA_CORE IC not support ALERT#.
DIS@ C7609
4
2nd = 84.2N702.E3F SC2700P50V2KX-1-GP
2
Q7602 3rd = 75.00601.07C
2N7002KDW-GP 4th = 84.DMN66.03F 256Mx16 DDR3L Hynix 0x4 H5TC4G63AFR-11C 0 1 0 0
DIS@
3
R7653 Micron 0xD MT41K256M16HA-107G:E 1 1 0 1
GPU1N 14 OF 14 3V3_AON_S0 P_H_S# 1 2 PURE_HW_SHUTDOWN# <24,26,36>
8/14 MISC1 GPIO9_ALERT DIS@
1
D9 SMBC_THERM_NV 0R2J-2-GP @
I2CS_SCL
I2CS_SDA
D8 SMBD_THERM_NV
R7612
C7610 Samsung 0x9 K4W4G1646D-BC1A 1 0 0 1
1 2 SC2700P50V2KX-1-GP
3V3_AON_S0
2
A9 I2CC_SCL @1 RE110 2 2.2K_0402_5%
I2CC_SCL B9 I2CC_SDA @1 RE109 2 2.2K_0402_5% 10KR2J-3-GP
I2CC_SDA DIS@ 3V3_AON_S0
GF119 3V3_AON_S0
C @
GF117 GK208 (DS-06814-001) C
TP7603 1 P2800_VGA_DXN E12
@ THERMDN C9 I2CB_SCL @1 RE112 2 2.2K_0402_5% 3V3_AON_S0
NC I2CB_SCL
TP7604 1 P2800_VGA_DXP F12 NC
C8 I2CB_SDA @1 RE111 2 2.2K_0402_5%
R7624
1
THERMDP I2CB_SDA
1
1
R7633 2 1 Q7601_G
N12P_JTAG_TCK AE5 GC6@ RE113 RE114
1 N12P_JTAG_TMS AD6 JTAG_TCK 10KR2J-3-GP DIS@ 0R2J-2-GP 4.7K_0402_5% 4.7K_0402_5%
TP7602 1 N12P_JTAG_TDI AE6 JTAG_TMS DIS@ DIS@
2
TP7605@ 1 N12P_JTAG_TDO AF6 JTAG_TDI
2
2
TP7601@ N12P_JTAG_TRST AG4 JTAG_TDO C6 GC6_FB_EN_GPU GPIO5_GC6_PWR_EN_GPU
JTAG_TRST# (GC6_FB_EN/FB_CLAMP_MON) GPIO0 Q7601
@ B2 3V3_MAIN_EN is an open-drain GPIO.
GPIO1 D6 3 4 SMBD_THERM_NV
GPIO2 <18,24,26> SML1_DATA
C7
3V3_AON_S0
1
1
GPIO3 F9 R7636 2 5
RE115 RE116 GPIO4 A3 GPIO5_GC6_PWR_EN_GPU 1 2
(3V3_MAIN_EN) GPIO5 GPIO5_GC6_PWR_EN <83>
10K_0402_5% 10K_0402_5% A4 GPU_EVENT_GPU# 0R2J-2-GP 1 6
(GPU_EVENT#/FB_CLAMP_TGL_REQ#)GPIO6
1
DIS@ DIS@ GK208
B6 GC6@
GPIO7 A6 OVERT_GPU# R7605 2N7002KDW-GP
OVERT
2
2
GPIO8 F8 GPIO9_ALERT DIS@ 100KR2J-1-GP DIS@

GPIO9 C5 GPIO10_FBVREF
GPIO10 E7 D7601 @
VGA_CORE_VID <82>
2
GPIO11 D7 PWR_LEVEL 2 1 SMBC_THERM_NV
GPIO12 AC_PRESENT <17,24>
B4
GPIO13 VGA_CORE_PSI <82> <18,24,26> SML1_CLK
L1SS400GT1G_SOD723-2
R7631 10KR2J-3-GP 2nd = 84.2N702.E3F
GK208 GF117 GF119 D7602 DIS@
3V3_AON_S0 1 2 3rd = 75.00601.07C
GPIO16 NC
D5 GC6@ 2 1 4th = 84.DMN66.03F
GPIO16 OVER_CURRENT_P8# <24>
GPIO20 NC
E6 GC6@
GPIO20 C4 GPU_PEX_RST_HOLD_GPU# 1 2 R7630
GPIO8 NC GPIO21 GPU_PEX_RST_HOLD <73> L1SS400GT1G_SOD723-2
0R2J-2-GP
GM108
(RVL-06891-001)N15V-
GT -S DDR3L Recommended Memories
DA-05691-001_V05 P15
GPIO20/21 NC : for ALL
N14M-GE-S-A2-GP
@ Strap
3D3V_VGA_S0
GPIO10_FBVREF
GPU1L 12 OF 14 Hynix 0x9 H5TC2G63FFR-11C
2
10/14 MISC2
128Mx16 DDR3L
1
R7626
@ R7610
GF117/GF119/GK208 10KR2J-3-GP
DIS@ 100KR2J-1-GP Micron 0xA MT41J128M16JT-093G:K
E10 NC
1
F10 VMON_IN0 D12 ROM_CS#

NC
2
VMON_IN1 ROM_CS#
ROM_SI
B12 ROM_SI Samsung 0xB K4W2G1646E-BY11
A12 ROM_SO
ROM_SO 3V3_AON_S0
STRAP0 D1 C12 ROM_SCLK
STRAP1 D2 STRAP0 ROM_SCLK
STRAP2 E4 STRAP1
STRAP2
Hynix 0x3 H5TC4G63AFR-11C
STRAP3 E3
2
N15V-GS supports Binary Mode. STRAP4 D3 STRAP3

B N15S-GT supports Multi-Level Strap. STRAP4 R7643 B
N15V-GM supports Binary Mode.
GF119
GF117 DIS@ @ 10KR2J-3-GP 256Mx16 DDR3L Micron 0x4 MT41J256M16HA-093G:E
N16V-GM supports Multi-Level Strap. GK208
C1 NC
R7628
(4 pcs VRAM)
1
STRAP5 D11 BUFRST# 2 1

N16V@ BUFRST# SYS_PEX_RST_MON_GPU# Samsung 0x5 K4W4G1646D-BC1A
1 2STRAP_REF0_GND_N9 F6 NC
D10 10KR2J-3-GP
MULTI_STRAP_REF0_GND PGOOD
R7607 40K2R2F-GP GF117 GF117
GF119
GK208 GK208
GF119
GC6@ Hynix 0xC H5TC4G63AFR-11C
F4 NC
R7629
MULTI_STRAP_REF1_GND GPIO8 E9 SYS_PEX_RST_MON_GPU# 1 2
F5
NC CEC 0R2J-2-GP SYS_PEX_RST_MON# <73> 256Mx16 DDR3L
MULTI_STRAP_REF2_GND NC GF117
GM108 Micron 0xD MT41J256M16HA-093G:E
GK208
GF119 Connect to SYS_PEX_RST_MON# (8 pcs VRAM)
N14M-GE-S-A2-GP if GC62.0 is implemented.
@ Leave NC for GC6 1.0. Samsung 0xE K4W4G1646D-BC1A
GC6@ NPN-06912 NPN-06975
R7623
GC6_FB_EN 1 2GC6_FB_EN_GPU
<20,24,75,83> GC6_FB_EN 3V3_AON_S0
0R2J-2-GP 3V3_AON_S0
1
3D3V_S0
R7627
2
@ 10KR2J-3-GP
2
R7649
GC6@ 10KR2J-3-GP R7648
2
GC6@ 10KR2J-3-GP
G
1
GPU_EVENT_GPU# 3 1
GPU_EVENT# <20>
S
Q7606 R7640,R7641,R7642 for N15S-GT 4 pcs VRAM Multi Strap:RAM_CFG[3:0]

2N7002K_SOT23-3
GC6@
R7619,R7638,R639 for N15S-GT 8 pcs VRAM 3V3_AON_S0
3D3V_VGA_S0 N15V-GM-S: Binary Strap for VRAMs.

N15S-GT-S: PH 49.9k ohm on STRAP0.
3V3_AON_S0
R7644
4K99R2F-L-GP
@
4K99R2F-L-GP
1
2 1
24K9R2F-L-GP
30K1R2F-L-GP
34K8R2F-1-GP
1
1
R7608
49K9R2F-L-GP
1
R7606 @ @ R7615 @ R7634

R7611
R7619
R7638
R7639
1
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
1
R7646
2
1
@ @ R7625
2
2
@ STRAP2 @ 10KR2J-3-GP R7635
2
ROM_SCLK @ @ @ @ 10KR2J-3-GP
2
STRAP3
2
A ROM_SO STRAP0 A
2
STRAP4
ROM_SI STRAP1
24K9R2F-L-GP
30K1R2F-L-GP
20KR2F-L-GP
1
1
R7616
R7614
R7640
R7641
R7642
10KR2F-2-GP
4K99R2F-L-GP
1
R7620
R7651
R7618
10KR2F-2-GP
10KR2F-2-GP
4K99R2F-L-GP
R7609 R7632 R7621 R7622

R7637 @ @ 10KR2J-3-GP @ 10KR2J-3-GP @ 10KR2J-3-GP @ 10KR2J-3-GP
SORx_EXPOSED=0000 10KR2J-3-GP
2
2
@ @ @ @
@ @ @
@
No VBIOS ROM

GPU(4/5)GPIO/STRAP
A00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU VGA_CORE

GPU1F 6 OF 14
13/14 GND
A2 M13
AB17 GND GND M15
Under GPU GPU1E 5 OF 14 AB20 GND GND M17
AB24 GND GND N10
11/14 NVVDD
K10 AC2 GND GND N12
K12 VDD AC22 GND GND N14
K14 VDD AC26 GND GND N16
C7722 C7708 C7723 C7702 C7701 K16 VDD AC5 GND GND N18
VDD GND GND
1
K18 AC8 P11
L11 VDD AD12 GND GND P13
SC4D7U6D3V3KX-GP
OPS
SC4D7U6D3V3KX-GP
OPS
SC4D7U6D3V3KX-GP
OPS
SC4D7U6D3V3KX-GP
OPS
SC4D7U6D3V3KX-GP
OPS VDD GND GND
L13 AD13 P15
2
L15 VDD A26 GND GND P17
L17 VDD AD15 GND GND P2
M10 VDD AD16 GND GND P23
D D
M16 VDD AD21 GND GND R10
M18 VDD AD22 GND GND R12
N11 VDD AE11 GND GND R14
N17 VDD AE20 GND GND T11
P10 VDD AB11 GND GND T13
C7709 C7725 C7721 C7720 C7719 P12 VDD AF1 GND GND T15
VDD GND GND
1
P14 AF11 T17
P16 VDD AF14 GND GND U10
SC4D7U6D3V3KX-GP
OPS
SC4D7U6D3V3KX-GP
OPS
SC4D7U6D3V3KX-GP
OPS
SC4D7U6D3V3KX-GP
OPS
SC4D7U6D3V3KX-GP
OPS VDD GND GND
P18 AF17 U12
2
R11 VDD AF20 GND GND U14
T10 VDD AG2 GND GND U23
T12 VDD AG26 GND GND U26
T14 VDD AB14 GND GND U5
T16 VDD B1 GND GND V11
T18 VDD B11 GND GND V13
U11 VDD B14 GND GND V15
U13 VDD B17 GND GND V17
OPS OPS OPS OPS VDD GND GND
U15 B20 Y2
U17 VDD B23 GND GND Y23
VDD GND GND
1
V10 B27 Y26
C7714 C7713 C7712 C7711 V12 VDD B5 GND GND Y5
VDD GND GND
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
V14 B8
2
V16 VDD E11 GND
V18 VDD E14 GND
VDD E17 GND
E2 GND
N14M-GE-S-A2-GP E20 GND
E22 GND
E25 GND
E5 GND
C C
E8 GND
H2 GND
OPS H23 GND
Near GPU H25 GND
H5 GND
K11 GND
K13 GND
K15 GND
K17 GND
C7732 C7731 C7730 C7726 C7724 C7717 C7710 L10 GND
GND
1
OPS OPS OPS OPS OPS OPS OPS L12
L14 GND
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
L16 GND
2
L18 GND
L2 GND
L23 GND
L25 GND
L5 GND AA7
M11 GND GND AB7
GND GND
N14M-GE-S-A2-GP
G10,G12:
If GC62.0 is implemented, connect to a 3V3 rail that will be on in GC6. OPS
If GC62.0 is NOT implemented, connect to the same rail as VDD33.
3V3_AON_S0
Under GPUNear GPU

B B
C7735
1
OPS C7736 C7704

SC1U10V2KX-1GP
SCD1U16V2KX-3GP
SC4D7U6D3V3KX-GP
OPS
GPU1C 3 OF 14
OPS
2
14/14 XVDD/VDD33
AD10 G10
AD7 NC#AD10(GM108:3V3_AON) VDD33 G12
B19 NC#AD7 (GM108:3V3_AON) VDD33 G8
NC#B19 FBA_CMD32 VDD33 G9
VDD33
F11
3V3AUX 3D3V_VGA_S0
V5
V6 NC#V5
NC#V6 Under GPU Near GPU
3.3V +/- 5%
CONFIGURABLE
POWER CHANNELS C7734 C7729
85mA
1
* nc on substrate OPS OPS C7728 C7703

SC1U10V2KX-1GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SC4D7U6D3V3KX-GP
OPS
G1 OPS
2
G2 NC#G1
G3 NC#G2
G4 NC#G3
G5 NC#G4
G6 NC#G5
G7 NC#G6
NC#G7
V1
A V2 NC#V1 A
NC#V2
W1
W2 NC#W1
W3 NC#W2
W4 NC#W3
NC#W4
N14M-GE-S-A2-GP 2015/01/20 2015/12/31 Title
Issued Date Deciphered Date
GPU(5/5)PWR/GND
A00
OPS
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU Data Bits 31:0 RANK 0

1D35V_VGA_S0 VRAM1 Place close VRAM1 VDD ball
VRAM1 FBA_D[0..31] <75,78,80> 1D35V_VGA_S0 VRAM2 1D35V_VGA_S0
B2 E3 FBA_D11 FBA_D[0..31] <75,78,80>
D9 VDD DQ0 F7 FBA_D13 VRAM2 B2 E3 FBA_D5
G7 VDD DQ1 F2 FBA_D8 D9 VDD DQ0 F7 FBA_D1
OPS
VDD DQ2 VDD DQ1
SC1U6D3V3KX-2GP
C7805
K2 F8 FBA_D15 G7 F2 FBA_D7
VDD DQ3 VDD DQ2
1
K8 H3 FBA_D10 K2 F8 FBA_D0 C7827 C7804
VDD DQ4 VDD DQ3
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
128M16 K4W2G1646Q-BC1A FBGA A31! N1 H8 FBA_D14 K8 H3 FBA_D4 DY DY
N9 VDD DQ5 G2 FBA_D9 N1 VDD DQ4 H8 FBA_D3
2
R1 VDD DQ6 H7 FBA_D12 N9 VDD DQ5 G2 FBA_D6
D SA000068U1L VDD DQ7 128M16 K4W2G1646Q-BC1A FBGA A31! VDD DQ6 D
1D35V_VGA_S0 R9 D7 FBA_D17 R1 H7 FBA_D2
VDD DQ8 C3 FBA_D22 1D35V_VGA_S0 R9 VDD DQ7 D7 FBA_D31
@ DQ9 SA000068U1L VDD DQ8
A1 C8 FBA_D16 C3 FBA_D25
A8 VDDQ DQ10 C2 FBA_D23 A1 DQ9 C8 FBA_D30
VDDQ DQ11 @ VDDQ DQ10
C1 A7 FBA_D19 A8 C2 FBA_D24
C9 VDDQ DQ12 A2 FBA_D21 C1 VDDQ DQ11 A7 FBA_D29
D2 VDDQ DQ13 B8 FBA_D18 C9 VDDQ DQ12 A2 FBA_D27
E9 VDDQ DQ14 A3 FBA_D20 D2 VDDQ DQ13 B8 FBA_D28
F1 VDDQ DQ15 E9 VDDQ DQ14 A3 FBA_D26 Place close VRAM2 VDD ball
H2 VDDQ F3 F1 VDDQ DQ15 1D35V_VGA_S0
VDDQ LDQS FBA_EDC1 <75,80> VDDQ
H9 G3 H2 F3
VDDQ LDQS# FBA_DQS_RN1 <75,80> VDDQ LDQS FBA_EDC0 <75,80>
H9 G3 OPS
VDDQ LDQS# FBA_DQS_RN0 <75,80>
C7 OPS
UDQS FBA_EDC2 <75,80>
SC1U6D3V3KX-2GP
C7822
FBA_VREF_0 H1 B7 C7
VREFDQ UDQS# FBA_DQS_RN2 <75,80> UDQS FBA_EDC3 <75,80>
1
R7808 M8 FBA_VREF_0 H1 B7 C7820 C7821
VREFCA VREFDQ UDQS# FBA_DQS_RN3 <75,80>
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 OPS 2 FBA_ZQ0 L8 K1 FBA_CMD0 <75,78,80> R7809 M8 DY
243R2F-2-GP ZQ ODT 1 OPS 2FBA_ZQ1 L8 VREFCA K1 FBA_CMD0 <75,78,80>
2
L2 243R2F-2-GP ZQ ODT
CS# FBA_CMD2 <75,78>
<75,78,79,80,81> FBA_CMD7 N3 T2 FBA_CMD20 <75,78,79,80,81> L2 FBA_CMD2 <75,78>
P7 A0 RESET# N3 CS# T2
<75,78,79,80,81> FBA_CMD10 A1 <75,78,79,80,81> FBA_CMD7 A0 RESET# FBA_CMD20 <75,78,79,80,81>
<75,78,79,80,81> FBA_CMD24 P3 J1 <75,78,79,80,81> FBA_CMD10 P7
N2 A2 NC#J1 J9 P3 A1 J1
<75,78,79,80,81> FBA_CMD6 A3 NC#J9 <75,78,79,80,81> FBA_CMD24 A2 NC#J1
<75,78,79,80,81> FBA_CMD22 P8 L1 <75,78,79,80,81> FBA_CMD6 N2 J9
P2 A4 NC#L1 L9 P8 A3 NC#J9 L1
<75,78,79,80,81> FBA_CMD26 A5 NC#L9 <75,78,79,80,81> FBA_CMD22 A4 NC#L1
<75,78,79,80,81> FBA_CMD5 R8 M7 <75,78,79,80,81> FBA_CMD26 P2 L9
R2 A6 NC#M7 T3 R8 A5 NC#L9 M7
<75,78,79,80,81> FBA_CMD21 A7 NC#T3 FBA_CMD12 <75,78,79,80,81>
<75,78,79,80,81> FBA_CMD5 A6 NC#M7
<75,78,79,80,81> FBA_CMD8 T8 T7 FBA_CMD14 <75,78,79,80,81>
<75,78,79,80,81> FBA_CMD21 R2 T3 FBA_CMD12 <75,78,79,80,81>
R3 A8 NC#T7 T8 A7 NC#T3 T7
<75,78,79,80,81> FBA_CMD4 A9 <75,78,79,80,81> FBA_CMD8 A8 NC#T7 FBA_CMD14 <75,78,79,80,81>
C
<75,78,79,80,81> FBA_CMD25 L7 <75,78,79,80,81> FBA_CMD4 R3 C
R7 A10/AP A9 L7 A9
<75,78,79,80,81>
<75,78,79,80,81>
FBA_CMD23
FBA_CMD9 N7 A11 VSS B3
<75,78,79,80,81>
<75,78,79,80,81>
FBA_CMD25
FBA_CMD23 R7 A10/AP A9 Place close VRAM1VDDQ ball
A12/BC# VSS E1 N7 A11 VSS B3 1D35V_VGA_S0
VSS <75,78,79,80,81> FBA_CMD9 A12/BC# VSS
G8 E1
M2 VSS J2 VSS G8
<75,78,79,80,81> FBA_CMD29 BA0 VSS VSS
<75,78,79,80,81> FBA_CMD13 N8 J8 <75,78,79,80,81> FBA_CMD29 M2 J2
BA1 VSS BA0 VSS
<75,78,79> FBA_CMD27 M3 M1 <75,78,79,80,81> FBA_CMD13 N8 J8 OPS OPS OPS OPS OPS
BA2 VSS BA1 VSS
SC1U6D3V3KX-2GP
C7812
SC1U6D3V3KX-2GP
C7810
SC1U6D3V3KX-2GP
C7814
M9 <75,78,79> FBA_CMD27 M3 M1
VSS BA2 VSS
1
P1 M9
E7 VSS P9 VSS P1
<75,80> FBA_DQM1
D3 LDM VSS T1 E7
OPS VSS P9
DY DY
<75,80> FBA_DQM2 <75,80> FBA_DQM0
2
UDM VSS T9 D3 LDM VSS T1
OPS VSS <75,80> FBA_DQM3 UDM VSS T9
J7 B1 VSS
<75,78,80> FBA_CLK0P CK VSSQ
<75,78,80> FBA_CLK0N K7 B9 <75,78,80> FBA_CLK0P FBA_CLK0P J7 B1
CK# VSSQ D1 FBA_CLK0N K7 CK VSSQ B9
VSSQ <75,78,80> FBA_CLK0N CK# VSSQ
<75,78,80> FBA_CMD3 FBA_CMD3 K9 D8 D1
CKE VSSQ E2 FBA_CMD3 K9 VSSQ D8
VSSQ <75,78,80> FBA_CMD3 CKE VSSQ
E8 E2
L3 VSSQ F9 VSSQ E8
<75,78,79,80,81> FBA_CMD28 WE# VSSQ VSSQ
K3 G1 L3 F9
<75,78,79,80,81> FBA_CMD15
<75,78,79,80,81> FBA_CMD11 J3 CAS# VSSQ G9
<75,78,79,80,81> FBA_CMD28
<75,78,79,80,81> FBA_CMD15 K3 WE# VSSQ G1 Place close VRAM2VDDQ ball
RAS# VSSQ J3 CAS# VSSQ G9 1D35V_VGA_S0
<75,78,79,80,81> FBA_CMD11 RAS# VSSQ
Check MT41K256M16HA-107G-E-GP
@ MT41K256M16HA-107G-E-GP
@ OPS OPS OPS OPS
SC1U6D3V3KX-2GP
C7817
SC1U6D3V3KX-2GP
C7811
SC1U6D3V3KX-2GP
C7816
1
1
B B
Frame Buffer Patition A-Lower Half DY DY DY
FBCLK Termination place on VRAM side
2
1D35V_VGA_S0
FBA_CLK0P
1
1K33R2F-GP
R7806
OPS R7810
162R2F-GP
2
FBA_VREF_0
<80> FBA_VREF_0 OPS
1
1
SC820P50V2KX-1GP
C7803
1K33R2F-GP
R7807
1
FBA_CLK0N
OPS OPS
2
Layout Note: Place in the end.

2
FBVREF Termination
A A
Type FBVREF% Voltage GPU_GPIO10
Un-termination 50% 0.749V High

Termination 70% 1.0617V Low Issued Date 2015/01/20 Deciphered Date 2015/12/31 Title
GPU-VRAM1,2 (1/4)
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1

VRAM3 1D35V_VGA_S0 VRAM3 1D35V_VGA_S0 VRAM4 Place close VRAM3 VDD ball
FBA_D[32..63] <75,79,81> FBA_D[32..63] <75,79,81> 1D35V_VGA_S0
B2 E3 FBA_D34 VRAM4 B2 E3 FBA_D44 OPS
D9 VDD DQ0 F7 FBA_D38 D9 VDD DQ0 F7 FBA_D43
VDD DQ1 VDD DQ1
G7 F2 FBA_D35 G7 F2 FBA_D45
VDD DQ2 VDD DQ2
SC1U6D3V3KX-2GP
C7906
K2 F8 FBA_D39 K2 F8 FBA_D40
VDD DQ3 VDD DQ3
1
128M16 K4W2G1646Q-BC1A FBGA A31! K8 H3 FBA_D32 K8 H3 FBA_D47
N1 VDD DQ4 H8 FBA_D36 N1 VDD DQ4 H8 FBA_D42
N9 VDD DQ5 G2 FBA_D33 N9 VDD DQ5 G2 FBA_D46
DY DY
D SA000068U1L 128M16 K4W2G1646Q-BC1A FBGA A31! D
2
R1 VDD DQ6 H7 FBA_D37 R1 VDD DQ6 H7 FBA_D41
1D35V_VGA_S0 R9 VDD DQ7 D7 FBA_D59 1D35V_VGA_S0 R9 VDD DQ7 D7 FBA_D52
@ VDD DQ8 SA000068U1L VDD DQ8
C3 FBA_D62 C3 FBA_D50
A1 DQ9 C8 FBA_D58 A1 DQ9 C8 FBA_D55
VDDQ DQ10 @ VDDQ DQ10
A8 C2 FBA_D63 A8 C2 FBA_D51
D2 VDDQ DQ13 B8 FBA_D56 D2 VDDQ DQ13 B8 FBA_D54
E9 VDDQ DQ14 A3 FBA_D61 E9 VDDQ DQ14 A3 FBA_D49
F1 VDDQ DQ15 F1 VDDQ DQ15
H2 VDDQ F3 H2 VDDQ F3 Place close VRAM4 VDD ball
VDDQ LDQS FBA_EDC4 <75,81> VDDQ LDQS FBA_EDC5 <75,81> 1D35V_VGA_S0
H9 G3 H9 G3
VDDQ LDQS# FBA_DQS_RN4 <75,81> VDDQ LDQS# FBA_DQS_RN5 <75,81>
C7 C7 OPS
UDQS FBA_EDC7 <75,81> UDQS FBA_EDC6 <75,81>
FBA_VREF_1 H1 B7 FBA_VREF_1 H1 B7 OPS OPS
VREFDQ UDQS# FBA_DQS_RN7 <75,81> VREFDQ UDQS# FBA_DQS_RN6 <75,81>
SC1U6D3V3KX-2GP
C7911
R7912 M8 R7913 M8
VREFCA VREFCA
1
1 OPS 2FBA_ZQ2 L8 K1 FBA_CMD16 <75,79,81> 1 OPS 2FBA_ZQ3 L8 K1 FBA_CMD16 <75,79,81>
243R2F-2-GP ZQ ODT 243R2F-2-GP ZQ ODT
L2 FBA_CMD18 <75,79> L2 FBA_CMD18 <75,79>
2
N3 CS# T2 N3 CS# T2
<75,78,79,80,81> FBA_CMD7 A0 RESET# FBA_CMD20 <75,78,79,80,81>
<75,78,79,80,81> FBA_CMD10 P7 <75,78,79,80,81> FBA_CMD10 P7
P3 A1 J1 P3 A1 J1
<75,78,79,80,81> FBA_CMD6 N2 J9 <75,78,79,80,81> FBA_CMD6 N2 J9
P8 A3 NC#J9 L1 P8 A3 NC#J9 L1
<75,78,79,80,81> FBA_CMD26 P2 L9 <75,78,79,80,81> FBA_CMD26 P2 L9
R8 A5 NC#L9 M7 R8 A5 NC#L9 M7
<75,78,79,80,81> FBA_CMD5 A6 NC#M7 <75,78,79,80,81> FBA_CMD5 A6 NC#M7
<75,78,79,80,81> FBA_CMD21 R2 T3 FBA_CMD12 <75,78,79,80,81>
<75,78,79,80,81> FBA_CMD21 R2 T3 FBA_CMD12 <75,78,79,80,81>
T8 A7 NC#T3 T7 T8 A7 NC#T3 T7
C R3 R3 C
<75,78,79,80,81>
<75,78,79,80,81>
FBA_CMD4
FBA_CMD25 L7 A9 <75,78,79,80,81>
<75,78,79,80,81>
FBA_CMD4
FBA_CMD25 L7 A9 Place close VRAM3 VDDQ ball
R7 A10/AP A9 R7 A10/AP A9 1D35V_VGA_S0
<75,78,79,80,81> FBA_CMD23 A11 VSS <75,78,79,80,81> FBA_CMD23 A11 VSS
<75,78,79,80,81> FBA_CMD9 N7 B3 <75,78,79,80,81> FBA_CMD9 N7 B3
A12/BC# VSS E1 A12/BC# VSS E1
VSS G8 VSS G8
VSS VSS
<75,78,79,80,81> FBA_CMD29 M2 J2 <75,78,79,80,81> FBA_CMD29 M2 J2 OPS OPS OPS
BA0 VSS BA0 VSS
SC1U6D3V3KX-2GP
C7916
SC1U6D3V3KX-2GP
C7915
SC1U6D3V3KX-2GP
C7919
BA1 VSS BA1 VSS
1
<75,78,79> FBA_CMD27 M3 M1 <75,78,79> FBA_CMD27 M3 M1
BA2 VSS M9 BA2 VSS M9
VSS P1 VSS P1
DY DY DY DY
OPS
2
E7 VSS P9 E7 VSS P9
<75,81> FBA_DQM4 LDM VSS <75,81> FBA_DQM5 LDM VSS
<75,81> FBA_DQM7 D3 T1 D3 T1
UDM VSS <75,81> FBA_DQM6 UDM VSS
T9 T9
VSS VSS
<75,79,81> FBA_CLK1P J7 OPS B1 <75,79,81> FBA_CLK1P FBA_CLK1P J7 B1
K7 CK VSSQ B9 FBA_CLK1N K7 CK VSSQ B9
<75,79,81> FBA_CLK1N CK# VSSQ <75,79,81> FBA_CLK1N CK# VSSQ
D1 D1
FBA_CMD19 K9 VSSQ D8 FBA_CMD19 K9 VSSQ D8
<75,79,81> FBA_CMD19 CKE VSSQ <75,79,81> FBA_CMD19 CKE VSSQ
E2 E2
VSSQ E8 VSSQ E8
L3 VSSQ F9 L3 VSSQ F9
<75,78,79,80,81> FBA_CMD28 WE# VSSQ <75,78,79,80,81> FBA_CMD28 WE# VSSQ
<75,78,79,80,81> FBA_CMD15 K3 G1 <75,78,79,80,81> FBA_CMD15 K3 G1
J3 CAS# VSSQ G9 J3 CAS# VSSQ G9
<75,78,79,80,81> FBA_CMD11 RAS# VSSQ <75,78,79,80,81> FBA_CMD11 RAS# VSSQ Place close VRAM4 VDDQ ball
1D35V_VGA_S0
MT41K256M16HA-107G-E-GP MT41K256M16HA-107G-E-GP
B @ @ B
OPS OPS OPS OPS OPS
SC1U6D3V3KX-2GP
C7917
SC1U6D3V3KX-2GP
C7926
SC1U6D3V3KX-2GP
C7924
1
1
Frame Buffer Patition A-Lower Half DY DY
FBCLK Termination place on VRAM side
2
1D35V_VGA_S0
FBA_CLK1P
1
1K33R2F-GP
R7903
OPS R7914
162R2F-GP
2
FBA_VREF_1
<81> FBA_VREF_1 OPS
1
1
SC820P50V2KX-1GP
C7902
1K33R2F-GP
R7904
1
FBA_CLK1N
OPS
OPS
2
Layout Note: Place in the end.
A A

GPU-VRAM3,4 (2/4)
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
1D35V_VGA_S0 VRAM5 Place close VRAM5 VDD ball

FBA_D[0..31] <75,78,80> 1D35V_VGA_S0 VRAM6 1D35V_VGA_S0
B2 E3 FBA_D13 FBA_D[0..31] <75,78,80>
D9 VDD DQ0 F7 FBA_D11 B2 E3 FBA_D1
G7 VDD DQ1 F2 FBA_D15 D9 VDD DQ0 F7 FBA_D5
VDD DQ2 VDD DQ1
SC1U6D3V3KX-2GP
C8003
K2 F8 FBA_D8 G7 F2 FBA_D0
VDD DQ3 VDD DQ2
1
D K8 H3 FBA_D12 K2 F8 FBA_D7 VRAM 8 PCS C8001 C8002 D
VDD DQ4 VDD DQ3
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
N1 H8 FBA_D9 K8 H3 FBA_D2 DY VRAM 8 PCS
N9 VDD DQ5 G2 FBA_D14 N1 VDD DQ4 H8 FBA_D6
2
R1 VDD DQ6 H7 FBA_D10 N9 VDD DQ5 G2 FBA_D3
1D35V_VGA_S0 R9 VDD DQ7 D7 FBA_D22 R1 VDD DQ6 H7 FBA_D4
VDD DQ8 C3 FBA_D17 1D35V_VGA_S0 R9 VDD DQ7 D7 FBA_D25
A1 DQ9 C8 FBA_D23 VDD DQ8 C3 FBA_D31
A8 VDDQ DQ10 C2 FBA_D16 A1 DQ9 C8 FBA_D24
C1 VDDQ DQ11 A7 FBA_D20 A8 VDDQ DQ10 C2 FBA_D30
D2 VDDQ DQ13 B8 FBA_D21 C9 VDDQ DQ12 A2 FBA_D28
E9 VDDQ DQ14 A3 FBA_D19 D2 VDDQ DQ13 B8 FBA_D27
F1 VDDQ DQ15 E9 VDDQ DQ14 A3 FBA_D29 Place close VRAM6 VDD ball
H2 VDDQ F3 F1 VDDQ DQ15 1D35V_VGA_S0
VDDQ LDQS FBA_EDC1 <75,78> VDDQ
H9 G3 H2 F3
VDDQ LDQS# FBA_DQS_RN1 <75,78> VDDQ LDQS FBA_EDC0 <75,78>
H9 G3
VDDQ LDQS# FBA_DQS_RN0 <75,78>
C7
UDQS FBA_EDC2 <75,78>
SC1U6D3V3KX-2GP
C8006
<78,80> FBA_VREF_0 FBA_VREF_0 H1 B7 C7
VREFDQ UDQS# FBA_DQS_RN2 <75,78> UDQS FBA_EDC3 <75,78>
1
R8002 M8 <78,80> FBA_VREF_0 FBA_VREF_0 H1 B7 C8004 C8005
VREFCA VREFDQ UDQS# FBA_DQS_RN3 <75,78>
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
VRAM 8 PCS 1 243R2F-2-GP
2 FBA_ZQ5 L8
ZQ ODT
K1 FBA_CMD0 <75,78,80> R8001
1 2FBA_ZQ6
M8
L8 VREFCA K1
DY DY VRAM 8 PCS
FBA_CMD0 <75,78,80>
2
L2 243R2F-2-GP ZQ ODT
CS# FBA_CMD1 <75,80>
<75,78,79,80,81> FBA_CMD9 N3 T2 FBA_CMD20 <75,78,79,80,81> VRAM 8 PCS L2 FBA_CMD1 <75,80>
P7 A0 RESET# N3 CS# T2
<75,78,79,80,81> FBA_CMD24 A1 <75,78,79,80,81> FBA_CMD9 A0 RESET# FBA_CMD20 <75,78,79,80,81>
<75,78,79,80,81> FBA_CMD10 P3 J1 <75,78,79,80,81> FBA_CMD24 P7
N2 A2 NC#J1 J9 P3 A1 J1
<75,78,79,80,81> FBA_CMD26 P8 L1 <75,78,79,80,81> FBA_CMD13 N2 J9
P2 A4 NC#L1 L9 P8 A3 NC#J9 L1
<75,78,79,80,81> FBA_CMD21 R8 M7 <75,78,79,80,81> FBA_CMD22 P2 L9
C R2 A6 NC#M7 T3 R8 A5 NC#L9 M7 C
<75,78,79,80,81> FBA_CMD21 A6 NC#M7
<75,78,79,80,81> FBA_CMD8 T8 T7 FBA_CMD12 <75,78,79,80,81>
<75,78,79,80,81> FBA_CMD5 R2 T3 FBA_CMD14 <75,78,79,80,81>
R3 A8 NC#T7 T8 A7 NC#T3 T7
<75,78,79,80,81> FBA_CMD23 A9 <75,78,79,80,81> FBA_CMD8 A8 NC#T7 FBA_CMD12 <75,78,79,80,81>
<75,78,79,80,81> FBA_CMD28 L7 <75,78,79,80,81> FBA_CMD23 R3
R7 A10/AP A9 L7 A9
<75,78,79,80,81>
<75,78,79,80,81>
FBA_CMD4
FBA_CMD7 N7 A11 VSS B3
<75,78,79,80,81>
<75,78,79,80,81>
FBA_CMD28
FBA_CMD4 R7 A10/AP A9 Place close VRAM5VDDQ ball
A12/BC# VSS E1 N7 A11 VSS B3 1D35V_VGA_S0
VSS <75,78,79,80,81> FBA_CMD7 A12/BC# VSS
G8 E1
M2 VSS J2 VSS G8
<75,78,79,80,81> FBA_CMD29
N8 BA0 VSS J8 M2 VSS J2
VRAM 8 PCS VRAM 8 PCS
<75,78,79,80,81> FBA_CMD6 BA1 VSS <75,78,79,80,81> FBA_CMD29 BA0 VSS
<75,80,81> FBA_CMD30 M3 M1 <75,78,79,80,81> FBA_CMD6 N8 J8
BA2 VSS BA1 VSS
SC1U6D3V3KX-2GP
C8007
SC1U6D3V3KX-2GP
C8008
SC1U6D3V3KX-2GP
C8009
M9 <75,80,81> FBA_CMD30 M3 M1
VSS BA2 VSS
1
P1 M9
E7 VSS P9 VSS P1
<75,78> FBA_DQM1
D3 LDM VSS T1 E7
VRAM 8 PCS
VSS P9
DY DY DY DY
<75,78> FBA_DQM2 <75,78> FBA_DQM0
2
UDM VSS T9 D3 LDM VSS T1
VSS <75,78> FBA_DQM3 UDM VSS
VRAM 8 PCS T9
J7 B1 VSS
<75,78,80> FBA_CLK0P CK VSSQ
<75,78,80> FBA_CLK0N K7 B9 <75,78,80> FBA_CLK0P FBA_CLK0P J7 B1
CK# VSSQ D1 FBA_CLK0N K7 CK VSSQ B9
VSSQ <75,78,80> FBA_CLK0N CK# VSSQ
<75,78,80> FBA_CMD3 FBA_CMD3 K9 D8 D1 VRAM 8 PCS
CKE VSSQ E2 FBA_CMD3 K9 VSSQ D8
VSSQ <75,78,80> FBA_CMD3 CKE VSSQ
E8 E2
L3 VSSQ F9 VSSQ E8
<75,78,79,80,81> FBA_CMD25 WE# VSSQ VSSQ
K3 G1 L3 F9
<75,78,79,80,81> FBA_CMD15
<75,78,79,80,81> FBA_CMD11 J3 CAS# VSSQ G9
<75,78,79,80,81> FBA_CMD25
<75,78,79,80,81> FBA_CMD15 K3 WE# VSSQ G1 Place close VRAM6VDDQ ball
RAS# VSSQ J3 CAS# VSSQ G9 1D35V_VGA_S0
<75,78,79,80,81> FBA_CMD11 RAS# VSSQ
MT41K256M16HA-107G-E-GP VRAM 8 PCS VRAM 8 PCS VRAM 8 PCS
B MT41K256M16HA-107G-E-GP B
@
SC1U6D3V3KX-2GP
C8014
SC1U6D3V3KX-2GP
C8015
SC1U6D3V3KX-2GP
C8016
@
1
DY
2
VRAM 8 PCS
FBVREF Termination
Type FBVREF% Voltage GPU_GPIO10
Un-termination 50% High

A 0.749V A
Termination 70% 1.0617V Low

GPU-VRAM5,6 (3/4)
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
1D35V_VGA_S0 VRAM7 1D35V_VGA_S0 VRAM8 Place close VRAM7 VDD ball

FBA_D[32..63] <75,79,81> FBA_D[32..63] <75,79,81> 1D35V_VGA_S0
B2 E3 FBA_D38 B2 E3 FBA_D43
D9 VDD DQ0 F7 FBA_D34 D9 VDD DQ0 F7 FBA_D44
VDD DQ1 VDD DQ1
G7 F2 FBA_D39 G7 F2 FBA_D40
VDD DQ2 VDD DQ2
SC1U6D3V3KX-2GP
C8103
D K2 F8 FBA_D35 K2 F8 FBA_D45 D
VDD DQ3 VDD DQ3
1
K8 H3 FBA_D37 K8 H3 FBA_D41
N1 VDD DQ4 H8 FBA_D33 N1 VDD DQ4 H8 FBA_D46
N9 VDD DQ5 G2 FBA_D36 N9 VDD DQ5 G2 FBA_D42
DY DY
2
R1 VDD DQ6 H7 FBA_D32 R1 VDD DQ6 H7 FBA_D47
1D35V_VGA_S0 R9 VDD DQ7 D7 FBA_D62 1D35V_VGA_S0 R9 VDD DQ7 D7 FBA_D50
VRAM 8 PCS
VDD DQ8 C3 FBA_D59 VDD DQ8 C3 FBA_D52
A1 DQ9 C8 FBA_D63 A1 DQ9 C8 FBA_D51
A8 VDDQ DQ10 C2 FBA_D58 A8 VDDQ DQ10 C2 FBA_D55
D2 VDDQ DQ13 B8 FBA_D60 D2 VDDQ DQ13 B8 FBA_D48
E9 VDDQ DQ14 A3 FBA_D57 E9 VDDQ DQ14 A3 FBA_D53
F1 VDDQ DQ15 F1 VDDQ DQ15
H2 VDDQ F3 H2 VDDQ F3 Place close VRAM8 VDD ball
VDDQ LDQS FBA_EDC4 <75,79> VDDQ LDQS FBA_EDC5 <75,79> 1D35V_VGA_S0
H9 G3 H9 G3
VDDQ LDQS# FBA_DQS_RN4 <75,79> VDDQ LDQS# FBA_DQS_RN5 <75,79>
C7 C7 VRAM 8 PCS
UDQS FBA_EDC7 <75,79> UDQS FBA_EDC6 <75,79>
<79,81> FBA_VREF_1 FBA_VREF_1 H1 B7 <79,81> FBA_VREF_1 FBA_VREF_1 H1 B7
VREFDQ UDQS# FBA_DQS_RN7 <75,79> VREFDQ UDQS# FBA_DQS_RN6 <75,79>
SC1U6D3V3KX-2GP
C8106
R8102 M8 R8101 M8
VREFCA VREFCA
1
1 2FBA_ZQ7 L8 K1 FBA_CMD16 <75,79,81> 1 2FBA_ZQ8 L8 K1 FBA_CMD16 <75,79,81>
243R2F-2-GP ZQ ODT 243R2F-2-GP ZQ ODT
VRAM 8 PCS L2 FBA_CMD17 <75,81> VRAM 8 PCS L2 FBA_CMD17 <75,81> VRAM 8 PCS VRAM 8 PCS
2
N3 CS# T2 N3 CS# T2
<75,78,79,80,81> FBA_CMD24 P7 <75,78,79,80,81> FBA_CMD24 P7
P3 A1 J1 P3 A1 J1
P8 A3 NC#J9 L1 P8 A3 NC#J9 L1
<75,78,79,80,81> FBA_CMD22 P2 L9 <75,78,79,80,81> FBA_CMD22 P2 L9
C R8 A5 NC#L9 M7 R8 A5 NC#L9 M7 C
<75,78,79,80,81> FBA_CMD21 A6 NC#M7 <75,78,79,80,81> FBA_CMD21 A6 NC#M7
<75,78,79,80,81> FBA_CMD5 R2 T3 FBA_CMD14 <75,78,79,80,81>
<75,78,79,80,81> FBA_CMD5 R2 T3 FBA_CMD14 <75,78,79,80,81>
T8 A7 NC#T3 T7 T8 A7 NC#T3 T7
R3 R3
<75,78,79,80,81>
<75,78,79,80,81>
FBA_CMD23
FBA_CMD28 L7 A9 <75,78,79,80,81>
<75,78,79,80,81>
FBA_CMD23
FBA_CMD28 L7 A9 Place close VRAM7 VDDQ ball
R7 A10/AP A9 R7 A10/AP A9 1D35V_VGA_S0
<75,78,79,80,81> FBA_CMD4 A11 VSS <75,78,79,80,81> FBA_CMD4 A11 VSS
<75,78,79,80,81> FBA_CMD7 N7 B3 <75,78,79,80,81> FBA_CMD7 N7 B3
A12/BC# VSS E1 A12/BC# VSS E1
VSS G8 VSS G8
VSS VSS
<75,78,79,80,81> FBA_CMD29 M2 J2 <75,78,79,80,81> FBA_CMD29 M2 J2
BA0 VSS BA0 VSS
SC1U6D3V3KX-2GP
C8107
SC1U6D3V3KX-2GP
C8108
SC1U6D3V3KX-2GP
C8109
BA1 VSS BA1 VSS
1
<75,80,81> FBA_CMD30 M3 M1 <75,80,81> FBA_CMD30 M3 M1
BA2 VSS M9 BA2 VSS M9
VSS P1 VSS P1
DY DY
VRAM 8 PCS VSS
2
E7 VSS P9 E7 P9
<75,79> FBA_DQM4 LDM VSS <75,79> FBA_DQM5 LDM VSS
<75,79> FBA_DQM7 D3 T1 D3 T1
UDM VSS <75,79> FBA_DQM6 UDM VSS
T9 T9
VSS VSS
J7
VRAM 8 PCS B1 FBA_CLK1P J7 B1
<75,79,81> FBA_CLK1P
K7 CK VSSQ B9
<75,79,81> FBA_CLK1P
FBA_CLK1N K7 CK VSSQ B9
VRAM 8 PCS VRAM 8 PCS VRAM 8 PCS
<75,79,81> FBA_CLK1N CK# VSSQ <75,79,81> FBA_CLK1N CK# VSSQ
D1 D1
FBA_CMD19 K9 VSSQ D8 FBA_CMD19 K9 VSSQ D8
<75,79,81> FBA_CMD19 CKE VSSQ <75,79,81> FBA_CMD19 CKE VSSQ
E2 E2
VSSQ E8 VSSQ E8
L3 VSSQ F9 L3 VSSQ F9
<75,78,79,80,81> FBA_CMD25 WE# VSSQ <75,78,79,80,81> FBA_CMD25 WE# VSSQ
<75,78,79,80,81> FBA_CMD15 K3 G1 <75,78,79,80,81> FBA_CMD15 K3 G1
J3 CAS# VSSQ G9 J3 CAS# VSSQ G9
<75,78,79,80,81> FBA_CMD11 RAS# VSSQ <75,78,79,80,81> FBA_CMD11 RAS# VSSQ Place close VRAM8 VDDQ ball
1D35V_VGA_S0
B MT41K256M16HA-107G-E-GP MT41K256M16HA-107G-E-GP B
VRAM 8 PCS
@ @
SC1U6D3V3KX-2GP
C8114
SC1U6D3V3KX-2GP
C8115
SC1U6D3V3KX-2GP
C8116
1
1
DY DY DY DY
2
VRAM 8 PCS
VRAM 8 PCS
A A

GPU-VRAM7,8 (4/4)
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = dGFX_CORE
@ PG8201
2 1
PU8203, PU8205, PU8207 and PU8209 manually change to 84.SRA12.037

PAD-OPEN 4x4m
@EMI@ PL8203
PWR_DCBATOUT_VGA_CORE1
FBMJ4516HS720NT_2P
2 1
DCBATOUT
D VGA@ VGA@ D
VGA@ VGA@ PC8210 PC8214 VGA@EMI@
SIRA12DP-T1-GE3 1N SIRA14DP-T1GE3_POWERPAK-SO8-5
SIRA12DP-T1-GE3 1N SIRA14DP-T1GE3_POWERPAK-SO8-5
PC8208
2200P_0402_25V7K
PC8209 PC8220
2
10U_0805_25VAK
10U_0805_25VAK
@EMI@ PC8227
2
2
4.7U_0805_25V6-K
0.1U_0402_25V6
4.7U_0805_25V6-K
5
5
5V_S0
1
PWR_VGA_CORE_UGATE1
@ PU8202 PU8204
1
VGA@
VGA@
2
PR4913 4 4
2.2_0603_5%
1
VGA_CORE
RT8812_PVCC
3
2
1
3
2
1
VGA@
PL8201
VGA@ VGA@
1
PC8202 1 2
PC8207
2 1PWR_VGA_CORE_TON_1 0.1U_0603_50V7K 0.33UH_PCMC063T-R33MN_20A_20%
PT8206
PT8207
18
330U_2.5V_M
330U_2.5V_M
1 1
0.1U_0402_25V6 PU8201 PU8203 PU8205
VGA@ VGA@ VGA@ @EMI@ PR8216 + +
PVCC
VGA@ PR8202 PR8201 4.7_0805_5%
VGA@
VGA@
2.2_0402_1% 499K_0402_1%
1
2 1 2 1 PWR_VGA_CORE_TON 9 2 PWR_VGA_CORE_UGATE1 4 4 2 2
DCBATOUT TON UGATE1 @ PR8210 VGA@ PC8211
2
PR8203 0_0603_5% 0.1U_0603_50V7K @ PG8202
2 1 13 1 PWR_VGA_CORE_BOOT12 1 PWR_VGA_CORE_BOOT1_1 2 1 @EMI@ PC8206
3V3_AON_S0 PGOOD BOOT1
VGA@ 330P_0402_50V7K 2 1
1
2
3
1
2
3
1
100K_0402_1%
PWR_VGA_CORE_EN 3 20 PWR_VGA_CORE_PHASE1
EN PHASE1 PAD-OPEN 4x4m
[15,24,83] DGPU_PWROK
@ PR8207 PWR_VGA_CORE_PSI 4 19 PWR_VGA_CORE_LGATE1 PWR_DCBATOUT_VGA_CORE2 @EMI@ PL8204
0_0402_5% PSI LGATE1
[76] VGA_CORE_VID
2 1 VGA@2 PR8224
1
OCP setting (current limit ~ 60.3A) FBMJ4516HS720NT_2P
2 1
PC8203 DCBATOUT
SIRA14DP-T1GE3_POWERPAK-SO8-5
SIRA14DP-T1GE3_POWERPAK-SO8-5
10.7K_0402_1% OPS should be in DUMMY column. VGA@ VGA@ VGA@EMI@
@ 1000P_0402_50V7K
1 2 PWR_VGA_CORE_VID 5 14 PWR_VGA_CORE_UGATE2 VGA@ VGA@ PC8215 PC8224
2200P_0402_25V7K
VID UGATE2 @ PR8211 VGA@ PC8216 PC8221
@EMI@ PC8228
PC8212 PC8213
2
10U_0805_25VAK
10U_0805_25VAK
C PC8201 0_0603_5% 0.1U_0603_50V7K VGA@ C
@
0.1U_0402_25V6
PWR_VGA_CORE_RGND 2 1 PWR_VGA_CORE_VREF 8 15 PWR_VGA_CORE_BOOT22 1 PWR_VGA_CORE_BOOT2_1 2 1
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@ PU8206 PU8208
PWR_VGA_CORE_UGATE2
VREF BOOT2
1
0.1U_0402_16V4Z
PWR_VGA_CORE_REFIN 7 16 PWR_VGA_CORE_PHASE2
2
R2 REFIN PHASE2 4 4
VGA@N15@ PR8206
7.5K_0402_1%
R1 PWR_VGA_CORE_REFADJ 6 17 PWR_VGA_CORE_LGATE2
REFADJ LGATE2
2
REFIN_VREF VGA@N15@
1
3
2
1
3
2
1
PR8222 PWR_VGA_CORE_SS 11 12 PWR_VGA_CORE_VSNS
R3 27K_0402_1%
SS VSNS VGA_CORE
VGA@
1
@ PL8202
21 10 PWR_VGA_CORE_RGND
2 1 PC8205
1
GND RGND 1 2
SIRA12DP-T1-GE3 1N
SIRA12DP-T1-GE3 1N
47P_0402_50V8J
VGA@N15@
2
PR8208 0.33UH_PCMC063T-R33MN_20A_20%
PT8209
330U_2.5V_M
0_0402_5% 1
5
RT8812AGQW-GP VGA@ VGA@
2
VGA@ PU8207 PU8209 +
OPS
1
VGA@N15@ 3V3_AON_S0
PC8223
VGA@
@EMI@ PR8215
5600P_0402_50V7K 2
2
4.7_0805_5%
C
2
PWR_VGA_CORE_RGND 4 4
VGA@ PWR_VGA_SNUB2
1
PR8258
2
10K_0402_1%
@EMI@ PC8218
1
1
2
3
1
2
3
R4+R5 330P_0402_50V7K
N15V_GM_S
1
2 1 PWR_VGA_CORE_PSI
2
[76] VGA_CORE_PSI
VGA@N15@ PR8209
PC8204 @ PR8257 Config D
2
7.87K_0402_1% 0_0402_5%
@ PC8226
2
PR8259
0.01U_0402_50V7K
0.1U_0402_25V6
Design Current=33.5A
1
10K_0402_1%
@ 56.65A <OCP< 66.7A
1
PWR_VGA_CORE_RGND
PWR_VGA_CORE_RGND
VGA_CORE
@
1
1
PR8212 Component N15V-GM-S N15-S-GT-S
B 100_0402_1% Config D Config B B
Check
VGA@ value
3D3V_VGA_S0
2
PR8256 VGA@ 2 1
1K_0402_1% VGACORE_VDD_SENSE_1 [73] 27K 20K
1 2 PWR_VGA_CORE_EN R1 (PR8222) 64.27025.6DL
1
@ @ PR8221 64.20025.6DL
1
PC8225 VGA@ PC8222 0_0402_5% R2 (PR8206) 7.5K 20K
PC8219 47P_0402_50V8J
2
64.75015.6DL
2
64.20025.6DL
47P_0402_50V8J
0.1U_0402_25V6
2
PR8260 0 2K
R3 (PR8208)
13K_0402_1% 2 1 63.R0034.1DL
1
64.20015.6DL
1 2 VGACORE_GND_SENSE_1 [73]
[15,83] DGPU_PWR_EN @ 7.87K 18K
1
@ @ PR8220 R4+R5 (PR8209) 64.78715.6DL 64.18025.6DL
VGA@
1
PC8217 0_0402_5%
47P_0402_50V8J PR8213 C (PC8223) 5.6nF 2.7nF
2
100_0402_1% 78.56222.2FL 78.27224.2FL
For tuning VGA_CORE sequence.
2
78.56222.2FL:OBS REASON: 50V is more popular, chage to 78.56224.2FL
PR8222 VGA@N16@ PR8206 VGA@N16@ PR8208 VGA@N16@ PR8209 VGA@N16@ PC8223 VGA@N16@
20K_0402_1% 20K_0402_1% 2K_0402_1% 18K_0402_1% 2700P_0402_50V7K
I/P cap: 10U 25V K0805 X5R/ 78.10622.51L

Inductor:CHIP CHOKE 0.22UH PCMC104T-R22/ 1mohm/ Isat =60A rms /68.R2210.10C
O/P cap: CHIP CAP EL 330U 2.5V M6.3*4.4 Chemi-con/79.3371V.6CL
H/S: SIRA14DP-T1-GE3 / 6.8mohm/8.5mOhm@4.5Vgs/ 84.A14DP.037
L/S:SIRA06DP-T1-GE3 / 2.75mohm/3.5mOhm@4.5Vgs/ 84.SRA06.037
A A

RT8812_VGACORE
A00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU

3D3V_VGA_S0
1D05V_VGA_S0
3D3V_VGA_S0 should ramp-up before VGA_Core
VGA_Core should ramp-up before 1D5V_VGA_S0
1D35V_VGA_S0 should ramp-up before 1D05V_VGA_S0
3D3V_VGA_S0
D D
3D3V_S0 to 3D3V_VGA_S0
1D05V_S0 to 1D05V_VGA_S0 VGA_CORE&1D05V_VGA_S0 Discharge Circuit
1
1D05V_S0
PR8301 1D05V_VGA_S0
1KR2J-1-GP U8301 Combine PG8313,PG8314,PG8315 to PG8313
GC6_20 1 13 PG8313 VGA_CORE
2
R8313 2 VIN1#1 VOUT1#13 14 1D05V_VGA_OUT2 1 2
1 2 1D05V_VGA_EN VIN1#2 VOUT1#14
<15,24,82,83> DGPU_PWROK
1
GC6@ 6 8 3V3_AON_S0 GAP-CLOSE-PWR
3D3V_S0 VIN2#6 VOUT2#8 3D3V_AUX_S5
0R2J-2-GP 7 9 PG8312 PR8317
VIN2#7 VOUT2#9 3D3V_VGA_OUT1 1 2 1D05V_VGA_S0 10R2J-2-GP
NON_GC6 2
12
@
1 OPS
C8309 5V_S0
4 OPS
SS1 10
VTT_CT_105VC_2
VTT_CT_3VC_1 GAP-CLOSE-PWR OPS2 DGPU_PWR_EN#
2
NOGC6@ VBIAS SS2
SCD1U16V2KX-3GP C8305 C8316 C8308 PR8313 D G S
1
1
@ C8307 OPS 100KR2J-1-GP
DY
SC470P50V2KX-3GP
SC2200P50V2KX-2GP
SC10U10V5KX-2GP
1D05V_VGA_EN 3 11 OPS OPS DY VGA_CORE_DISCHG DIS@
SCD1U16V2KX-3GP
EN1 GND DIS@
1
5 15
2
<15,82,83> DGPU_PWR_EN EN2 GND DIS@ PQ8305
@ OPS 10R2J-2-GP
EM5209VF DFN 14P DUAL LOAD SW
2N7002KDW-GP
OPS PR8316
1
1
DY C8302 DY C8304 DIS@
2
1
2
C8310 2nd = 84.2N702.E3F PQ8307
SC1U10V2KX-1GP
SC1U10V2KX-1GP
1
SC10U10V5KX-2GP
DY C8306 OPS 3rd = 75.00601.07C S G D 2N7002K_SOT23-3
2
2
DIS@ D
SCD1U16V2KX-3GP
2
1
4th = 84.DMN66.03F DGPU_PWR_EN# 2
@ G
X01_0721 DIS@
DIS@
DIS@ S
1D05V_VGA_S0_DISCHG OPS
3
<15,82,83> DGPU_PWR_EN DIS@
3D3V_S0 3D3V_VGA_S0
@ @ Q8302
C Cold Boot/Optimus: 3V3_AON&3V3_MAIN==>NVDD&PEX_1.05V==>FBVDD/Q NTK3139PT1G_SOT723-3 @ C
GC6 2.0 Exit: 3.3V_MAIN==>NVDD&PEX1.05V 3
GC6@ DIS@
D
1
GC6@ C8311
1
GC6_20 GC6_20
G
2
1
R8302
SCD1U16V2KX-3GP
1
3V3_AON_S0 10KR2J-3-GP C8301
GC6_20
2
R8303
2
R8315 0R2J-2-GP SCD1U16V2KX-3GP
2
1 2 1 2 GPIO5_GC6_PWR_EN_R# 3V3_AON_S0 3D3V_VGA_S0
GC6_20 DY
DY 0R2J-2-GP
GPIO5_GC6_PWR_EN#
GC6@
3V3_MAIN_EN is an open-drain GPIO. GC6@
<76> GPIO5_GC6_PWR_EN @ GC6@ @
R8304
1
R8301 GC6_20 1 2
100KR2J-1-GPDY 2 GC6@
G
0R5J-5-GP
NON_GC6
2
Could also be used for tuning sequence. 3 1

S
@ GT: R8303 = 0 ohm (63.R0034.1DL); C8301 = 0.01u (78.10324.2FL) NOGC6@

Q8301
2N7002K_SOT23-3
B
1D35V_VGA_S0 SIRA06DP-T1-GE3
1.35V +/- 3%. B
Id=10A, Qg=22.5~34nC 1D35V_S3 5.6A 1D35V_VGA_S0

Rdson=2.75~3.5m ohm
PQ8308
3
2
5 1
1
PC8307
1
SC10U6D3V3MX-GP
PC8303 OPS OPS
4
SC10U6D3V3MX-GP SIRA06DP-T1-GE_POWERPAKSO-8-5
2
DIS@
DIS@
DIS@
3D3V_AUX_KBC 1D35V_ENABLE_RC
1
DY 2
R8314
1 OPS 2
1D35V_VGA_EN#
1D35V_VGA_S0
PR8314 220KR2J-L2-GP
Discharge Circuit
1
100KR2J-1-GP PC8302 OPS

3D3V_AUX_S5 SCD01U50V2KX-1GP DIS@
1
@ OPS OPS
2
1 2
10R2J-2-GP
PR8311 D G S DIS@ PR8315
100KR2J-1-GP
2
OPS
6
DIS@ DIS_1D35V_VGA_S0
PQ8304 15V_S5 DCBATOUT DIS@
2N7002KDW-GP
OPS
1
A
2nd = 84.2N702.E3F DIS@ A
S G D PR8312 D
3rd = 75.00601.07C 2
D8301 DY PR8310 1MR2J-1-GP 1D35V_VGA_EN#
2 4th = 84.DMN66.03F 100KR2J-1-GP OPS G
<20,24,75,76> GC6_FB_EN PQ8306 S
1
1 1D35V_VGA_EN
3
2N7002K_SOT23-3
3 @ 1D35V_ENABLE DIS@
<15,24,82,83> DGPU_PWROK DIS@
BAT54C-7-F_SOT23-3
GC6@ Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 2015/01/20 2015/12/31 Title
R8312
Issued Date Deciphered Date
0R2J-2-GP 1 2
DISCRETE VGA POWER
NON_GC6 R8305 GC6_20 Size Document Number Rev
1MR2J-1-GP A00
NOGC6@
GC6@
LA-B483P
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Reserved
A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = UnusedParts

HCPU1 HCPU2 HCPU3 DAX10
H_3P7 H_3P7 H_3P4
H1 H2 H3 H4 H5 H6 H7 R3
H_3P2 H_3P0 H_3P0 H_3P0 H_3P0 H_3P2 H_3P0
@ @ @ PCB AAL10 LAB843P LS-B843P/B844P/B845P/B915P GOLD A31 !
1
D @ @ @ @ @ @ @ DAZ1AO00101 D
1
1
HGPU3 HGPU2 HGPU1
H_3P3 H_3P3 H_3P3 SPR1 SPR2 SPR3
SPRING-31-GP SPRING-24-GP-U SPRING-13-GP-U
H8 H9 @ @ @
H_4P0N H_3P0X3P8N
@ @ @ @ @
1
1
1
FD1 FD2 FD3 FD4 FD5 FD6
@ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL
1
C C
Main Func = EMICapacitors

AUD_AGND
1D35V_VGA_S0
Mind the voltage rating of the caps. EC9727 EC9725 EC9726 EC9730 EC9728 EC9729 EC9731 EC9739 EC9744 EC9743 EC9745
1
DCBATOUT DY DY DY DY DY DY DY DY DY DY DY
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1KP50V2KX-1GP
2
2
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
EC9709 EC9710
1
EC9701 EC9702 EC9703 EC9704 EC9708 EC9705 EC9706 EC9707

SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
DY DY DY DY DY DY DY
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
2
DCBATOUT 1D35V_VGA_S0
EC9740 EC9742 EC9748 EC9749 EC9746 EC9750 EC9751 EC9752 EC9753 EC9754
1
EC9711 EC9714 EC9741 DY EC9747
SCD1U25V2KX-GP
1
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
EC9717 EC9712 EC9713 EC9716 EC9715 DY DY DY DY DY DY DY DY DY
SCD1U25V2KX-GP
B B
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
DY DY
SCD1U25V2KX-GP
SCD1U25V2KX-GP
2
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
2
VGA_CORE
EC9755 EC9756 EC9757 3D3V_S0 5V_S5

1
5V_S0
DY DY DY EC9737 EC9735 EC9736 EC9738 EC9734 EC9732 EC9733
2
1
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
EC9720 EC9719 EC9718 EC9723 EC9721 EC9722 EC9724

1
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
2
2
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
2
BT+
A EC9758 EC9759 EC9760 EC9761 A

1
DY DY DY DY
2
2
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP

UNUSED PARTS/EMI Capacitors
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
D D
C (Blanking) C
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A

Reserved
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Main Func = Debug

CPU XDP
D D
CFG[19:0]
<6> CFG[19:0]
XDP_BPM[7:0]
<4> XDP_BPM[7:0]
XDP_PREQ# 1 TP9601 TPAD14-OP-GP
<4> XDP_PREQ#
<4> XDP_PRDY# XDP_PRDY# 1 TP9602 TPAD14-OP-GP

<4> XDP_TDO XDP_TDO 1 TP9624 TPAD14-OP-GP
<4> XDP_TRST# XDP_TRST# 1 TP9621 TPAD14-OP-GP
<4> XDP_TDI XDP_TDI 1 TP9623 TPAD14-OP-GP
XDP_TMS 1 TP9611 TPAD14-OP-GP
<4> XDP_TMS
XDP_BPM0 1 TP9612 TPAD14-OP-GP
<7> H_VCCST_PWRGD R9601 1 DY 2 1KR2J-1-GP VCCST_PWRGD_XDP 1 TP9648 TPAD14-OP-GP XDP_BPM3 1 TP9615 TPAD14-OP-GP
R9603 1 2 0R2J-2-GP BP_PWRGD_RST# 1 TP9645 TPAD14-OP-GP XDP_BPM4 1 TP9616 TPAD14-OP-GP
<17,24> PM_PWRBTN# DY XDP_BPM5 1 TP9617 TPAD14-OP-GP
C R9604 1 2 0R2J-2-GP XDP_PWR_DEBUG 1 TP9647 TPAD14-OP-GP XDP_BPM6 1 TP9618 TPAD14-OP-GP C
<7> PWR_DEBUG R9605 1 DY 2 0R2J-2-GP XDP_SYS_PWROK 1 TP9644 TPAD14-OP-GP XDP_BPM7 1 TP9619 TPAD14-OP-GP
<17,24> SYS_PWROK DY
@ RE117 1 0_0402_5%
2 XDP_SMBDAT 1 TP9646 TPAD14-OP-GP
<12,13,18,55,62> PCH_SMBDATA
@ RE118 1 0_0402_5%
2 XDP_SMBCLK 1 TP9649 TPAD14-OP-GP CFG0 1 TP9626 TPAD14-OP-GP
<12,13,18,55,62> PCH_SMBCLK
CFG1 1 TP9627 TPAD14-OP-GP
<4> XDP_TCLK XDP_TCLK 1 TP9650 TPAD14-OP-GP CFG2 1 TP9620 TPAD14-OP-GP
<18> PCIE_CLK_XDP_P PCIE_CLK_XDP_P 1 TP9652 TPAD14-OP-GP CFG5 1 TP9631 TPAD14-OP-GP
<18> PCIE_CLK_XDP_N PCIE_CLK_XDP_N 1 TP9651 TPAD14-OP-GP CFG6 1 TP9629 TPAD14-OP-GP
R9602 2 10R2J-2-GP XDP_RST 1 TP9654 TPAD14-OP-GP CFG17 1 TP9634 TPAD14-OP-GP
<17,24,30,36,52,58,65,73> PLT_RST# DY XDP_DBRESET# 1 TP9653 TPAD14-OP-GP CFG16 1 TP9635 TPAD14-OP-GP
<17> XDP_DBRESET# C9602 CFG8 1 TP9633 TPAD14-OP-GP
1
DY CFG9 1 TP9632 TPAD14-OP-GP

SCD1U16V2KX-3GP

2

B CFG12 1 TP9640 TPAD14-OP-GP B
A A

CPU_XDP;PCH_XDP
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
CLK Block Diagram
Intel CPU
Haswell/Broadwell ULT
M_A_DIMA_CLK_DDR0
CK0 SA_CLK0
M_A_DIMA_CLK_DDR#0
D CK0# SA_CLK#0
D
DDR3L DIMM1
M_A_DIMA_CLK_DDR1
CK1 SA_CLK1
M_A_DIMA_CLK_DDR#1
CK1# SA_CLK#1
CLK_PCIE_WLAN_P3
M_B_DIMB_CLK_DDR0 CLKOUT_PCIE_P2 REFCLKP0
CK0 SB_CLK0 WLAN
M_B_DIMB_CLK_DDR#0 CLK_PCIE_WLAN_N3
CK0# SB_CLK#0 CLKOUT_PCIE_N2 REFCLKN0 NGFF
DDR3L DIMM2
M_B_DIMB_CLK_DDR1
CK1 SB_CLK1
M_B_DIMB_CLK_DDR#1
CK1# SB_CLK#1
LAN
Co-lay CLK_PCIE_LAN_P4
RTL8106E/RTL8111G
CLKOUT_PCIE_P3 REFCLK_P
VRAM6
VRAM5
VRAM2
VRAM1
CLK_PCIE_LAN_N4
CLKOUT_PCIE_N3 REFCLK_N
C VGA C
N15V-GM-S-A2
LANXIN
GB2-64 (23x23) CKXTAL1
CK#
CK
CK#
CK
CK#
CK
CK#
CK
4 pcs VRAM PEX_REFCLK# CLK_PCIE_VGA#

CLKOUT_PCIE_N4
CLK_PCIE_VGA X3001
PEX_REFCLK CLKOUT_PCIE_P4 25MHz
FBA_CLK0N
FBA_CLK0P
FBA_CLK0N
FBA_CLK0P
FBA_CLK0N
FBA_CLK0P
FBA_CLK0N
FBA_CLK0P
N15S-GT for Vostro LANXOUT

CKXTAL2
8 pcs VRAM
‧‧ ‧‧ ‧‧
FBA_CLK0P 27MHZ_IN
FBA_CLK0 XTAL_IN
FBA_CLK0N
FBA_CLK0#
X7601
‧‧ ‧‧ ‧‧
27MHz
FBA_CLK1P
FBA_CLK1
FBA_CLK1N
FBA_CLK1# XTAL_OUT
Audio
27MHZ_OUT
Realtek
FBA_CLK1N
FBA_CLK1P
FBA_CLK1N
FBA_CLK1P
FBA_CLK1N
FBA_CLK1P
FBA_CLK1N
FBA_CLK1P
R1907
HDA_BITCLK HDA_CODEC_BITCLK
HDA_BCLK/I2S0_SCLK BITCLK ALC3224
33R2J-2-GP
B RTC_X1
RTCX1 B
CK#
CK
CK#
CK
CK#
CK
CK#
CK
X1901
KBC
VRAM8
VRAM7
VRAM4
VRAM3
32.768KHz
RTC_X2
NPCE285P
RTCX2 SUS_CLK_PCH R1710 SUS_CLK R2441 SUSCLK_KBC
SUSCLK/GPIO62 GPIO0/EXTCLK/F_SDIO3
XTAL24_IN 0R2J-2-GP 0R2J-2-GP
CLK_PCI_KBC_R R1805 CLK_PCI_KBC
XTAL24_IN CLKOUT_LPC_1 LCLK/GPIOF5
33R2J-2-GP
X1801
24MHz
CLK_PCI_LPC_R R1804 CLK_PCI_LPC
CLKOUT_LPC_0
XTAL24_OUT
33R2J-2-GP LPC
XTAL24_OUT
CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P
Test Point
A A

CLK Block Diagram
A00
5 4 3 2 1
5 4 3 2 1
Change notes -
DATE VERSON DATE Page Modify List OWNER
D D
C C
B B
A A

Change History
A00
LA-B483P
5 4 3 2 1
5 4 3 2 1
Shark Bay Platform Power Sequence (DC mode) Red Words: Controlled by EC GPIO
+RTC_VCC t01 >9ms Wistron SHARK BAY POWER UP SEQUENCE DIAGRAM

RTC_RST#
DCBATOUT
3D3V_AUX_S5
Sense the power button status Press Power button

KBC_PWRBTN# Platform to KBC PSL_IN2 DC 3
BT+ SWITCH
Battery PM_SLP_S4#
PSL_OUT#(GPIO71) keep low Page44
Page43
3D3V_AUX_KBC
KBC GPIO34 control power on by 3V_5V_EN -7 -3 DCBATOUT
S5_ENABLE
AC +DC_IN SWITCH DCBATOUT
5V_S5 Adapter in S5_ENABLE 3a
5V_S5 & 3D3V_S5 need meet 0.7V difference Page44 4a
V5REF_Sus must be powered up before Page42 VIN 1D35V_S3
VccSus3_3, or after VccSus3_3 within 3D3V_S5 SW
0.7 V. Also, V5REF_Sus must power 5V_S5 & 3D3V_S5 need meet 0.7V difference VIN 1D05V_S0
D down after VccSus3_3, or before AD+ SW D
+5VA_PCH_VCC5REFSUS Ta
VccSus3_3 within 0.7 V.
4 TPS51367
EN1 EN2 RUNPWROK
KBC GPIO43 to PCH -5 3D3V_S5 TPS51367 EN PGOOD
PM_RSMRST#(RSMRST#_RST) t05 >10ms PM_SLP_S3# RUNPWROK Page48
t07 >100ms PCH to KBC GPIO00 Charger EN PGOOD
In case of a non-Deep S4/S5 Platform DCBATOUT TPS51225CRUKR Page48 4b
timing t42 should be added to t07 PCH_SUSCLK_KBC BQ24715 VIN
which will make it 100mS minimum. DC/DC -2 4b
KBC GPIO20 to PCH (3.3V/5V) 5V_S5
ACOK Page44 1D35V_S3
PM_PWRBTN#
Page41
3D3V_AUX_S5 RUNPWROK 5V_S0

4 SWITCH
Page36
DDR_VTT_PG_CTRL
TPS51206 0D675V_S0
-4 SWITCH
DC PM_PWRBTN#
After Power Button Page24 Page46
RUNPWROK 3D3V_S0
-6 SWITCH
PCH to KBC GPIO44 3D3V_AUX_KBC -3 4b Page36
5
PM_SLP_S4#
t10 PCH to KBC GPIO01 AC_IN S5_ENABLE 7
PSL_IN1# GPIO34
PM_SLP_S3# >30us
DDR_PG_CTL RUNPWROK Level H_VCCST_PWRGD
KBC GPIO47 to LAN H_VR_ENABLE
PM_LAN_ENABLE 1 VR_EN
Shifter
Enable by PM_SLP_S4# Page7
KBC_PWRBTN#
1D5V_S3 PSL_IN2# KBC -1 DPWROK H_CPU_SVIDDAT
VIDSOUT
DDR_VREF_S3(0.75V) PM_SLP_S4#
NPCE985 GPIO43
RSMRST#_KBC
RSMRST# Haswell ULT CPU
5V_S0 & 3D3V_S0 need meet 0.7V difference GPIO8 PM_PWRBTN# 11
5V_S0
PM_SLP_S3#
GPIO01
GPIO20 PWRBTN# with
3D3V_S5
V5REF must be powered up before 3D3V_S0 GPIO80 2 Lynx Point PCH
Vcc3_3, or after Vcc3_3 within 0.7
V. Also, V5REF must power down Page24 12 4a
after Vcc3_3, or before Vcc3_3 +5VS_PCH_VCC5REF Tb
within 0.7 V. SLP_S3# de-assert, delay 20ms; APWROK PCI_PLTRST# 4 VIN 1D5V_S0
PLTRST# VOUT
1D5V_S0 PCH_PWROK assert.
10 S0_PWR_GOOD
6 PCH_PWROK VCCST_PWRGD SYS_PWROK VR_READY PM_SLP_S3# TPS51312 RUNPWROK
1D8V_S0 SLP_S3# de-assert, delay 200ms; EN PGOOD
S0_PWR_GOOD assert. Page51
0D75V_S0 5 4b
1D8V_S0 & 1D5V_S3 power ready
RUNPWROK PCH_PWROK H_VCCST_PWRGD
1D05V_PCH
SYS_PWROK be asserted after S0_PWR_GOOD
VCCP_CPU assertion and CPU core VR power good
assertion.
1D05_VTT_PWRGD 11
S0_PWR_GOOD
H_CPU_SVIDDAT
0D85V_S0 VDIO
TPS51622 9
7 H_VR_ENABLE IMVP_PWRGD
VR_ON PGOOD
0D85V_S0
D85V_PWRGD Page46
C C
CPU SVID BUS SetVID ACK 50us< t36 <2000us PWR_VCC_PWM1

VCC_CORE
DCBATOUT 8
VCC_GFXCORE
CSD97374
t37 VCC_CORE
VSW
<5ms Page47
IMVP_PWRGD
PCH_CLOCK_OUT
ALL_SYS_PWRGD=D85V_PWRGD t14 >99ms KBC GPIO77 to PCH

This signal represents the Power
Good for all the non-CORE and PWROK(S0_PWR_GOOD)
non-graphics power rails.
t18
D85V_PWRGD >0us PCH to CPU
DRAMPWROK(VDDPWRGOOD) 2ms<t17 <650ms 1 2 3a 4 4a 4b 5 6 7 8 9 10 11 12
t19 >1ms
1D8V_S0
t20 >2ms
5ms<t13 <650ms PCH to CPU
UNCOREPWRGOOD(H_CPUPWRGD)
SYS_PWROK t21+t22 >1ms+60us

1ms< t25 <100ms PCH to all system
N14P-GT Power-Up/Down Sequence PLT_RST#
t39 <200us
DMI
3D3V_S0
PCH GPIO54 output
DGPU_PWR_EN#(Discrete only)
3D3V_VGA_S0(VDD33)
8209A_EN/DEM_VGA(Discrete only)
VGA_CORE(NVVDD) tNVVDD >0ms

RT8208 PGOOD
DGPU_PWROK(Discrete only)
1D5V_VGA_S0(FBVDDQ) tNV-FBVDDQ >0ms
1D05V_VGA_S0(PEX_VDD) tNV-PEX_VDD >0ms
First rail to power down VGA_CORE,1D05V_VGA_S0

1D5V_VGA_S0,3D3V_VGA_S0
Last rail to power down
tPOWER-OFF <10ms
B B
For power-down, reversing the ramp-up sequence is recommended.
A A

Power Sequence
Size Docum ent Num ber Rev
A00
LA-B483P
Date: Wednes day, January 21, 2015 Sheet 99 of 102
5 4 3 2 1
5 4 3 2 1
DCBATOUT
Adapter
RT8237 TPS51216RUKR ISL95813 AP3211
D D
Charger
1D05V_S0
BQ24717
1D35V_S3 0D675V_S0 VCC_CORE VGA_CORE
Battery +PBATT
TPS22966 TLV70215 SIRA06DP
1D05V_VGA_S0 1D5V_S0 1D35V_VGA_S0
C C
TPS51125ARGER
15V_S5 3D3V_AUX_S5 5V_AUX_S5 5V_S5 3D3V_S5
TPS22966
AP2182SG AP2301M8G TPS22966 AO3403
TLV70215
3D3V_S0
USB30_VCCA +5V_USB1 5V_S0 3D3V_LAN_S5
USB30_VCCB 1D5V_S0
B B
SY6288
ODD_PWR_5V
RT9724 TPS22966
Power Shape
LCDVDD 3D3V_VGA_S0
Regulator LDO Switch
A A

Power Block Diagram
A00
LA-B483P
5 4 3 2 1
A B C D E
PCH SMBus Block Diagram KBC SMBus Block Diagram

3D3V_S5_PCH 3D3V_S0
‧ ‧ TP_VDD
3D3V_S0 ‧
SRN2K2J-1-GP
‧ SRN10KJ-5-GP
RN6201
DIMM 1
‧ ‧
Q1801 SRN10KJ-5-GP
‧ ‧
SMBCLK SMB_CLK PCH_SMBCLK
1
TouchPad Conn. 1
‧
SCL
SMBDATA SMB_DATA PCH_SMBDATA 100R2J-2-GP
‧
SDA PSDAT1 TPDATA TPDATA_C TPDATA
PSCLK1 TPCLK TPCLK_C TPCLK

SMBus Address:0xA0/0xA1
2N7002KDW-GP 100R2J-2-GP
3D3V_AUX_KBC
DIMM 2
PCH_SMBCLK
PCH_SMBDATA
SCL
SDA
‧
3D3V_S5_PCH
SMBus Address:
‧
SRN4K7J-8-GP
Battery Conn.
TPAD ‧‧ 100R2J-2-GP
‧ ‧
GPIO17/SCL1 BAT_SCL PBAT_SMBCLK1 CLK_SMB
PCH_SMBCLK
SRN2K2J-4-GP
SCL
GPIO22/SDA1 BAT_SDA PBAT_SMBDAT1 DAT_SMB SMBus address:16
PCH_SMBDATA
SDA 100R2J-2-GP
SML0CLK SML0_CLK SMBus Address:0x58/0x59

SML0DATA SML0_DATA BQ24770RUYR
RTD2168 KBC SCL
SDA SMBus address:12

PCH_SMBCLK
PCH_SMBDATA
VDDA33_DP
TMS (Tulip Only) NPCE285P

2
SMBus Address:0xC0H/0x40H 2
GPIO73/SCL2/N2TCK
GPIO74/SDA2/N2TMS
PCH 3D3V_S0 SMBus Address:
‧
0x94/0x95/0x96/0x97
3D3V_S0
‧ SRN2K2J-8-GP
‧ ‧ ‧
Q2601
Thermal
‧ ‧ ‧
SML1_CLK THM_SML1_CLK
SCL
SML1CLK
SML1_DATA THM_SML1_DATA
SML1DATA SDL
NCT7718W
SMBus Address:0x82/0x83 SMBus Address:0x98/0x99
2N7002KDW-GP
3D3V_VGA_S0
‧ SRN4K7J-8-GP
3D3V_VGA_S0
‧ dGPU
3 3
‧
Q7601
‧ SMBus Address:0x9E/0x9F
SMBC_Therm_NV I2CS_SCL
SMBD_Therm_NV I2CS_SDA
2N7002KDW-GP
3D3V_S0 5V_S0
‧ ‧ 0R2J-2-GP
DY
‧
3D3V_S0
SRN2K2J-1-GP
‧ SRN2K2J-1-GP GPIO47/SCL4A
GPIO53/SDA4A
PROCHOT_EC
LCD_TST_EN
‧ LCD_TST_EN
‧ H_PROCHOT#_EC
‧ ‧ 0R2J-2-GP
‧ ‧‧ ‧
DDPB_CTRLCLK PCH_HDMI_CLK DDC_CLK_HDMI
LCD_TST
DDPB_CTRLDATA PCH_HDMI_DATA DDC_DATA_HDMI
HDMI CONN
2N7002DW-1-GP
4 4

SMBUS Block Diagram
A00
A B C D E
A B C D E
Thermal Block Diagram Audio Block Diagram

1 1
3D3V_S5_PCH 3D3V_S0
PAGE26 D+ NCT7718_DXP
PCH LMBT3904LT1G-GP
SPKR_L+
SPKR_L-
D- NCT7718_DXN
SC2200P50V2KX-2GP SPKR_R-
SPKR_R+ SPEAKER
Thermal Place near CPU
NCT7718W
‧ ‧‧ ‧
PWM CORE
SML1DATA/GPIO74
SML1_DATA THM_SML1_DATA SDA
Codec
‧‧ ‧ ‧
2N7002
SML1CLK/GPIO75 SML1_CLK THM_SML1_CLK SCL
MMBT3904-3-GP
ALC3224
T8 AUD_HP1_JACK_L HP MIC
SML1_DATA
AUD_HP1_JACK_R
SML1_CLK
3D3V_S0
T_CRIT# THERM_SYS_SHDN#
2N7002
D
PURE_HW_SHUTDOWN#
EN 3V/5V SLEEVE Universal
‧
PAGE18 S PCH_PWROK
G RING2
2
Put under CPU(T8 HW shutdown) AUD_SENSE
2
JACK_PLUG_DET
PAGE24 GPIO74 PAGE76
KBC GPIO73
NPCE285P 2N7002
SMBD_THERM_NV I2CS_SCL
VGA
SMBC_THERM_NV I2CS_SDA
GPIO4
N15V-GM-S-A2 DMIC_DATA_R R2714 DMIC_DATA
RN5204
Digital
GPIO0/DMIC_DATA
GPIO94 GPIO56
GB2-64 (23x23) DMIC_CLK_R
0R2J-2-GP
R2716 MIC
GPIO1/DMIC_CLK DMIC_CLK SRN33J-5-GP-U
FAN_TACH1
FAN1_DAC_1
0R2J-2-GP
3 3
TACH
FAN
VIN
FAN_VCC1
5V
VIN VSET VOUT
FAN CONTROL
AP2113MTR
PAGE26
4 4

Thermal/Audio Block Diagram
A00
A B C D E

La B843P

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5 4 3 2 1

Iris HSW/BDW Schematics

UMA: UMA only installed

PCB P/N: 14216 SYSTEM DC/DC

73,74,75,76,77 28W (UMA) DDR3L DDR3L SUS

DP/VGA Converter WPT-LP 0D675V_S0

LPC BUS 3D3V_S5 3D3V_S0

IO Board USB3(USB2.0) USB2.0 x 1

USB1(USB3.0) SATA(Gen1) x 1 ODD

CardReader Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

Main Func = CPU

XDP_TRST# EC402 1 2 SCD1U16V2KX-3GP SRN51J-1-GP @

TP402 PREQ# E60 XDP_TCLK

Security Classification Compal Secret Data Compal Electronics, Inc.

Main Func = CPU

DDR3L ball type: Non-Interleaved Type

M_A_DQ[63:0] CPU1D HSW_ULT_DDR3L 4 OF 19

CPU1 4030@ CPU1 BDW_PQS@

CL8064701552900 SR1EN D0 1.9G A31! FH8065801620003 QH15 E0 2.2G

FH8065801882800 SR215 E0 1.5G FCBGA FH8065801884006 SR244 F0 2G FCBGA

FH8065801620204 SR23Y F0 2.2G FCBGA

Main Func = CPU

#514405 PCH strap pin:

PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

DISPLAY PORT PRESENCE STRAP

Security Classification Compal Secret Data Compal Electronics, Inc.

Main Func = CPU

<48> H_VR_ENABLE F60 F52

1 RSVDP60 P60 VSS VCC G31

2 AD59 RSVD#AD60 VCC G43

74LVC1G07GW -GP U59 G53

@EMI@ 1D05V_S0 1D05S_VCCST RSVD#V59 VCC G57

R711 AC22 VCC H23

<24,48> IMVP_PW RGD 1 2 IMVP_PW RGD_R

Security Classification Compal Secret Data Compal Electronics, Inc.

<54,55> HDMI_CRT_N0 C54 C45

Security Classification Compal Secret Data Compal Electronics, Inc.

Main Func = CPU

Main Func = CPU

Main Func = CPU

1.838A 41mA 42mA

57mA 62mA 185mA

1D05V_S0 +V1.05S_APLLOPI 1D05V_S0 +V1.05S_AXCK_DCB

31mA 658mA 1.632A 1mA

1D05V_S0 +1.05M_ASW 1D05V_S0 +V1.05S_CORE_PCH

Security Classification Compal Secret Data Compal Electronics, Inc.

Main Func = DIMM1

M_A_DQ27 34 DQ13 197 SA0_DIMA C1210

M_A_DQ6 143 117

M_A_DQ4 132 DQ36 VDD16 123

M_A_DQ3 140 DQ37 VDD17 124

M_A_DQ38 177 DQ50 VSS 32 1D35V_S3

M_A_DQ39 176 DQ54 VSS 44 Q1202

Security Classification Compal Secret Data Compal Electronics, Inc.

Main Func = DIMM2

M_B_DQ29 23 DQ8 SCL

M_B_DQ25 22 DQ11 199

M_B_DQ1 131 111

M_B_DQ7 143 DQ34 VDD14 117

M_B_DQ5 130 DQ35 VDD15 118

M_B_DQ52 181 DQ55 VSS 48

spacing=20 mil 204 206