Design Considerations for Designing with Cree

SiC Modules Part 2. Techniques for Minimizing

Parasitic Inductance

Design Considerations for Designing with Cree SiC Modules

Part 2. Techniques for Minimizing Parasitic Inductance

Scope:
This application guide shows techniques to minimize parasitic inductance in printed circuit boards to
maximize the benefits of SiC (silicon carbide) modules. Cree’s CAS100H12AM1 1.2kV, 100A 50mm half-
bridge module and Cree’s CCS050M12CM2 1.2kV, 50A six-pack module are used as examples.

Introduction:

Cree SiC MOSFET modules provide a unique combination of high voltage, high current and high switching
speed. This combination requires careful consideration of circuit parasitic elements, beyond what is
customary when using conventional Si IGBT modules. The effects of circuit parasitics were previously
discussed in “Minimizing Parasitic Effects in SiC MOSFET Modules,” and this application note will provide
guidance on minimizing these parasitic elements.

Parasitic inductance in the link capacitor bank and its interface to the SiC module is the primary concern.
Design recommendations begin with a theoretical discussion of the sources of parasitic inductance, and
include recommendations on interconnect layout, as well as suggestions for capacitor selection from both
a performance and economic perspective. Two designs using these guidelines are presented, along with
measured parasitic inductance. The two designs are the capacitor board circuits used to gather switching
data on Cree’s CAS100H12AM1 1.2kV, 100A 50mm half-bridge module and Cree’s CCS050M12CM2 1.2kV,
50A six-pack module.

Discussion:

This discussion takes an intuitive approach to minimization of parasitic inductance in the link capacitor bank
and its interface to the SiC power module. While it is possible to fully model all parasitics via finite element
techniques, this approach is complex and time consuming. The following points will be discussed:

• Parasitic Considerations – brief discussion of the electromagnetic principles involved along with conductor
geometry recommendations.
• Component Selection – first order trade-off concerning link capacitor selection from a parasitic
inductance and economic perspective.
• Cree 50mm Half-Bridge Capacitor Board Design and Results – an example demonstrating a low
inductance link capacitor bank for half-bridge modules.
ance

• Cree Six-Pack Module Capacitor Board Design and Results – a second example demonstrating a low
inductance link capacitor bank for six pack modules.
rasitic Induct
r Minimizing Pa
REV –
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CPWR-AN13,
Te ch niqu es

Subject to change without notice.

1
www.cree.com
 Parasitic
Parasitic Considerations:
Considerations:
Parasitic Considerations:
Inductance
Inductance is
is based
based on
on two
two fundamental
fundamental discoveries
discoveries in
in physics.
physics. First,
First, Oerstead
Oerstead discovered
discovered the
the
force
force between
Inductancebetween
is based two
twooncharge
charge objects
objects depended
two fundamentaldepended on
on the
discoveries the rate
rate of
of flow
in physics. flow of charge
charge (i.e.
ofOerstead
First, (i.e. current).
current).theAmpere
discovered Ampere
force
measuredtwo the
chargeforce caused
objects by the
depended current
on the and
rate expressed
of flow of this
charge relationship
(i.e. in
measured the force caused by the current and expressed this relationship in equation form.
between current). equation
Ampere form.
measured the
The ‘force at a distance’ was the effect of the magnetic field. Ampere’s law in vector
The ‘force at a distance’ was the effect of the magnetic field. Ampere’s law in vector notation is was
force caused by the current and expressed this relationship in equation form. The ‘force notation
at a is
distance’
theas follows
aseffect
follows (bold
(bold
of the are
are vector
field.quantities):
vector
magnetic quantities):
Ampere’s law in vector notation is as follows (bold are vector quantities):

∇×𝑩𝑩
∇×𝑩𝑩 =
= 𝜇𝜇  𝑱𝑱
𝜇𝜇  𝑱𝑱
This
This
This states
thatthat
states
states thethe
that curlcurl
the curl of
of the
of the the magnetic
magnetic
magnetic B is B
fieldfield
field is
is equal
Bequalequal to the
the product
to product
to the product of the
the material
of material
of the material
permeability µ and
permeability
permeability
electric µ and
current density electric
µ and electric current
J and iscurrent density
density
customarily J and is
J and is by
illustrated customarily
customarily illustrated
illustrated
the ‘right hand by the
the ‘right
by shown
rule’ as ‘right hand
hand rule’
in Figure rule’
1. From
as
Lenz’sshown
as shown in
law in in Figure
anFigure 1. From
electric1.circuit
FromwithLenz’s
Lenz’s law in
law in an
inductance an electric
electrican
changing circuit
circuit with inductance
withcurrent
electric inductance changing
changing
that has inductancean
an electric
electric
induces a
current
current
voltage
that has
has inductance
thatopposes
which inductance
the change
induces
induces a
a voltage
voltage
in current
which
which opposes
opposes
(self-inductance)
the
suchthe
change
change in
that: in current
current (self-
(self-
inductance)
inductance) such
such that:
that:
𝑑𝑑𝑑𝑑
𝑑𝑑𝑑𝑑
𝑉𝑉 = 𝐿𝐿
𝑉𝑉 = 𝐿𝐿 𝑑𝑑𝑑𝑑
𝑑𝑑𝑑𝑑
The keykey
The issue is that
issue the the
is that magnetic fieldfield
magnetic gives rise rise
gives to the
to inductance. Ampere’s
the inductance. circuital
Ampere’s law provides
circuital law a
The key issue is that the magnetic field gives rise to the inductance. Ampere’s circuital law
provides
means a
a means
of calculating
provides meanstheof
of calculating the
steady state
calculating steady
steady state
magnetic
the magnetic
field based
state field
field based
on steady
magnetic on
on steady
steady state
state current.
based state current.
current.

Electric
ElectricCurrent
Electric Current
Current

Magnetic Field
Magnetic
Magnetic Field
Field

Figure
Figure 1:
1: Right
Right hand
hand rule
rule (red
(red =
Figure
= magnetic
magnetic field,
1: Right hand rule (red blue
field, blue =
= current)
= magnetic field, blue = current)
current)

AnAn obvious method

obvious methodfor minimizing
for inductance is toiscancel the magnetic field as much as possible. Some
An obvious method for minimizing
minimizing inductance
inductance is to
to cancel
cancel the
the magnetic
magnetic field
field as
as much
much as
as
illustrations of this concept are the twisted pair conductors and coaxial cables.
possible. Some illustrations of this concept are the twisted pair conductors and coaxial cables.
possible. Some illustrations of this concept are the twisted pair conductors and coaxial cables.
There are two general ways of laying out a pair of conductors on/in a printed circuit card or bus bar. The
There
There are
are two general ways
ways of
of laying out
out a pair
pair of
of aconductors on/in a
a printed circuit
circuit card or
or bus
first way is totwo general
stack the conductors laying
vertically, aforming conductors on/in
parallel plate printed
structure as shown card
in Figurebus
2.
bar.
bar. The
The first
first way
way is
is to
to stack
stack the
the conductors
conductors vertically,
vertically, forming
forming a
a parallel
parallel plate
plate structure
structure as
as
The second way is to place the conductors side by side in the same horizontal plane, forming a coplanar
shown
shown asin
in Figure
Figure 2. The
The second
2. Figure second way is
is to
to place the
the conductors side
side by side
side in the
the same
structure shown in 3. Theway
coplanar place
conductor conductors
layout is popular by
in IGBT in
modulesame
based inverters.
horizontal
horizontal plane,
plane, forming
forming a
a coplanar
coplanar structure
structure as
as shown
shown in
in Figure
Figure 3.
3. The
The coplanar
coplanar conductor
conductor
Bolt-on connections to IGBT modules and electrolytic capacitors are simplified because both conductors are
in the same plane.

2
2

CPWR-AN13, REV – This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
2 Techniques for Minimizing information, please contact Cree Sales at PowerSales@cree.com.
Parasitic Inductance
 Figure 2: Parallel plate Figure 3: Coplanar plate

Both techniques provide lower inductance by placing the conductors in close proximity to one another and
therefore cancelling the field. The degree of cancellation can be rigorously calculated by Ampere’s law;
however, valuable insight can be gathered by considering the geometry and the subsequent magnetic field.
The best way to illustrate the geometric effects is to first consider the magnetic field created by a single
rectangular conductor as shown in Figures 4 and 5. The current flow and magnetic field lines obey the
right hand rule.

Figure 4: Rectangular foil (end view) Figure 5: Rectangular foil (side view)
  Blue dot: Current flowing out of page     Blue line: Current flow
  Red lines: Magnetic field     Red dot: Magnetic field flowing out of page
    Red cross: Magnetic field flowing into page

Now, consider the pairs of conductors with currents flowing in opposite directions. The solid red line is the
field caused by the current flowing out of the page and the dashed line is the field from the current flowing
into the page. The parallel plate case magnetic field overlap is shown in Figure 6 and the coplanar plate
case magnetic field overlap is shown in Figure 7.

Figure 6: Parallel plate overlap Figure 7: Coplanar plate overlap

This simple graphical example shows that the parallel plate structure has substantially more overlap and
therefore cancels the magnetic field better than the coplanar approach.

CPWR-AN13, REV – This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
3 Techniques for Minimizing information, please contact Cree Sales at PowerSales@cree.com.
Parasitic Inductance
 The The
The parallel
parallel
parallel plate
plate
plate and
and and coplanar
coplanar
coplanar plate
plate geometries
plategeometries are
geometries popular
areare
popular transmission
popular line formats.
transmission
transmission line
line Inductance per
formats.
formats.
unit length
Inductance
Inductance peris
pera standard
unit
unit
length
lengthparameter
is is
a standardfor transmission
a standard parameter
parameter lines.
forfor Hence, estimates
transmission
transmission lines. of Hence,
lines. inductance
Hence, per unit of
estimates
estimates length
of
for the
inductance
inductanceparallel
perper plate
unit
unit and
length
lengthcoplanar
forfor
thethe structures
parallel
parallel are
plate widely
plate
and
and available
coplanar
coplanar from several
structures
structures sources.
are
are widely The
widely free
available space
available
fromfrom
(relative permeability and permittivity equal to unity) inductance approximations for these two structures
several
several sources.The
sources.The free
free
space
space (relative
(relativepermeability
permeability andandpermittivity
permittivityequal
equal to to
unity)
unity)
inductance
inductance
are shown in Figures
approximations
approximations forfor
these8 and
these two 9.structures
two structures are
are
shown
shown in in
Figures
Figures 8 and
8 and
9. 9.

d=w+t
d=w+t
d=w+t
ww
w
tt t

h hh
w
ww

ℎℎ 𝜇𝜇 𝜇𝜇 !!!!𝑤𝑤𝑤𝑤++𝑡𝑡 𝑡𝑡
𝐿𝐿/𝑚𝑚
𝐿𝐿/𝑚𝑚≈≈𝜇𝜇 𝜇𝜇 𝐿𝐿/𝑚𝑚
𝐿𝐿/𝑚𝑚≈≈ coshcosh
𝑤𝑤𝑤𝑤 𝜋𝜋 𝜋𝜋 𝑤𝑤𝑤𝑤

Figure
Figure 8: 8:8:
Figure Parallel
Parallel
Parallel plate
plate
plate inductance
inductance
inductance approximation
approximation
approximation Figure
Figure
Figure 9: 9:
9: Coplanar
Coplanar
Coplanar plate
plate plateinductance
inductance
inductance approximation
approximation
approximation
AnAnillustration
illustration of of
thethe
difference
difference between
between thethe
twotwo
geometries
geometries cancan
bebeassessed
assessed byby
anan
example
example
An illustration of the difference between the two geometries can be assessed by an example that considers
that
thatconsiders
considers a width
a width(w)(w)
of of
20 20
mm mmfor
for
both
bothcases,
cases,
with
with
thethe
spacing
spacingsetset
to to
thethe
smallest
smallest
a width (w) of 20 mm for both cases, with the spacing set to the smallest value commensurate with an
value
value
commensurate
commensurate with
withan
operating voltage of 1.2kV.anoperating
operating voltage
voltageof of
1.2kV.
1.2kV.

For For
For the
thethe parallel
parallel
parallel plate
plate
plate case,
case,
case, aa conservative
conservative
a conservative spacing
spacing between
spacing between the the
between parallel
the conductors
parallel
parallel (h) would
conductors
conductors be
(h)(h)
would
would bebe
approximately
approximately
approximately 1/10
1/10
1/10 the
thethe short
short
short term
termterm dielectric
dielectric
dielectricstrength
strength
strengthfor FR-4.
forfor
FR-4. The
FR-4.Theshort
The term
short
short dielectric
term
term breakdown
dielectric
dielectric for
FR-4
breakdown
breakdownis approximately
forfor
FR-4
FR-4 20kV/mm,
is is
approximately
approximately giving a conservative
20kV/mm,
20kV/mm, givingoperating
giving rating
a conservative
a conservativeof 2kV/mm,
operating
operatingwhich
ratingequates
rating
of of to
0.6mmwhich
2kV/mm,
2kV/mm, spacing
which at
equates1.2kV.
equates The
to to
0.6mm inductance/mm
0.6mm spacing
spacing for
at at this geometry
1.2kV.
1.2kV. The The is a simple ratio
inductance/mm
inductance/mm and
forfor
thisinversely
this
geometry proportional
geometry is is
aa
to spacing (h). In the case where w = 20mm and h = 0.6mm, the inductance per unit length is 0.0377nH/
simple
simple ratio
ratio
andandinversely
inversely proportional
proportional to to
spacing
spacing (h).
(h).In In
thethe
case
casewhere
where ww = 20mm
= 20mm andandh =h =
mm.
0.6mm,
0.6mm, thethe
inductance
inductance per per
unitunitlength
lengthis is
0.0377nH/mm.
0.0377nH/mm.
For the coplanar plate case, the IPC-2221 Generic Standard on Printed Board Design recommends 3mm of
For
Forthethe
spacingcoplanar
coplanar plate
(t in Figureplate
9)case,
atcase,thethe
1.2kV IPC-2221
for IPC-2221
polymer Generic
orGeneric
conformalStandard
Standard
(A5/B4)on on
Printed
coatedPrintedBoard
Board
boards. InDesign
Design
this case, 3mm sets
recommends
recommends
the minimum 3mm
3mm of of
spacingspacing
t.spacing (t (t
The only inremaining
in
Figure
Figure
9)parameter
9)
at at
1.2kV
1.2kVforfor
that polymer
polymer
can oror
conformal
be adjusted conformal (A5/B4)
to minimize (A5/B4) coated
coated
the inductance/
boards.
boards.In In
mm is this
this
case,
increasing case,
the3mm3mm
width sets
w.sets thethe
The minimum
minimum spacing
inductance/mm spacing
vs. t. t.The
width wTheonly
is only
an remaining
remaining
inverse parameter
parameter
hyperbolic cosine that
that
can
functioncan
bebeand is shown
adjusted
adjusted to toinminimize
Figure 10.
minimize thethe this case whereiswis
In inductance/mm
inductance/mm =increasing
20mm and
increasing thetthe
= 3mm,
width
width w.the
w.The
inductance
The per unit length
inductance/mm
inductance/mm vs.vs.is
0.2167nH/mm.
width
width ww is is
ananinverse
inverse hyperbolic
hyperbolic cosine
cosinefunction
function and
andis is
shown
shown in in
Figure
Figure 10.10.In In
this
thiscase
case where
where
ww=The
20mm
= 20mm andandt =t 3mm,
= 3mm, thetheinductance
inductance per
per
unit
unit
length
lengthis is
0.2167nH/mm.
0.2167nH/mm.
results show that under the conditions described above, the inductance per unit length for the coplanar
arrangement is approximately 5.7 times higher than the parallel plate configuration. An obvious question
TheThe results
wouldresults
be show
howshow that
wide thatunder
the under thethe
conductors conditions
conditions
would need described
described
to be to makeabove,
above,
thethe theinductance
inductance
inductance per
per unit per unit
unit
length length
length
of thefor for
coplanar
thethecoplanar
coplanar
configuration arrangement
arrangement
equal to the is is
approximately
approximately
parallel 5.75.7
plate configuration.times
times higher
higher
This than
than
is illustrated thethe
inparallel
parallel
Figure plate
10.plate configuration.
This configuration.
graph shows
AnAn obvious
theobvious question
inductance question would
per unit would bebe
length howhow
versuswide
wide
widththethe
forconductors
conductors
the coplanarwouldwould
plate needneed to to
bebe
configuration. to The
to
make
make thethe
graph shows that the
inductance
inductance
inductance per
per
perunit
unit
length
unit length
length ofdecreases
of
thethe
coplanar
coplanar configuration
at a slow configuration equal
equal
rate with increasing towidth.
to
thetheparallel
parallel
The 20mm plate
plateconfiguration.
widthconfiguration.
case is shown
This
This
asisthe
is
illustrated
illustrated
red circlein in
Figure
and Figure 10.10.This
the 0.0377nH Thisgraph
casegraph shows
is shownshows asthethe
the inductance
inductance
green ‘X’. A per perunit
coplanarunit
length
length
plate versus
versus
conductor width
width
width for
offor
thethecoplanar
coplanar
675.5mm plate
plate
would configuration.
be configuration.
needed to achieve TheThegraph
thegraph
sameshows
shows that
inductancethat
thethe
per inductance
inductance
unit length asperperunit
the unit
20mmlength
length
wide parallel plate
decreases
decreases at at
configuration, a slow
aclearly
slowrateratewith
withincreasing
demonstrating increasing width.
width.The
the advantage The
of 20mm
the20mm width
parallel width
platecase
caseis is
shown
shown
configuration. asas thetheredred
circle
circle
andand thethe 0.0377nH
0.0377nH case
case is is
shown
shown asasthethe
green
green ‘X’.‘X’.A Acoplanar
coplanar plate
plate conductor
conductor width
width of of
675.5mm
675.5mm would
would bebeneeded
needed to to
achieve
achieve thethe
samesame inductance
inductance perperunitunit
length
length asas thethe20mm20mm wide
wide

CPWR-AN13, REV – 44
This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
4 Techniques for Minimizing information, please contact Cree Sales at PowerSales@cree.com.
Parasitic Inductance
 1
w = 20mm
w = 675.5mm

5.7x wider
nH/mm

0.2167 nH/mm
0.1

0.0377 nH/mm

0.01
1 10 100 1000
Width (mm)

Figure 10: Coplanar plate inductance/mm gap = 3mm

A summary of the key points about inductance, magnetic fields and conductor configurations are as
follows:

• Minimizing parasitic inductance, beyond minimizing the conductor length, is best achieved by cancelling
out stray magnetic fields as much as possible.
• The geometry of closely placed conductors is a significant factor in minimizing the magnetic field to
reduce inductance.
• With conductors that have a rectangular cross section, the parallel conductor (stacked) layout is superior
to a coplanar conductor (side by side) layout in minimizing parasitic inductance.

CPWR-AN13, REV – This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
5 Techniques for Minimizing information, please contact Cree Sales at PowerSales@cree.com.
Parasitic Inductance
 Component Selection:

Because it was critical to minimize the inductance from the onset, polypropylene film capacitors were
chosen because of their low loss characteristics at high frequencies. The capacitor bank required a center
tap to allow the generation of a neutral lead if needed. There are two approaches to realizing the capacitor
bank. First, and most obvious, is to use one large capacitor (actually, two tied in series to generate the
center tap). The other approach is to use a multiplicity of smaller capacitors connected in parallel. A
small generalized study was undertaken to see what approach would offer the lowest equivalent series
inductance (ESL). The capacitors chosen for the large capacitor approach is the AVX FFVS6K0147K 140µF
600V polypropylene as shown in Figure 11, which has has extremely low ESL for a capacitor in this form
factor. The capacitor chosen for each element of the parallel array approach is the Epcos B32796G3166K
16µF 700V polypropylene capacitor as shown in Figure 12.

Figure 11: AVX capacitor form factor Figure 12: Epcos capacitor form factor

The basis of the comparison was to compare the two series connected 140µF capacitors as shown with
Figure 13 with an equivalent parallel array of the 16µF capacitors as shown in Figure 14.

+LINK +LINK

140µF 600V
ESL = 11nH

MID MID

140µF 600V
ESL = 11nH

-LINK -LINK

Figure 13: Large capacitor approach

CPWR-AN13, REV – This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
6 Techniques for Minimizing information, please contact Cree Sales at PowerSales@cree.com.
Parasitic Inductance
 +LINK +LINK
Nine
16µF 700V
ESL = 30nH
in parallel
MID MID
Nine
16µF 700V
ESL = 30nH
in parallel
-LINK -LINK

Figure 14: Parallel array approach (all capacitors 16µF 700V)

A comparison of overall capacitance, voltage rating, ESL and cost are provided in Table 1. The parallel
array approach offers higher capacitance and voltage, one third the ESL and about half the cost.
Therefore, a multiplicity of capacitors offers significant advantages over few large capacitors.

Table 1: Capacitor Bank Approach Comparison

Parameter Large Capacitor Approach Parallel Array Approach
Capacitance 70µF 72µF
Voltage Rating 1.2kV 1.4kV
ESL 22nH 6.67nH
Cost (1k) $204.16 $114.48

Cree 50mm Half-Bridge Capacitor Board Design and Results:

The concept of magnetic field cancelling as a means to minimize parasitic inductance was used in the
design of a capacitor board to do dynamic evaluation of the Cree 1.2kV 100A 50mm half-bridge module.
The actual capacitor board required only 50µF of capacitance for the 50mm module double pulse tester. A
schematic of the capacitor board is shown in Figure 15.

+LINK D1

R1
220k 2W C1 C3 C5 C7 C9 C11 C13
16 uF 16 uF 16 uF 16 uF 16 uF 16 uF 8 uF
R2 700VDC 700VDC 700VDC 700VDC 700VDC 700VDC 700VDC
220k 2W
MID MID

R3
C2 C4 C6 C8 C10 C12 C14
220k 2W
16 uF 16 uF 16 uF 16 uF 16 uF 16 uF 8 uF
R4 700VDC 700VDC 700VDC 700VDC 700VDC 700VDC 700VDC
-LINK 220k 2W S2

Figure 15: Capacitor board schematic

CPWR-AN13, REV – This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
7 Techniques for Minimizing information, please contact Cree Sales at PowerSales@cree.com.
Parasitic Inductance
 In this case, the capacitor bank consisted of 12 Epcos B32796G3166K 16µF 700V capacitors in a series
parallel array. Two additional Epcos B32794D3805K 8µF 700V capacitors were added to take advantage of
some unused space on the printed circuit card.

The layup of the printed circuit card is shown in Figure 16. The parallel plate structure was formed the
entire top layer for the –LINK node, the entire middle layers for MID node and the entire bottom layer
for the +LINK node. The overall thickness of the board was 1.57mm (0.062”). The outer copper layer
thickness was 0.139mm (4 oz. copper) and the inner layers were 0.0694 mm (2 oz. copper). Layers 2 and
3 are at the same potential so the middle FR4 layer can be set to minimum thickness; in this case it was
set to 0.254mm (0.010”). The remaining two FR4 layers were 0.450mm thick (0.0177”) each.

Layer 1: – LINK plane

FR4

Layer 2: MID plane

FR4 – minimum thickness
Layer 3: MID plane

FR4

Layer 4: + LINK plane

Figure 16: Printed circuit board layup

The goal of paralleling the capacitors was to minimize inductance, but the need to connect the capacitors
in series distracts from this goal. The magnetic field cancelling technique was used to mitigate this effect,
as illustrated in Figure 17. This concept minimized the area of the current loops, by making the series
capacitor MID connection on the outer two pins and the +LINK and –LINK connections on the inner two
pins. The current path is illustrated with the dashed black line.

Capacitor Capacitor

- LINK plane
MID plane

+ LINK plane

Figure 17: Capacitor series connection magnetic field cancellation scheme

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8 Techniques for Minimizing information, please contact Cree Sales at PowerSales@cree.com.
Parasitic Inductance
 Magnetic field cancellation was also applied to the parallel rows of capacitors. This is best illustrated by
referring to sketches of the –LINK plane shown in Figure 18 and the +LINK plane shown in Figure 19. The
connections from each series pair of capacitors to the –LINK and +LINK plane are staggered; therefore, the
current flowing though the paralleled capacitor arrays is traveling in opposite directions to help cancel the
field. The current flows through each series connected pair are illustrated with black arrows.

CAS100H12AM1
SiC MODULE
+LINK

C13
C1 C3 C5 C7 C9 C11
R1 R2 D1

MID
MID

-LINK
R3 R4 S2
C2 C4 C6 C8 C10 C12
C14

Figure 18: - LINK layer

CAS100H12AM1
SiC MODULE
+LINK

C13
C1 C3 C5 C7 C9 C11
R1 R2 D1

MID
MID

-LINK
R3 R4 S2
C2 C4 C6 C8 C10 C12
C14

Figure 19: + LINK layer

Photographs of the capacitor top and bottom side are provided in Figures 20 and 21 respectively.

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9 Techniques for Minimizing information, please contact Cree Sales at PowerSales@cree.com.
Parasitic Inductance
 Figure 20: Capacitor board top side Figure 21: Capacitor board bottom side

The equivalent series inductance (ESL) of the 16µF capacitors is 30nH and the 8µF capacitors is 27nH.
The overall inductance of the series parallel array (assuming no magnetic field cancelling) is 7.30nH. The
ESL of the capacitor board as reported in “Design considerations for designing with Cree SiC modules
Part 1. Understanding the effects of parasitic inductance” was 5.3nH. This measurement was taken
at the module connection point holes, which are not parallel plate geometry, since clearance had to be
made around the module mounting surfaces to avoid electrical shorts. Hence, the 5.3nH consists of the
inductance of the parallel plate capacitor array, plus the slight non-parallel protrusion over the module
interconnection points. A new ESL measurement was carefully made to ensure that the measurement
points were in the parallel plate array itself by using a short calibration fixture that moved the calibration
plane back into the parallel plate array. This method is illustrated in Figure 22. The calibration short is
shown placed over the back side of the printed circuit board. The ‘legs’ of the short are the same length
as the module interconnect tabs.

Figure 22: Calibration short

The impedance and overall inductance of the capacitor board was measured on a LRC meter and the
results are shown in Figure 23. The measured ESL is 2.97nH @ 1MHz, a 2.5x improvement over the simple
parallel connection.

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Parasitic Inductance
 ESL = 2.97 nH @ 1MHz

Figure 23: Capacitor board measured impedance

This simple design study provides valuable insight on the design of low parasitic inductance capacitor banks
for SiC MOSFET modules. The key points are as follows:

• In general, a parallel array of smaller capacitors is superior to a non-parallel array of larger capacitors
for a given capacitance value in minimizing ESL. In this case, the parallel array of smaller capacitors had
one third the ESL of the large capacitor approach.
• The cost of an array of smaller capacitors is generally lower; in this case, it was about half the cost.
• Applying the parallel plate interconnection scheme along with magnetic field cancelling wherever possible
reduced the ESL by a factor of 2.5 versus paralleling alone.

CPWR-AN13, REV – This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
11 Techniques for Minimizing information, please contact Cree Sales at PowerSales@cree.com.
Parasitic Inductance
 Cree Six Pack Module Capacitor Board Design and Results:

Cree’s recently-released CCS050M12CM2 1.2kV 50A SiC MOSFET six-pack module is the first commercially
available SiC MOSFET module in the “six pack” form factor. This module is capable of significantly faster
switching speeds when compared to Si IGBTs; however, the faster switching speed of the SiC MOSFET
module can result in appreciable ringing. The key method to minimizing the ring is to minimize the
parasitic inductance. The following discussion addresses the design steps undertaken by Cree to minimize
this inductance in the double pulse switching time test setup used to characterize the dynamic behavior of
the module.

The module, shown in Figure 24 is packaged in a traditional six-pack configuration with two sets of DC link
terminals on the right side and left side, with three output phase connections provided in the top row of
terminals and six gate drive inputs located in the bottom row of terminals.

Figure 24: Cree 1.2kV 50A SiC MOSFET six-pack module

The schematic of the module is shown in Figure 25. This package is designed for user convenience by
forming a functional block containing all of the semiconductor switches and diodes to implement a three
phase inverter. However, this presents some challenges in designing an appropriate low inductance
capacitor bank to realize optimum performance. A key factor to consider is the two sets of DC link
connections. Minimizing parasitic inductance requires that both sets of connections are used at all times;
using only one set of DC link connections is not recommended, since the layout inductance in the package
will result in asymmetric parasitic inductance between the individual half-bridge sections. Both sets of
link connections must be used to avoid this condition. Also, the link capacitor bank should be laid out
symmetrically with the centerline of the module. Lastly, all previously described techniques for minimizing
inductance should be applied.

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Parasitic Inductance
 17 18

NTC
25 15
26 16

M1 M3 M5
1 D1 5 D3 9 D5

2 6 10
23 21 19
24 22 20

M2 M4 M6
3 D2 7 D4 11 D6

4 8 12
27 13
28 14

Figure 25: Cree 1.2kV 50A six-pack module schematic

Cree developed a double-pulse test setup that follows all of these requirements. A review of the design
and layout provides significant insight on how to optimize the PCB design to get maximum benefit from the
module. The test board, consisting of a capacitor bank, gate drivers and diagnostics to perform dynamic
testing of the Cree SiC MOSFET module, is shown in Figures 26 and 27. The module is mounted to the back
side of the board and the remaining components are mounted to the top side of the board to allow easy
mounting to a heat sink or hot plate.

MODULE

Figure 26: Six-pack test board (front) Figure 27: Six-pack test board (back)

A simplified schematic of the test board is shown in Figure 28. (The schematic does not show the individual
gate drivers to maintain clarity). The corresponding physical locations of the various blocks are shown in
the photograph provided in Figure 29.

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13 Techniques for Minimizing information, please contact Cree Sales at PowerSales@cree.com.
Parasitic Inductance
 +LINK

A B C

25 15
26 16

M1 M3 M5
D1 D3 D5
1 5 9

2 6 10
23 21 19
24 22 20

M2 M4 M6
MID MID
3 D2 7 D4 11
D6

4 8 12

27 13
28 14

Current Viewing
Resistors

-LINK

Capacitor
Arrays

Figure 28: Six-pack test board simplified schematic (gate drivers not shown)

As shown in Figure 29, the physical layout of the key components is symmetric along the centerline of the
printed circuit card.

Capacitor Bank Capacitor Bank

Current Viewing
Resistors

Gate Drives

Figure 29: Six-pack test board major block location

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14 Techniques for Minimizing information, please contact Cree Sales at PowerSales@cree.com.
Parasitic Inductance
 The module has two sets of DC input connections and both need to be utilized to keep symmetry. The link
capacitor bank consists of two identical parallel arrays of series connected capacitors. The exact layout and
the same capacitors utilized in the 50mm half-bridge capacitor board discussion are fully leveraged in this
application. It is possible that the current flowing into the link might not be symmetric; therefore, two T&M
Research SDN-404-01 current viewing resistors are used to monitor the current in both –LINK connections
on the module. The two signals are summed together in the oscilloscope to provide the measurement of
total module link current. It is critical that the coaxial cables connecting the current viewing resistors are
the same length to insure matched propagation delay times.

It is also worth noting that ground loops can be formed by the current and voltage measurement
connections, which can cause false transient readings to be present on the observed waveforms. High
permeability ferrite chokes on the measurement leads are required to mitigate this issue.

The impedance vs. frequency of the test board was characterized using an LCR meter. The measurement
assess the amount of parasitic inductance in the capacitor bank by replacing the current viewing resistors
with shorts. The six pack has two sets of DC link input connections; therefore, two separate impedance
measurements were made of the left and right-hand +DC and –DC link connections. A graph of both
impedance measurements is provided in Figure 30.

100
|Z| Left Side
|Z| Right Side
10

1
|Z| ( )

0.1

0.01

0.001

0.0001
100 1000 10000 100000 1000000 10000000
Freq (Hz)

Figure 30: Impedance vs. frequency for each set of DC link connections

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Parasitic Inductance
 The impedance on both sides is almost identical below 200kHz. The measured impedance of the right
side DC link connections is slightly higher than the left side. A detailed impedance vs. frequency plot is
provided in Figure 31 to highlight the differences. The ESL for each side is shown at 1MHz.

0.1
|Z| Left Side
ESL Left Side
|Z| Right Side
ESL Right Side
2.97nH

2.60nH
|Z| ( )

0.01

0.001
100000 1000000 10000000
Freq (Hz)

Figure 31: Impedance vs. frequency for each set of DC link connections and ESL differences

Because there is a slight layout difference between the right and the left sides of the printed circuit board,
the right side ESL was measured to be 2.97nH and the left side was 2.60nH. The top –DC LINK plane
on the right side has an area cut out that contains the traces for the NTC thermistor. Therefore, it is
reasonable to assume that the ESL on the right side would be somewhat higher.

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16 Techniques for Minimizing information, please contact Cree Sales at PowerSales@cree.com.
Parasitic Inductance
 Conclusions and Recommendations:

A key consideration to realize the best performance from SiC MOSFET modules is the minimization of ESL
of the link capacitor bank and the parasitic inductance of the interface between the link capacitor and
module. The considerations for accomplishing this are as follows:

• Parasitic inductance is a measure of the magnetic field around a conductive path carrying current.
Creating a geometry that cancels the magnetic field will in turn minimize parasitic inductance.
• Parallel (stacked) conductor geometries provide significantly less parasitic inductance than coplanar (side
by side) geometries.
• In general, a parallel array of small capacitors is superior to one large capacitor. Parasitic inductance is
minimized and so is cost. (Note, this applies only for standard geometry capacitors.)
• Applying field cancelling techniques to a parallel array of capacitors can cut the ESL by more than half
when compared to a parallel capacitor array inductance estimate.

Copyright © 2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the
Cree logo, and Zero Recovery are registered trademarks of Cree, Inc. Cree, Inc.
4600 Silicon Drive
This document is provided for informational purposes only and is not a warranty or a specification. This product is currently
Durham, NC 27703
available for evaluation and testing purposes only, and is provided “as is” without warranty. For preliminary, non-binding product
specifications, please see the preliminary data sheet available at www.cree.com/power. USA Tel: +1.919.313.5300
Fax: +1.919.313.5451
www.cree.com/power
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17
Parasitic Inductance