LIBRARY ieee;

USE ieee.std_logic_1164.all;

entity CLOCKDIV is
port(
CLK : in std_logic;
DIVOUT : buffer bit);
end CLOCKDIV;

architecture behavioural of CLOCKDIV is

begin
process(CLK)
variable count : integer:=0;
constant div : integer:=500000;
begin
if CLK'event and CLK='1' then
if(count<div) then
count:=count+1;
if(DIVOUT='0') then
DIVOUT<='0';
elsif(DIVOUT='1') then
DIVOUT<='1';
end if;
else
if(DIVOUT='0') then
DIVOUT<='1';
elsif(DIVOUT='1') then
DIVOUT<='0';
end if;
count:=0;
end if;
end if;
end process;
end behavioural;