Clock Distribution Networks in

Synchronous Digital Integrated Circuits

Sanjay Nath H
sanjay.nath.h@intel.com

August 1, 2018
 Contents 1

Introduction

Synchronous Timing Basics

Setup and hold constraints

Clock Skew and Jitter

Clock Distribution Techniques

Types of distribution network

References

Sanjay Nath H | Intel Corporation

 Introduction
Clock 2

I It is a time reference for the movement of data within a system.

I They are simple control signals.
I Clock waveforms must be particularly clean and sharp .
I They have a temporal relation with the data

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 Introduction
Synchronous Digital System 3

I A synchronous signal is one that has the exact same frequency

and a known fixed phase offset with respect to the local clock.
I A digital synchronous circuit is composed of:-
I memory storage elements
I logic elements
I clocking circuitry and distribution network

Figure: Synchronous interconnect methodology.

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 Synchronous Timing Basics 4

Figure: Pipelined Datapath Circuit and timing parameters.

The following timing parameters characterize the timing of the

sequential circuit.
I The contamination (minimum) delay tc−q,cd , and maximum
propagation delay of the register tc−q .
I The set-up (tsu ) and hold time (thold ) for the registers
I The contamination delay tlogic,cd and maximum delay tlogic of the
combinational logic.

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 Setup and hold constraints
Ideal cases 5

The clock period must be long enough for the data to propagate
through the registers and logic and be set-up at the destination
register before the next rising edge of the clock.

T ≥ Tc−q + Tlogic + Tsu (1)

The hold time of the destination register must be shorter than the
minimum propagation delay through the logic network.

Thold < Tc−q + Tlogic (2)

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 Clock Skew 6

I The spatial variation in arrival time of a clock transition on an

integrated circuit is commonly referred to as clock skew.
I The clock skew can be positive or negative depending upon the
routing direction and position of the clock source.

Figure: positive skew.

The constraints are modified as.

T ≥ Tc−q + Tlogic + Tsu − δ (3)

Thold < Tc−q + Tlogic − δ (4)

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 Clock Skew
Cont: 7

Figure: Negative skew.

The constraints are modified as.

T ≥ Tc−q + Tlogic + Tsu + δ (5)

Thold < Tc−q + Tlogic + δ (6)

Sanjay Nath H | Intel Corporation

 Clock Jitter 8

I Clock jitter refers to the temporal variation of the clock period at a

given point.
I Cycle-to-cycle jitter refers to time varying deviation of a single
clock period and for a given spatial location i.

Tjitter ,i (n) = Ti (n + 1) + Ti (n) − TCLK (7)

Figure: Worst Case Jitter.

The new constraint is:-

T ≥ Tc−q + Tlogic + Tsu + 2tjitter (8)

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 Clock Distribution Techniques
Introduction 9

I Design Constraints
I Minimal skew and jitter
I Power Dissipation
I Degrees of freedom
I Type of material used for wires
I Basic topology and hierarchy
I Sizing of wires and buffers
I Rise and Fall times
I Partitioning of load capacitance

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 Types of distribution network 10

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 Unconstrained Tree 11

Figure: Unconstrained Tree

I The network design is accomplished with a cost function that

minimizes the delay differences across all clock branches
I A clock network with dissimilar buffer and interconnect delay
composition may result in radically different branches that will
exhibit significant mis-tracking across PVT variations
I Usually restricted to small functional blocks within a larger
design.
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 Balanced Tree 12

Figure: H Tree

I A balanced tree exhibits identical nominal delay and identical

buffer and interconnect segments
I Ideally structural skew can be zero
I Good tracking across PVT variations.
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 Other Balanced Trees 13

I X tree exhibits the same properties as an H-tree.

I The trunk widths in a tapered H-tree increase geometrically
toward the root
I Spans the entire die in both the horizontal and vertical
dimensions.

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 Binary Tree 14

I It is intended to deliver the clock in either the vertical or

horizontal dimension.
I Buffers in a binary tree can be designed to co-locate in close
proximity along a centralized stripe.
I This helps in reduced PVT variations than a H tree
I A balanced tree is capable of delivering the clock from the root to
all regions of the die with good structural matching, efficient clock
power and low structural latency

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 Central spine with matched branches 15

I It is a specific implementation of a binary tree.

I The clock can be transported in a balanced fashion across one
dimension of the die with low structural skew.
I The unconstrained branches are simple to implement although
there will be residual skew due to asymmetry
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 Clock Grid 16

I A deep distribution tree will exhibit degraded clock performance.

I Clock grid resembles a mesh with fully connected clock tracks in
both dimensions and grid drivers located on all four sides.
I The grid effectively shorts the output of all drivers and helps
minimize delay mismatches
Sanjay Nath H | Intel Corporation
 References 17

[1]. J. M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated

Circuits: A Design Perspective, 2nd ed. Upper Saddle
River,NJ:Pearson Educ. In1.,2003.
[2]. E. G. Friedman, "Clock distribution networks in synchronous
digital integrated circuits," in Proceedings of the IEEE, vol. 89, no. 5,
pp. 665-692, May 2001.doi: 10.1109/5.929649
[3]. Modern Clock Distribution Systems, Simon Tam, Intel Corporation
(SC12-408)

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Thank you