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A B C D E

COMPAL CONFIDENTIAL
MODEL NAME : PLM00
1 1

PCB NO : LA-7161P (DAZ0I800100)


BOM P/N : 4319AS31L01
4319AS31L02
4319AS31L03
4319AS31L04
4319AS31L05
4319AS31L06
4319AS31L07
Andros MLK
4319AS31L08

AMD APU (Ontario/Zacate) -FT1 + FCH Hudson-M1


2 2

2011-01-05
REV : 1.0(A00)

3
@ : Nopop Component 3

WWAN@: WWAN function


CONN@: Connector only
Z@ : Zacate
O@ : Ontario

4 4

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Cover Sheet
http://hobi-elektronika.net
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

www.vinafix.vn
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 1 of 43
A B C D E
A B C D E

LVDS
LVDS conn. Page 20

TMDS DDR3-SO-DIMM X2
HDMI conn. Page 18 AMD Brazos APU Page 10, 11
DDR3 BUS
VGA FT1
CRT conn. Page 19 1.5V DDRIII 1066 Single Channel
1
BGA 413-Ball 1

19mm x 19mm DDRIII 800~1066MHz


GPP
PCI Express Page 7,8,9

GPP PCIE2 GPP PCIE3 GPP PCIE1

LAN Mini Card UMI


Atheros AR8152 WLAN Mini Card
WWAN
Page 21 Page 25
Page 25

USB port2
RJ45 conn. USB conn.
Page 23
Page 21
USB port0,1
USB conn. x 2
Sub/B & Page 26
2 2

Hudson M1 USB port4 Mini Card


WLAN Page 25
BGA 605-Ball
Clock Generator 23mm x 23mm USB2.0 USB port5 Mini Card
WWAN Page 25 SIM conn.
Page 25
FCH
USB port6
Internal CKG Bluetooth conn.
Page 25
Page 13
Page 12,13,14,15,16
Page 22
USB port8 CardBus 7 in 1 conn.
Realtek RTS5138 Page 22

LPC BUS USB port9


Camera
Page 20
DC/DC Power Button
3
(Power Control) Page 28 Sub/B 3

EC ENE KB926QFE0 CODEC Audio Jack x 2


Sub/B
Page 17 AZ-Audio I/F Realtek ALC259
BATT IN &OTP
Page 32 Page 24
Digital MIC
Camera side

DC IN & DECTOR Int. KBD


Page 17
Page 33
T/P conn.
Page 29
CHARGER SPI ROM
Page 12
Page 34

4 4

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Block Diagram
http://hobi-elektronika.net
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

www.vinafix.vn
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 2 of 43
A B C D E
5 4 3 2 1

POWER SEQUENCE

VIN
D D
B+
+3VALW,+5VALW
+1.1VALW

ON/OFFBTN# NOTE1
T1>10ms, +3VALW to RSMRST#
T1
EC->FCH EC_RSMRST#
T2>100ms, RSMRST# to PBTN_OUT#
EC->FCH PBTN_OUT# T2
T3>100ns, PBTN_OUT# to SLP_S5#
T3
FCH->EC SIO_SLP_S5#
T4>10ms, SLP_S5# to SYSON
T4
EC->PWR SYSON

+1.5V
The same with SLP_S5#
FCH->EC SIO_SLP_S3#
T5>10ms, SYSON to SUSP#
T5
EC->PWR SUSP#

C
+3VS,+5VS,+0.75VS C

+1.8VS

+1.1VS
T6>100ms, SUSP# to VR_ON
T6
EC->PWR VR_ON

+APU_CORE
+APU_COREP_NB NOTE2

PWR->EC VGATE
T7>50ms, VGATE to EC_FCH_PWROK
T7
EC->FCH EC_FCH_PWROK

EC->FCH KB_RST#
98ms>T8>150ms, EC_FCH_PWROK to APU_PWRGD
T8
FCH->APU APU_PWRGD
101ms>T9>113ms, EC_FCH_PWROK to A_RST#
T9
FCH->DEVICE A_RST#

FCH->APU LDT_RST#
B B

NOTE1: RSMRST# rise time(10% to 90%)<50ms


fail time<1ms

NOTE2: EC_FCH_PWROK rise time(10% to 90%)<50ms


fail time<1ms

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, POWER SEQUENCE

www.vinafix.vn
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 3 of 43
5 4 3 2 1
5 4 3 2 1

D D
Voltage Rails
Power Plane Description S1 S3 S5

VIN Adapter power supply (19V) N/A N/A N/A


B+ AC or battery power rail for power circuit. N/A N/A N/A
+APU_CORE Core voltage for CPU (0.7-1.2V) ON OFF OFF
+APU_CORE_NB 1.0V switched power rail ON OFF OFF
+1.5V 1.5V power rail for CPU VDDIO and DDRIII ON ON OFF
+0.75VS 0.75VS switched power rail for DDR terminator ON OFF OFF
+1.05VS 1.05V switched power rail for NB VDDC & VGA ON OFF OFF
+1.1VS 1.1VS switched power rail ON OFF OFF
+1.8VS 1.8V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
+3V_LAN 3.3V power rail for LAN ON ON(WOL) OFF
+3VS 3.3V switched power rail ON OFF OFF

C
+5VALW 5V always on power rail ON ON ON* C

+5VS 5V switched power rail ON OFF OFF

+RTCVCC RTC power ON ON ON

+1.1VALW 1.1V always on power rail ON ON ON*

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW


B B
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF

S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF

S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF

Board ID Table for AD channel


Vcc 3.3V +/- 5% BOARD ID Table
Ra 100K +/- 5%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 Board ID PCB Revision
0 0 0 V 0 V 0.155 V 0x00-0x0C 0 0.1
1 8.2K +/- 5% 0.168 V 0.250 V 0.362 V 0x0D-0x1C 1 0.2
A 2 18K +/- 5% 0.375 V 0.503 V 0.621 V 0x1D-0x30 2 0.3 A

3 33K +/- 5% 0.634 V 0.819 V 0.945 V 0x31-0x49 3 0.4


4 56K +/- 5% 0.958 V 1.185 V 1.359 V 0x4A-0x69 4 0.5
5 100K +/- 5% 1.372 V 1.650 V 1.838 V 0x6A-0x8E 5
6 200K +/- 5% 1.851 V 2.200 V 2.420 V 0x8F-0xBB 6
Title
7 NC 2.433 V 3.300 V 3.300 V 0xBC-0xFF 7
Power Rails
http://hobi-elektronika.net
www.vinafix.vn
Size Document Number Rev
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 4 of 43
5 4 3 2 1
5 4 3 2 1

+3VS
1K
D 1K D

Ontario
P3 APU_SIC
MMBT3904
SMBUS Address [TBD]
P4 APU_SID
MMBT3904
Zacate

+3VS
2.2K
2.2K

AD22 SMB_FCH_CK0 202 JDIMMA SMBUS Address [TBD]


AE22 SMB_FCH_DA0 200
C GND C
10K
10K 202 JDIMMB SMBUS Address [TBD]
200
F5 SMB_FCH_CK1
F4 SMB_FCH_DA1
UT7
Hudson GND 8
(NB_Thermal)
SMBUS Address [TBD]
10K 7
10K

D25 SCL2
F23 SDA2

+3VALW
10K
10K

B26 FCH_SIC
0R @
E26 FCH_SID
0R @
B B

+5VALW
4.7K
4.7K
0R @ WWAN_SMB_CK_R 30 JWLAN1 SMBUS Address [TBD]
100R PJBATT 0R @
77 EC_SMB_CK1 7 SMBUS Address [TBD] WWAN_SMB_DA_R 32
(BattERy conn)
78 EC_SMB_DA1
100R 6

0R @ WWAN_SMB_CK_R 30
+3VS JWWAN1 SMBUS Address [TBD]
2.2K 0R @
KB 926 WWAN_SMB_DA_R 32
2.2K

79 EC_SMB_CK2
0R @ LAN_SMB_CK_R 30 UL10 (LAN) SMBUS Address [TBD]
80 EC_SMB_DA2
0R @ LAN_SMB_DA_R 32

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
SMBus Topology
http://hobi-elektronika.net
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

www.vinafix.vn
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 5 of 43
5 4 3 2 1
A

Board ID Table for AD channel


Vcc 3.3V +/- 5% BOARD ID Table USB PORT# DESTINATION
Ra 100K +/- 5%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 Board ID PCB Revision 0 USB Port 0 (Sub-board)
0 0 0 V 0 V 0.155 V 0x00-0x0C 0 0.1
1 8.2K +/- 5% 0.168 V 0.250 V 0.362 V 0x0D-0x1C 1 0.2 1 USB Port 1 (Sub-board)
2 18K +/- 5% 0.375 V 0.503 V 0.621 V 0x1D-0x30 2 0.3
3 33K +/- 5% 0.634 V 0.819 V 0.945 V 0x31-0x49 3 0.4 2 USB Port 2
4 56K +/- 5% 0.958 V 1.185 V 1.359 V 0x4A-0x69 4 0.5
5 100K +/- 5% 1.372 V 1.650 V 1.838 V 0x6A-0x8E 5 3 None
6 200K +/- 5% 1.851 V 2.200 V 2.420 V 0x8F-0xBB 6
7 NC 2.433 V 3.300 V 3.300 V 0xBC-0xFF 7 4 MiniCard- WLAN

SMBUS Control Table USB 5 MiniCard- WWAN

EXPRESS 6 None
SOURCE MIINI1 BATT MINI2 CARD SODIMM CLKOUT DESTINATION

PCI0 None 7 None


EC_SMB_CK1
EC_SMB_DA1
KB926 X V X X X
8 Card Reader
EC_SMB_CK2 KB926 X X X X X PCI1 PCICLK1
EC_SMB_DA2
9 Camera
PCH_SMBCLK PCI2 PCICLK2
PCH_SMBDATA PCH
V X V V X 10 None
PCI3 PCICLK3
MEM_SMBCLK
MEM_SMBDATA PCH
X X X X V PCI4 PCICLK4
11 None

12 None

13 None
1 1

APU

DIFFERENTIAL DESTINATION SATA DESTINATION PCI EXPRESS DESTINATION

CLKOUT_PCIE0 10/100 LAN SATA0 HDD1 Port0 None

CLKOUT_PCIE1 MINI CARD- WLAN SATA1 None Port1 WWAN

CLKOUT_PCIE2 MINI CARD- WWAN SATA2 None Port2 10/100

CLK CLKOUT_PCIE3 None SATA3 None Port3 WLAN

CLKOUT_PCIE4 None SATA4 None FCH

CLKOUT_PCIE5 None Symbol Note : SATA5 None PCI EXPRESS DESTINATION

CLKOUT_PCIE6 None : means Digital Ground Port0 None

CLKOUT_PCIE7 None Port1 None


: means Analog Ground
CLKOUT_PCIE8 None Port2 None

Port3 None

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/31 Deciphered Date 2011/07/31 Title
Notes List
http://hobi-elektronika.net
www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 6 of 43
A
5 4 3 2 1

UU1B
+1.8VS
CU1 1 2 0.1U_0402_16V7K HDMI_TXD2P_C A8 H3 RU3 1 2 150_0402_1%

DISPLAYPORT 1
<18> HDMI_TXD2P CU3 HDMI_TXD2N_C TDP1_TXP0 DP_ZVSS
1 2 0.1U_0402_16V7K B8

DP MISC
RU1 APU_LDT_STP# <18> HDMI_TXD2N TDP1_TXN0
1 2 1K_0402_5% G2 ENBKL <20>
CU4 HDMI_TXD1P_C DP_BLON
1 2 0.1U_0402_16V7K B9 H2 ENVDD <20>
<18> HDMI_TXD1P TDP1_TXP1 DP_DIGON
RU4 1 2 300_0402_5% DBREQ# <18> HDMI_TXD1N
CU5 1 2 0.1U_0402_16V7K HDMI_TXD1N_C A9 TDP1_TXN1 DP_VARY_BL H1 NB_LCD_PWM <20>
RU5 1 2 1K_0402_5% APU_SVC CU6 1 2 0.1U_0402_16V7K HDMI_TXD0P_C D10
<18> HDMI_TXD0P CU7 HDMI_TXD0N_C C10 TDP1_TXP2
<18> HDMI_TXD0N
1 2 0.1U_0402_16V7K TDP1_TXN2 TDP1_AUXP B2 HDMICLK_UMA <18>
RU2 1 2 1K_0402_5% APU_SVD C2 HDMIDAT_UMA <18>
CU2 HDMI_CLKP_C TDP1_AUXN
1 2 0.1U_0402_16V7K A10
<18> HDMI_CLKP TDP1_TXP3
RU6 1 2 300_0402_5% LDT_RST# CU8 1 2 0.1U_0402_16V7K HDMI_CLKN_C B10 C1 HDMI_HPD <18>
<18> HDMI_CLKN TDP1_TXN3 TDP1_HPD
RU7 1 2 300_0402_5% APU_PWRGD <20> LVDS_A2+
B5 LTDP0_TXP0 LTDP0_AUXP A3 LDDC_CLK_MCH <20>
A5 B3

DISPLAYPORT 0
<20> LVDS_A2- LTDP0_TXN0 LTDP0_AUXN LDDC_DATA_MCH <20>
RU8 1 2 510_0402_1% TEST_25_L
D D6 D3 LTDP0_HPD RU9 2 @ 1 100K_0402_5% D
RU10 1 TEST_36 <20> LVDS_A1+ LTDP0_TXP1 LTDP0_HPD
2 1K_0402_5% C6
<20> LVDS_A1- LTDP0_TXN1
DAC_RED C12 VGA_CRT_R <19>
RU35 2 1 1K_0402_5% TEST_35 A6 D13 RU11 1 2 150_0402_1%
<20> LVDS_A0+ LTDP0_TXP2 DAC_REDB
<20> LVDS_A0-
B6 LTDP0_TXN2 DAC_GREEN A12 VGA_CRT_G <19>
Enable HDMI output B12 RU12 1 2 150_0402_1%
DAC_GREENB
D8 A13

VGA DAC
<20> LVDS_ACLK+ LTDP0_TXP3 DAC_BLUE VGA_CRT_B <19>
C8 B13 RU13 1 2 150_0402_1%
+3VS <20> LVDS_ACLK- LTDP0_TXN3 DAC_BLUEB
<13> CLK_APU V2 CLKIN_H DAC_HSYNC E1 VGA_CRT_HSYNC <19>
<13> CLK_APU# V1 CLKIN_L DAC_VSYNC E2 VGA_CRT_VSYNC <19>
RU16 1 2 1K_0402_5% APU_PROCHOT#

CLK
<13> CLK_APU_DP D2 DISP_CLKIN_H DAC_SCL F2 VGA_DDC_CLK <19>
RU18 1 2 1K_0402_5% APU_ALERT#_R <13> CLK_APU_DP# D1 D4
DISP_CLKIN_L DAC_SDA VGA_DDC_DATA <19>
RU19 1 2 1K_0402_5% APU_SIC J1 D12 RU17 1 2 499_0402_1%
<40> APU_SVC SVC DAC_ZVSS
<40> APU_SVD J2
APU_SID SVD TEST_4

SER
RU20 1 2 1K_0402_5% R1 PAD TU1
APU_SIC TEST4 TEST_5
Link to Power IC P3
SIC TEST5
R2 PAD TU2
RU21 1 2 1K_0402_5% APU_THERMTRIP#_R APU_SID P4 R6
SID TEST6 TEST_14
T5 PAD TU3
TEST14 TEST_15
<13> LDT_RST# T3 E4
RU30 2 TEST_18 RESET_L TEST15 TEST_16
1 1K_0402_5% <13> APU_PWRGD T4
PWROK TEST16
K4 PAD TU4

CTRL
L1 TEST_17 PAD TU5
RU32 2 TEST_19 APU_PROCHOT# U1 TEST17 TEST_18
1 1K_0402_5% L2
APU_THERMTRIP#_R U2 PROCHOT_L TEST18 TEST_19
RU24 footprint short M2

TEST
RU34 1 TEST_25_H APU_ALERT#_R T2 THERMTRIP_L TEST19 TEST_25_H
2 510_0402_5% RU24 1 @ 2 0_0402_5% K1
@ <17> APU_ALERT# RU25 1 @ ALERT_L TEST25_H TEST_25_L
2 0_0402_5% K2
RU36 2 TEST_15 <12> APU_ALERT#_FCH APU_TDI TEST25_L TEST_28_H
1 1K_0402_5% N2 L5 PAD TU6
APU_TDO TDI TEST28_H TEST_28_L
Connection to EC, FCH input need to pull-down N1
TDO TEST28_L
M5 PAD TU7
AMD check list Ver 1.02 APU_TCLK P1 M21 TEST_31 PAD TU8
TCK TEST31

JTAG
Close to APU APU_TMS P2 J18 TEST_33_H CU91 2 0.1U_0402_16V4Z RU27
1 2 51_0402_1%
Delete 1K pulldown requirement for TEST15 APU_TRST# TMS TEST33_H TEST_33_L CU10
TU13PAD M4
TRST_L TEST33_L
J19 1 2 0.1U_0402_16V4Z RU28
1 2 51_0402_1%
DBRDY M3 U15 TEST_34_H PAD TU9
TU14PAD DBRDY TEST34_H
DBREQ# M1 T15 TEST_34_L PAD TU10
DBREQ_L TEST34_L TEST_35
H4
TEST35 TEST_36
F4 N5
<40> APU_VDDNB_RUN_FB_H VDDCR_NB_SENSE TEST36 TEST_37
C G1 R5 PAD TU11 C
<40> APU_VDD0_RUN_FB_H VDDCR_CPU_SENSE TEST37
+5VS
AMD check list Ver 1.03 TU12PAD F3
VDDIO_MEM_S_SENSE
use 2k pull up to +5V. F1
<40> APU_VDD0_RUN_FB_L VSS_SENSE
K3
RU14 1 HDMIDAT_UMA TEST38 APU_LDT_STP#
2 2K_0402_1% B4 T1 APU_LDT_STP# <13>
RSVD_1 DMAACTIVE_L
W11
RU15 1 HDMICLK_UMA RSVD_2
2 2K_0402_1% V5
RSVD_3
Link to Power IC ZACATE-EME350GBB22GT-1.6G_BGA_A31!
RU23 1 2 2K_0402_1% LDDC_DATA_MCH Z@
+3VS
RU26 1 2 2K_0402_1% LDDC_CLK_MCH SA00004KG1L
1 2 APU_PROCHOT#
<13> FCH_PROCHOT#
RU22 1 2 100K_0402_5% LTDP0_HPD @ RU38 0_0402_5%

1
footprint short RU39

2
10K_0402_5%
RU40
1K_0402_5%

2 2
B
2N7002KDW

1
+3VS

E
APU_THERMTRIP#_R 3 1 APU_THERMTRIP# <14>

C
Vgs(th): min 1.0V QU2
1

MMBT3904_NL_SOT23-3
RU41
Typ 1.6V
10K_0402_5% Max 2.5V 1 RU42 2 0_0402_5%
@ @
ESD 2KV
2

If FCH internal pull-up disabled, level-shifter could be deleted.


Need BIOS to disable internal pull-up!!
2

B APU_SID 1 6 EC_SMB_DA 1 2 FCH_SID T0 FCH B


FCH_SID <14>
RU43 0_0402_5%
@ QU1A 1 2 EC_SMB_DA2
EC_SMB_DA2 <17,21,25>
2N7002KDWH_SOT363-6 RU44 0_0402_5% TO EC
1 2 +1.8VS +1.8VS
@ RU45 0_0402_5% footprint short +'7&211(&725
5

APU_SIC EC_SMB_CK FCH_SIC


$0'$38'(%8*3257
4 3 1 2 FCH_SIC <14> T0 FCH
RU46 0_0402_5%

2
@ QU1B 1 2 EC_SMB_CK2 EC_SMB_CK2 <17,21,25>
2N7002KDWH_SOT363-6 RU47 0_0402_5% TO EC JU1 CONN@
1 2 RU48 1 2 APU_TCLK RU50 2 1 1K_0402_5%
@ RU49 0_0402_5% 1 2
footprint short 1K_0402_5% 3 4 APU_TMS RU51 2 1 1K_0402_5%

1
3 4
5 6 APU_TDI RU52 2 1 1K_0402_5%
5 6
footprint short
7 8 APU_TDO
0_0402_5% 7 8
APU_TRST# @ RU53 1 2 APU_TRST#_R 9 10 APU_PWRGD
9 10
2 1 11 12 LDT_RST#
RU54 10K_0402_5% 11 12 +1.8VS
UU1 2 1 13 14 DBRDY
RU55 10K_0402_5% 13 14
2 1 15 16 DBREQ# 1 2
RU56 10K_0402_5% 15 16 RU57 300_0402_5%
17 18 J108_PLLTST0 1 2 TEST_19
17 18 @ RU58 0_0402_5%
UU1 19 20 J108_PLLTST1 1 2 TEST_18
19 20 @ RU59 0_0402_5%
O@
footprint short
S IC ONTARIO CMC50AFPB22GT 1G BGA A31! SAMTE_ASP-136446-07-B

A SA00004KD1L A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/31 Deciphered Date Title

www.vinafix.vn THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DISPLAY,CLK,JTAG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-7161P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 05, 2011 Sheet 7 of 43
5 4 3 2 1
5 4 3 2 1

<10,11> DDR_D[0..63] <13> UMI_C_TXP[0..3]


<10,11> DDR_DQS#[0..7] <13> UMI_C_TXN[0..3]
<10,11> DDR_DQS[0..7]

<10,11> DDR_DM[0..7] <13> UMI_C_RXP[0..3]


<10,11> DDR_MA[0..15] <13> UMI_C_RXN[0..3]

UU1E UU1A
DDR_MA0 R17 B14 DDR_D0 AA6 AB6
DDR_MA1 M_ADD0 M_DATA0 DDR_D1 P_GPP_RXP0 P_GPP_TXP0
H19 A15 Y6 AC6
DDR_MA2 M_ADD1 M_DATA1 DDR_D2 P_GPP_RXN0 P_GPP_TXN0
J17 A17
DDR_MA3 M_ADD2 M_DATA2 DDR_D3
H18 D18 <25> PCIE_NRX_WWANTX_P2 AB4 AB3 PCIE_NTX_WWANRX_P2_C CF78 1 2 0.1U_0402_16V7K PCIE_NTX_WWANRX_P2 <25>

PCIE I/F
M_ADD3 M_DATA3 P_GPP_RXP1 P_GPP_TXP1
::$1 <25> ::$1
D DDR_MA4 DDR_D4 D
H17 A14 PCIE_NRX_WWANTX_N2 AC4 AC3 PCIE_NTX_WWANRX_N2_C CF79 1 2 0.1U_0402_16V7K PCIE_NTX_WWANRX_N2 <25>
DDR_MA5 M_ADD4 M_DATA4 DDR_D5 P_GPP_RXN1 P_GPP_TXN1
G17 C14
DDR_MA6 M_ADD5 M_DATA5 DDR_D6 PCIE_NTX_LANRX_P0_C CU11 1
H15 C16 <21> PCIE_NRX_LANTX_P0 AA1 Y1 2 0.1U_0402_16V7K PCIE_NTX_LANRX_P0 <21>
M_ADD6 M_DATA6 P_GPP_RXP2 P_GPP_TXP2
DDR_MA7
DDR_MA8
G18
M_ADD7 M_DATA7
D16 DDR_D7
/$1 <21> PCIE_NRX_LANTX_N0 AA2
P_GPP_RXN2 P_GPP_TXN2
Y2 PCIE_NTX_LANRX_N0_C CU12 1 2 0.1U_0402_16V7K PCIE_NTX_LANRX_N0 <21> /$1
F19
DDR_MA9 M_ADD8 DDR_D8 PCIE_NTX_WLANRX_P1_C CU13 1
E19 C18 <25> PCIE_NRX_WLANTX_P1 Y4 V3 2 0.1U_0402_16V7K PCIE_NTX_WLANRX_P1 <25>
M_ADD9 M_DATA8 P_GPP_RXP3 P_GPP_TXP3
DDR_MA10
DDR_MA11
T19
M_ADD10 M_DATA9
A19 DDR_D9
DDR_D10
:/$1 <25> PCIE_NRX_WLANTX_N1 Y3
P_GPP_RXN3 P_GPP_TXN3
V4 PCIE_NTX_WLANRX_N1_C CU14 1 2 0.1U_0402_16V7K PCIE_NTX_WLANRX_N1 <25> :/$1
F17 B21
DDR_MA12 M_ADD11 M_DATA10 DDR_D11 RU60 1
E18 D20 +1.05VS 2 2K_0402_1% Y14 AA14 RU61 1 2 1.27K_0402_1%
DDR_MA13 M_ADD12 M_DATA11 DDR_D12 P_ZVDD_10 P_ZVSS
W17 A18
DDR_MA14 M_ADD13 M_DATA12 DDR_D13
E16 B18
DDR_MA15 M_ADD14 M_DATA13 DDR_D14
G15 M_ADD15 M_DATA14 A21

DDR SYSTEM MEMORY


C20 DDR_D15 UMI_C_RXP0 AA12 AB12 UMI_TXP0 CU17 1 2 0.1U_0402_16V7K UMI_C_TXP0
DDR_BS0 M_DATA15 UMI_C_RXN0 P_UMI_RXP0 P_UMI_TXP0 UMI_TXN0 CU18 1
<10,11> DDR_BS0 R18 M_BANK0 Y12 P_UMI_RXN0 P_UMI_TXN0 AC12 2 0.1U_0402_16V7K UMI_C_TXN0
<10,11> DDR_BS1 DDR_BS1 T18 C23 DDR_D16
DDR_BS2 M_BANK1 M_DATA16 DDR_D17 UMI_C_RXP1 UMI_TXP1 CU19 1
<10,11> DDR_BS2 F16 M_BANK2 M_DATA17 D23 AA10 P_UMI_RXP1 P_UMI_TXP1 AC11 2 0.1U_0402_16V7K UMI_C_TXP1
F23 DDR_D18 UMI_C_RXN1 Y10 AB11 UMI_TXN1 CU20 1 2 0.1U_0402_16V7K UMI_C_TXN1

UMI I/F
DDR_DM0 M_DATA18 DDR_D19 P_UMI_RXN1 P_UMI_TXN1
D15 M_DM0 M_DATA19 F22
DDR_DM1 B19 C22 DDR_D20 UMI_C_RXP2 AB10 AA8 UMI_TXP2 CU21 1 2 0.1U_0402_16V7K UMI_C_TXP2
DDR_DM2 M_DM1 M_DATA20 DDR_D21 UMI_C_RXN2 P_UMI_RXP2 P_UMI_TXP2 UMI_TXN2 CU22 1
D21 M_DM2 M_DATA21 D22 AC10 P_UMI_RXN2 P_UMI_TXN2 Y8 2 0.1U_0402_16V7K UMI_C_TXN2
DDR_DM3 H22 F20 DDR_D22
DDR_DM4 M_DM3 M_DATA22 DDR_D23 UMI_C_RXP3 UMI_TXP3 CU23 1
P23 M_DM4 M_DATA23 F21 AC7 P_UMI_RXP3 P_UMI_TXP3 AB8 2 0.1U_0402_16V7K UMI_C_TXP3
DDR_DM5 V23 UMI_C_RXN3 AB7 AC8 UMI_TXN3 CU24 1 2 0.1U_0402_16V7K UMI_C_TXN3
DDR_DM6 M_DM5 DDR_D24 P_UMI_RXN3 P_UMI_TXN3
AB20 M_DM6 M_DATA24 H21
DDR_DM7 AA16 H23 DDR_D25 ZACATE-EME350GBB22GT-1.6G_BGA_A31!
M_DM7 M_DATA25 DDR_D26 Z@
M_DATA26 K22
DDR_DQS0 A16 K21 DDR_D27
DDR_DQS#0 M_DQS_H0 M_DATA27 DDR_D28
B16 M_DQS_L0 M_DATA28 G23
DDR_DQS1 B20 H20 DDR_D29
DDR_DQS#1 M_DQS_H1 M_DATA29 DDR_D30
A20 M_DQS_L1 M_DATA30 K20
DDR_DQS2 E23 K23 DDR_D31
DDR_DQS#2 M_DQS_H2 M_DATA31 +1.5V
E22 M_DQS_L2
C DDR_DQS3 DDR_D32 C
J22 M_DQS_H3 M_DATA32 N23
DDR_DQS#3 J23 P21 DDR_D33
DDR_DQS4 M_DQS_L3 M_DATA33 DDR_D34
R22 M_DQS_H4 M_DATA34 T20

1
DDR_DQS#4 P22 T23 DDR_D35
DDR_DQS5 M_DQS_L4 M_DATA35 DDR_D36 RU62
W22 M_DQS_H5 M_DATA36 M20
DDR_DQS#5 V22 P20 DDR_D37
DDR_DQS6 M_DQS_L5 M_DATA37 DDR_D38 1K_0402_1%
AC20 M_DQS_H6 M_DATA38 R23
DDR_DQS#6 AC21 T22 DDR_D39

2
DDR_DQS7 M_DQS_L6 M_DATA39 +M_VREF 1000P_0402_50V7K
AB16
DDR_DQS#7 M_DQS_H7 DDR_D40
AC16 V20 1 1
M_DQS_L7 M_DATA40 DDR_D41 CU25 CU26
V21
M_DATA41

1
<10> DDR_A_CLK0 DDR_A_CLK0 M17 Y23 DDR_D42
DDR_A_CLK0# M_CLK_H0 M_DATA42 DDR_D43 RU63
<10> DDR_A_CLK0# M16 Y22
DDR_A_CLK1 M_CLK_L0 M_DATA43 DDR_D44 2 2
<10> DDR_A_CLK1 M19 T21
DDR_A_CLK1# M_CLK_H1 M_DATA44 DDR_D45 1K_0402_1%
<10> DDR_A_CLK1# M18 U23
DDR_B_CLK0 M_CLK_L1 M_DATA45 DDR_D46 0.1U_0402_16V4Z
<11> DDR_B_CLK0 N18 W23

2
DDR_B_CLK0# M_CLK_H2 M_DATA46 DDR_D47
<11> DDR_B_CLK0# N19 Y21
DDR_B_CLK1 M_CLK_L2 M_DATA47
<11> DDR_B_CLK1 L18
DDR_B_CLK1# M_CLK_H3 DDR_D48
<11> DDR_B_CLK1# L17 Y20
M_CLK_L3 M_DATA48 DDR_D49
AB22
DDR_RST# M_DATA49 DDR_D50
<10,11> DDR_RST# L23 AC19
DDR_EVENT# M_RESET_L M_DATA50 DDR_D51
<10,11> DDR_EVENT# N17 AA18
M_EVENT_L M_DATA51 DDR_D52
AA23
M_DATA52 DDR_D53
AA20
DDR_CKE0 M_DATA53 DDR_D54
<10,11> DDR_CKE0 F15 AB19
DDR_CKE1 M_CKE0 M_DATA54 DDR_D55
<10,11> DDR_CKE1 E15 Y18
M_CKE1 M_DATA55
AC17 DDR_D56
M_DATA56 DDR_D57
Y16
DDR_A_ODT0 M_DATA57 DDR_D58
<10> DDR_A_ODT0 W19 AB14
DDR_A_ODT1 M0_ODT0 M_DATA58 DDR_D59
<10> DDR_A_ODT1 V15 AC14
DDR_B_ODT0 M0_ODT1 M_DATA59 DDR_D60
<11> DDR_B_ODT0 U19 AC18
B DDR_B_ODT1 M1_ODT0 M_DATA60 DDR_D61 B
<11> DDR_B_ODT1 W15 AB18
M1_ODT1 M_DATA61 DDR_D62
AB15
DDR_A_CS0# M_DATA62 DDR_D63
<10> DDR_A_CS0# T17 AC15
DDR_A_CS1# M0_CS_L0 M_DATA63
<10> DDR_A_CS1# W16
DDR_B_CS0# M0_CS_L1
<11> DDR_B_CS0# U17
DDR_B_CS1# M1_CS_L0 +M_VREF +1.5V
<11> DDR_B_CS1# V16 M23
M1_CS_L1 M_VREF
<10,11> DDR_RAS# DDR_RAS# U18
DDR_CAS# M_RAS_L
<10,11> DDR_CAS# V19
DDR_WE# M_CAS_L RU64 39.2_0402_1%
<10,11> DDR_WE# V17 M22 1 2
M_WE_L M_ZVDDIO_MEM_S
ZACATE-EME350GBB22GT-1.6G_BGA_A31!
Z@

+1.5V

DDR_EVENT# RU67 2 1 1K_0402_1%

DDR_RST# RU68 2 1 1K_0402_1%


@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/31 Deciphered Date Title
DDRIII,UMI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-7161P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 05, 2011 Sheet 8 of 43
5 4 3 2 1
5 4 3 2 1

+APU_CORE

+1.8VS

UU1C @ LU1
+APU_CORE +VDD_18 2 1 UU1D

TSense/PLL/DP/PCIE/IO
E5 U8 0_0805_5% A7 N13
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
180P_0402_50V8J

0.1U_0402_16V7K
VDDCR_CPU_1 VDD_18_1 VSS_1 VSS_50
1 1 1 1 1 1 1 E6 W8 1 1 1 1 1 1 1 B7 N20
VDDCR_CPU_2 VDD_18_2 VSS_2 VSS_51
CU34

CU35

CU27

CU36

CU28

CU29

CU33

CU30

CU37

CU38

CU39

CU31

CU40

CU32
F5 U6 B11 N22
D VDDCR_CPU_3 VDD_18_3 VSS_3 VSS_52 D
F7
VDDCR_CPU_4 VDD_18_4
U9 footprint short B17
VSS_4 VSS_53
P10
G6 W6 B22 P14
2 2 2 2 2 2 2 VDDCR_CPU_5 VDD_18_5 2 2 2 2 2 2 2 VSS_5 VSS_54
G8 T7 C4 R4
VDDCR_CPU_6 VDD_18_6 VSS_6 VSS_55
H5 V7 D5 R7
VDDCR_CPU_7 VDD_18_7 VSS_7 VSS_56

CPU CORE
H7 D7 R20
VDDCR_CPU_8 VSS_8 VSS_57
J6 D9 T6
VDDCR_CPU_9 VSS_9 VSS_58
J8 D11 T9
VDDCR_CPU_10 VSS_10 VSS_59
L7 D14 T11
VDDCR_CPU_11 VSS_11 VSS_60
M6 B15 T13
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

180P_0402_50V8J

180P_0402_50V8J
VDDCR_CPU_12 VSS_12 VSS_61
1 1 1 1 1 1 M8 D17 U4
VDDCR_CPU_13 VSS_13 VSS_62
CU41

CU42

CU43

CU44

CU45

CU46
N7 D19 U5
VDDCR_CPU_14 +1.8VS VSS_14 VSS_63
R8 E7 U7
VDDCR_CPU_15 VSS_15 VSS_64

GND
E9 U12
2 2 2 2 2 2 +APU_CORE_NB @ LU2 VSS_16 VSS_65
E12 U20
VSS_17 VSS_66

DAC
E8 W9 +VDD_18_DAC 2 1 E20 U22
VDDCR_NB_1 VDD_18_DAC 0_0805_5% VSS_18 VSS_67
E11 F8 V8

10U_0603_6.3V6M
180P_0402_50V8J
VDDCR_NB_2 VSS_19 VSS_68
E13 1 1 1 footprint short F11 V9

1U_0402_6.3V6K
VDDCR_NB_3 VSS_20 VSS_69

CU47

CU48

CU49
F9 F13 V11
VDDCR_NB_4 VSS_21 VSS_70
F12 G4 V13
VDDCR_NB_5 VSS_22 VSS_71

GPU AND NB CORE


G11 G5 W1
G13
VDDCR_NB_6
VDDCR_NB_7
POWER TU15
2 2 2 G7
VSS_23
VSS_24
VSS_72
VSS_73
W2
H9 +1.05VS G9 W4
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

VDDCR_NB_8 PAD VSS_25 VSS_74


1 1 1 1 1 H12 G12 W5
VDDCR_NB_9 VSS_26 VSS_75
CU50

CU51

CU52

CU53

CU54

K11
VDDCR_NB_10 TU15 near UU1 G20
VSS_27 VSS_76
W7
K13 LU3 G22 W12
VDDCR_NB_11 VSS_28 VSS_77

DIS PLL
L10 U11 +VDDL_10 2 1 H6 W20
2 2 2 2 2 VDDCR_NB_12 VDDPL_10 VSS_29 VSS_78
L12 H11 Y5

1U_0402_6.3V6K
180P_0402_50V8J

10U_0603_6.3V6M
0.1U_0402_16V7K
VDDCR_NB_13 FBMA-L11-201209-221LMA30T_0805 VSS_30 VSS_79
L14 1 1 1 1 H13 Y7
VDDCR_NB_14 VSS_31 VSS_80

CU55

CU56

CU57

CU58
M11 J4 Y9
VDDCR_NB_15 VSS_32 VSS_81
M12 J5 Y11
VDDCR_NB_16 VSS_33 VSS_82
M13 J7 Y13
VDDCR_NB_17 2 2 2 2 VSS_34 VSS_83
N10 J20 Y15
VDDCR_NB_18 VSS_35 VSS_84
N12 K10 Y17
+APU_CORE_NB VDDCR_NB_19 @ LU4 VSS_36 VSS_85
N14 K14 Y19
VDDCR_NB_20 VSS_37 VSS_86

PCIE/IO/DDR3 Phy
P11 +VDD_10 2 1 L4 AA4
VDDCR_NB_21 0_0805_5% VSS_38 VSS_87
P13 U13 L6 AA22

10U_0603_6.3V6M

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K
180P_0402_50V8J

0.1U_0402_16V7K

0.1U_0402_16V7K
VDDCR_NB_22 VDD_10_1 VSS_39 VSS_88
W13 1 1 1 1 1 1 1 L8 AB2
+1.5V VDD_10_2 VSS_40 VSS_89

CU59

CU60

CU61

CU62

CU63

CU64

CU65
C
VDD_10_3
V12 footprint short L11
VSS_41 VSS_90
AB5 C
G16 T12 L13 AB9
VDDIO_MEM_S_1 VDD_10_4 VSS_42 VSS_91
G19 L20 AB13
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

VDDIO_MEM_S_2 2 2 2 2 2 2 2 VSS_43 VSS_92


1 1 1 1 1 E17 L22 AB17
VDDIO_MEM_S_3 VSS_44 VSS_93
CU66

CU67

CU68

CU69

CU70

J16 M7 AB21
VDDIO_MEM_S_4 VSS_45 VSS_94

DDR3
L16 N4 AC5
VDDIO_MEM_S_5 VSS_46 VSS_95
L19 N6 AC9
2 2 2 2 2 VDDIO_MEM_S_6 VSS_47 VSS_96
N16 N8 AC13
VDDIO_MEM_S_7 VSS_48 VSS_97
R16 N11 A11

DP Phy/IO
VDDIO_MEM_S_8 VSS_49 VSSBG_DAC
R19
VDDIO_MEM_S_9 +3VS
W18
VDDIO_MEM_S_10
U16 A4
VDDIO_MEM_S_11 VDD_33 ZACATE-EME350GBB22GT-1.6G_BGA_A31!

1U_0402_6.3V6K
0.1U_0402_16V7K
1 1
ZACATE-EME350GBB22GT-1.6G_BGA_A31!

CU71

CU72
Z@
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

180P_0402_50V8J

180P_0402_50V8J

1 1 1 1 1 1 1 2 2
CU73

CU74

CU75

CU76

CU77

CU78

CU79

2 2 2 2 2 2 2
+1.5V
10U_0603_6.3V6M

10U_0603_6.3V6M

1 1
CU80

CU81
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

1 1 1 1 2 2
CU82

CU83

CU84

CU85

2 2 2 2
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1
CU86

CU87

CU88

CU89

B B

POWER +1.05VS
2 2 2 2
220U_B2_2.5VM_R35

1
10U_0603_6.3V6M

CU91

1
+
CU90

@ 1 1 1 1 1
180P_0402_50V8J

180P_0402_50V8J
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

2 2
CU92

CU93

CU94

CU95

CU96

2 2 2 2 2

+APU_CORE POWER
330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

1 1 1
10U_0603_6.3V6M

1
+ + +
CU97

CU98

CU99

CU106
U106

@
@C
2 2 2 2

+1.5V
POWER +1.8VS
POWER
Near CPU Socket
+APU_CORE_NB
A A
330U_2.5V_M

1
10U_0603_6.3V6M
330U_2.5V_M

1 1
22U_0805_6.3V6M

+
CU110

CU113
U113

1
330U_D2_2.5VY_R9M

+
CU109

CU115

1 1
10U_0603_6.3V6M

@
@C
330U_2.5V_M

1 2 2
+ +
CU111

CU112

CU114

2 2
@
2 2 2

Near CPU Socket Near CPU Socket Near CPU Socket


Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/31 Deciphered Date 2011/07/31 Title
P07-FT1 PWR/VSS

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
(330uF_6.3V_4.2L_ESR17m)*1=(SF000002Z00) (330uF_6.3V_4.2L_ESR17m)*1=(SF000002Z00) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 9 of 43
5 4 3 2 1
5 4 3 2 1

+1.5V +1.5V
M1 Circuit <8,11> DDR_DQS#[0..7]
JDIMMA
+1.5V 1 2
<8,11> DDR_D[0..63] +VREF_DQ VREF_DQ VSS1
3 4 DDR_D4
DDR_D0 VSS2 DQ4 DDR_D5
<8,11> DDR_DM[0..7] 5 DQ0 DQ5 6

1
1 1 0.1U_0402_16V4Z DDR_D1 7 8
RD2 CD1 CD2 DQ1 VSS3 DDR_DQS#0
<8,11> DDR_DQS[0..7] 9 VSS4 DQS#0 10
1000P_0402_50V7K DDR_DM0 11 12 DDR_DQS0
1K_0402_1% DM0 DQS0
<8,11> DDR_MA[0..15] 13 VSS5 VSS6 14
2 2 DDR_D2 DDR_D6
15 16
2

DDR_D3 DQ2 DQ6 DDR_D7


+VREF_DQ 17 DQ3 DQ7 18
19 20
VSS7 VSS8
1

DDR_D8 21 22 DDR_D12
RD3 DDR_D9 DQ8 DQ12 DDR_D13
23 24
D DQ9 DQ13 D
25 26
1K_0402_1% DDR_DQS#1 VSS9 VSS10 DDR_DM1
27 28
DDR_DQS1 DQS#1 DM1
29 30
2

DQS1 RESET# DDR_RST# <8,11>


31 32
DDR_D10 VSS11 VSS12 DDR_D14
33 34
DDR_D11 DQ10 DQ14 DDR_D15
35 36
DQ11 DQ15
37 38
DDR_D16 VSS13 VSS14 DDR_D20
39 40
+1.5V DDR_D17 DQ16 DQ20 DDR_D21
41 42
DQ17 DQ21
43 44
DDR_DQS#2 VSS15 VSS16 DDR_DM2
45 46
DQS#2 DM2
1

DDR_DQS2 47 48
RD12 DQS2 VSS17 DDR_D22
49 VSS18 DQ22 50
DDR_D18 51 52 DDR_D23
1K_0402_1% DDR_D19 DQ18 DQ23
53 DQ19 VSS19 54
55 56 DDR_D28
2

DDR_D24 VSS20 DQ28 DDR_D29


+VREF_CA 57 DQ24 DQ29 58
DDR_D25 59 60
DQ25 VSS21
1

61 62 DDR_DQS#3
RD11 DDR_DM3 VSS22 DQS#3 DDR_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
1K_0402_1% DDR_D26 67 68 DDR_D30
DDR_D27 DQ26 DQ30 DDR_D31
69 70
2

DQ27 DQ31
71 VSS25 VSS26 72

<8,11> DDR_CKE0 73 CKE0 CKE1 74 DDR_CKE1 <8,11>


75 VDD1 VDD2 76
77 78 DDR_MA15
NC1 A15 DDR_MA14
<8,11> DDR_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
C +1.5V DDR_MA12 DDR_MA11 C
83 A12/BC# A11 84
DDR_MA9 85 86 DDR_MA7
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z A9 A7
87 VDD5 VDD6 88
2 2 2 2 2 2 2 2 2 2 2 2 DDR_MA8 89 90 DDR_MA6
DDR_MA5 A8 A6 DDR_MA4
91 A5 A4 92
CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 CD11 CD12 CD13 CD14 93 94
DDR_MA3 VDD7 VDD8 DDR_MA2
95 A3 A2 96
1 1 1 1 1 1 1 1 1 1 1 1 DDR_MA1 97 98 DDR_MA0
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z A1 A0
99 100
VDD9 VDD10
<8> DDR_A_CLK0 101 102 DDR_A_CLK1 <8>
CK0 CK1
<8> DDR_A_CLK0# 103 104 DDR_A_CLK1# <8>
CK0# CK1#
105 106
DDR_MA10 VDD11 VDD12
107 108 DDR_BS1 <8,11>
A10/AP BA1
<8,11> DDR_BS0 109 110 DDR_RAS# <8,11>
BA0 RAS#
111 112
VDD13 VDD14
<8,11> DDR_WE# 113 114 DDR_A_CS0# <8>
WE# S0#
<8,11> DDR_CAS# 115 116 DDR_A_ODT0 <8>
CAS# ODT0
117 118
DDR_MA13 VDD15 VDD16 +VREF_CA
119 120 DDR_A_ODT1 <8>
A13 ODT1
<8> DDR_A_CS1# 121 122
S1# NC2
123 124
VDD17 VDD18
CRB 0.1u X1 4.7u X1 CRB 100U X2 125
127
NCTEST VREF_CA
126
128
DDR_D32 VSS27 VSS28 DDR_D36
129 130 1 1
+1.5V DDR_D33 DQ32 DQ36 DDR_D37 CD15
131 132
+0.75VS DQ33 DQ37 CD16
133 134
DDR_DQS#4 VSS29 VSS30 DDR_DM4 1000P_0402_50V7K 0.1U_0402_16V4Z
135 136
DDR_DQS4 DQS#4 DM4 2 2
137 138
DQS4 VSS31
220U_B2_2.5VM_R35
0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

139 140 DDR_D38


DDR_D34 VSS32 DQ38 DDR_D39
2 2 1 1 141 142
DQ34 DQ39
CD17

CD18

CD19

DDR_D35 143 144


+ DQ35 VSS33
CD20

145 146 DDR_D44


B DDR_D40 VSS34 DQ44 DDR_D45 B
147 148
1 1 2 DDR_D41 DQ40 DQ45
149 150
2 DQ41 VSS35 DDR_DQS#5
151 152
DDR_DM5 VSS36 DQS#5 DDR_DQS5
153 154
DM5 DQS5
155 156
DDR_D42 VSS37 VSS38 DDR_D46
157 158
DDR_D43 DQ42 DQ46 DDR_D47
159 160
DQ43 DQ47
161 162
DDR_D48 VSS39 VSS40 DDR_D52
Place near JDIMM1 163
DQ48 DQ52
164
DDR_D49 165 166 DDR_D53
DQ49 DQ53
167 168
DDR_DQS#6 VSS41 VSS42 DDR_DM6
169 170
DDR_DQS6 DQS#6 DM6
171 172
DQS6 VSS43 DDR_D54
173 174
DDR_D50 VSS44 DQ54 DDR_D55
175 176
DDR_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_D60
179 180
DDR_D56 VSS46 DQ60 DDR_D61
181 182
DDR_D57 DQ56 DQ61
183 184
DQ57 VSS47 DDR_DQS#7
185 186
DDR_DM7 VSS48 DQS#7 DDR_DQS7
187 188
DM7 DQS7
189 190
DDR_D58 VSS49 VSS50 DDR_D62
191 192
DDR_D59 DQ58 DQ62 DDR_D63
193 194
DQ59 DQ63
195 196
RD5 VSS51 VSS52
1 2 10K_0402_5% 197
SA0 EVENT#
198 DDR_EVENT# <8,11>
+3VS 199 200 SMB_FCH_DA0 <11,14>
VDDSPD SDA
201 202 SMB_FCH_CK0 <11,14>
SA1 SCL
1 1 203 204 +0.75VS
VTT1 VTT2
1

CD21 CD22 205


G1
4mm G2
206
2.2U_0603_6.3V6K 0.1U_0402_16V4Z RD6
A 2 2 10K_0402_5% FOX_AS0A626-U4RN-7F A
SP07000J500
CONN@
2

REVERSE TYPE
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/31 Deciphered Date 2011/07/31 Title
DDRIII-SODIMM A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-7161P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 05, 2011 Sheet 10 of 43
5 4 3 2 1
5 4 3 2 1

+1.5V +1.5V
JDIMMB
+VREF_DQ 1 VREF_DQ VSS1 2
3 4 DDR_D4
DDR_D0 VSS2 DQ4 DDR_D5
5 DQ0 DQ5 6
1 1 DDR_D1 7 8
CD24 CD23 DQ1 VSS3 DDR_DQS#0
9 VSS4 DQS#0 10
DDR_DM0 11 12 DDR_DQS0
1000P_0402_50V7K 0.1U_0402_16V4Z DM0 DQS0
<8,10> DDR_DQS#[0..7] 13 VSS5 VSS6 14
2 2 DDR_D2 15 16 DDR_D6
DDR_D3 DQ2 DQ6 DDR_D7
<8,10> DDR_D[0..63] 17 18
DQ3 DQ7
19 20
DDR_D8 VSS7 VSS8 DDR_D12
<8,10> DDR_DM[0..7] 21 22
D DDR_D9 DQ8 DQ12 DDR_D13 D
23 24
DQ9 DQ13
<8,10> DDR_DQS[0..7] 25 26
DDR_DQS#1 VSS9 VSS10 DDR_DM1
27 28
DDR_DQS1 DQS#1 DM1
<8,10> DDR_MA[0..15] 29 30 DDR_RST# <8,10>
DQS1 RESET#
31 32
DDR_D10 VSS11 VSS12 DDR_D14
33 34
DDR_D11 DQ10 DQ14 DDR_D15
35 36
DQ11 DQ15
37 38
DDR_D16 VSS13 VSS14 DDR_D20
39 40
DDR_D17 DQ16 DQ20 DDR_D21
41 42
DQ17 DQ21
43 44
DDR_DQS#2 VSS15 VSS16 DDR_DM2
45 DQS#2 DM2 46
DDR_DQS2 47 48
DQS2 VSS17 DDR_D22
49 VSS18 DQ22 50
DDR_D18 51 52 DDR_D23
DDR_D19 DQ18 DQ23
53 DQ19 VSS19 54
55 56 DDR_D28
DDR_D24 VSS20 DQ28 DDR_D29
57 DQ24 DQ29 58
DDR_D25 59 60
DQ25 VSS21 DDR_DQS#3
61 VSS22 DQS#3 62
DDR_DM3 63 64 DDR_DQS3
DM3 DQS3
65 VSS23 VSS24 66
DDR_D26 67 68 DDR_D30
DDR_D27 DQ26 DQ30 DDR_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

<8,10> DDR_CKE0 73 CKE0 CKE1 74 DDR_CKE1 <8,10>


75 VDD1 VDD2 76
77 78 DDR_MA15
NC1 A15 DDR_MA14
<8,10> DDR_BS2 79 BA2 A14 80
C C
81 VDD3 VDD4 82
DDR_MA12 83 84 DDR_MA11
DDR_MA9 A12/BC# A11 DDR_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_MA8 89 90 DDR_MA6
DDR_MA5 A8 A6 DDR_MA4
91 A5 A4 92
93 VDD7 VDD8 94
+1.5V DDR_MA3 95 96 DDR_MA2
DDR_MA1 A3 A2 DDR_MA0
97 98
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z A1 A0
99 100
VDD9 VDD10
2 2 2 2 2 2 2 2 2 2 2 2 <8> DDR_B_CLK0 101 102 DDR_B_CLK1 <8>
CK0 CK1
<8> DDR_B_CLK0# 103 104 DDR_B_CLK1# <8>
CD25 CD26 CD27 CD28 CD29 CD30 CD31 CD32 CD33 CD34 CD35 CD36 CK0# CK1#
105 106
DDR_MA10 VDD11 VDD12
0.1U_0402_16V4Z 107 108 DDR_BS1 <8,10>
1 1 1 1 1 1 1 1 1 1 1 1 A10/AP BA1
<8,10> DDR_BS0 109 110 DDR_RAS# <8,10>
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z BA0 RAS#
111 112
VDD13 VDD14
<8,10> DDR_WE# 113 114 DDR_B_CS0# <8>
WE# S0#
<8,10> DDR_CAS# 115 116 DDR_B_ODT0 <8>
CAS# ODT0
117 118
DDR_MA13 VDD15 VDD16
119 120 DDR_B_ODT1 <8>
A13 ODT1 +VREF_CA
<8> DDR_B_CS1# 121 122
S1# NC2
CRB 0.1u X1 4,7uX1 123
125
VDD17 VDD18
124
126
NCTEST VREF_CA
127 128
DDR_D32 VSS27 VSS28 DDR_D36
129 130 1 1
+0.75VS DDR_D33 DQ32 DQ36 DDR_D37 CD37 CD38
131 132
DQ33 DQ37 1000P_0402_50V7K 0.1U_0402_16V4Z
133 134
VSS29 VSS30
0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

DDR_DQS#4 135 136 DDR_DM4


DDR_DQS4 DQS#4 DM4 2 2
2 2 1 137 138
DQS4 VSS31 DDR_D38
139 140
VSS32 DQ38
CD39

CD40

CD41

DDR_D34 141 142 DDR_D39


DDR_D35 DQ34 DQ39
143 144
B 1 1 2 DQ35 VSS33 DDR_D44 B
145 146
DDR_D40 VSS34 DQ44 DDR_D45
147 148
DDR_D41 DQ40 DQ45
149 150
DQ41 VSS35 DDR_DQS#5
151 152
DDR_DM5 VSS36 DQS#5 DDR_DQS5
153 154
DM5 DQS5
155 156
DDR_D42 VSS37 VSS38 DDR_D46
157 158
DDR_D43 DQ42 DQ46 DDR_D47
Place near JDIMM2 159
DQ43 DQ47
160
161 162
DDR_D48 VSS39 VSS40 DDR_D52
163 164
DDR_D49 DQ48 DQ52 DDR_D53
165 166
DQ49 DQ53
167 168
DDR_DQS#6 VSS41 VSS42 DDR_DM6
169 170
DDR_DQS6 DQS#6 DM6
171 172
DQS6 VSS43 DDR_D54
173 174
DDR_D50 VSS44 DQ54 DDR_D55
175 176
DDR_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_D60
179 180
DDR_D56 VSS46 DQ60 DDR_D61
181 182
DDR_D57 DQ56 DQ61
183 184
DQ57 VSS47 DDR_DQS#7
185 186
DDR_DM7 VSS48 DQS#7 DDR_DQS7
187 188
DM7 DQS7
189 190
DDR_D58 VSS49 VSS50 DDR_D62
191 192
DDR_D59 DQ58 DQ62 DDR_D63
193 194
DQ59 DQ63
195 196
RD9 VSS51 VSS52
1 2 10K_0402_5% 197
SA0 EVENT#
198 DDR_EVENT# <8,10>
+3VS 199 200 SMB_FCH_DA0 <10,14>
VDDSPD SDA
1 2 201
SA1 SCL
202 SMB_FCH_CK0 <10,14>
1 1 RD10 10K_0402_5% 203 204 +0.75VS
VTT1 VTT2
CD42 CD43 205
4mm 206
A 2.2U_0603_6.3V6K G1 G2 A
2 2 0.1U_0402_16V4Z FOX_AS0A626-U8RN-7F DC020811210
CONN@

REVERSE TYPE
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/31 Deciphered Date Title
DDRIII-SODIMM B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-7161P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 05, 2011 Sheet 11 of 43
5 4 3 2 1
5 4 3 2 1

0.01U_0402_16V7K UF1B
SATA_STX_DRX_P0 2 1 CF5 SATA_STX_DRX_P0_C AH9 AH28
<27> SATA_STX_DRX_P0 SATA_STX_DRX_N0 SATA_STX_DRX_N0_C SATA_TX0P FC_CLK
2 1 CF6 AJ9 AG28
<27> SATA_STX_DRX_N0 0.01U_0402_16V7K SATA_TX0N FC_FBCLKOUT
HDD SATA_SRX_DTX_N0 FC_FBCLKIN AF26
<27> SATA_SRX_DTX_N0 AJ8 SATA_RX0N
SATA_SRX_DTX_P0 AH8 AF28
<27> SATA_SRX_DTX_P0 SATA_RX0P FC_OE_L/GPIOD145
FC_AVD_L/GPIOD146 AG29
AH10 SATA_TX1P FC_WE_L/GPIOD148 AG26
AJ10 SATA_TX1N FC_CE1_L/GPIOD149 AF27
FC_CE2_L/GPIOD150 AE29
AG10 AF29
SATA_RX1N FC_INT1/GPIOD144
AF10 AH27
SATA_RX1P FC_INT2/GPIOD147

GPIOD
D D
AG12 AJ27
SATA_TX2P FC_ADQ0/GPIOD128
AF12 AJ26
SATA_TX2N FC_ADQ1/GPIOD129
AH25
FC_ADQ2/GPIOD130
AJ12 AH24
SATA_RX2N FC_ADQ3/GPIOD131

SERIAL ATA
AH12 AG23
SATA_RX2P FC_ADQ4/GPIOD132
AH23
FC_ADQ5/GPIOD133
AH14 AJ22
SATA_TX3P FC_ADQ6/GPIOD134
AJ14 AG21
SATA_TX3N FC_ADQ7/GPIOD135
AF21
FC_ADQ8/GPIOD136
AG14 AH22
SATA_RX3N FC_ADQ9/GPIOD137
AF14 AJ23
SATA_RX3P FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139 AF23
AG17 SATA_TX4P FC_ADQ12/GPIOD140 AJ24
AF17 SATA_TX4N FC_ADQ13/GPIOD141 AJ25
FC_ADQ14/GPIOD142 AG25
AJ17 SATA_RX4N FC_ADQ15/GPIOD143 AH26
AH17 SATA_RX4P
AJ18 SATA_TX5P

HW MONITOR
AH18 SATA_TX5N FANOUT0/GPIO52 W5
FANOUT1/GPIO53 W6
AH19 SATA_RX5N FANOUT2/GPIO54 Y9
AJ19 SATA_RX5P
FANIN0/GPIO56 W7
FANIN1/GPIO57 V9
+1.1VS 1 RF5 2 1K_0402_1% SATA_CALRP AB14 W8
SATA_CALRN SATA_CALRP FANIN2/GPIO58
1 RF6 2 931_0402_1% AA14 SATA_CALRN
B6 RF7 1 2 10K_0402_5%
10K_0402_5% 2 TEMPIN0/GPIO171
+3VS 1 RF8 TEMPIN1/GPIO172 A6 RF9 1 2 10K_0402_5%
SATA_ACT#_R AD11 A5 RF10 1 2 10K_0402_5%
<26> SATA_ACT#_R SATA_ACT_L/GPIO67 TEMPIN2/GPIO173
TEMPIN3/TALERT_L/GPIO174 B5 APU_ALERT#_FCH <7>
TEMP_COMM C7
C C
SATA_X1 A3 RF12 1 2 10K_0402_5% RF13 1 2 10K_0402_5%
VIN0/GPIO175 RF14 10K_0402_5%
AD16 SATA_X1 VIN1/GPIO176 B4 1 2
2

A4 RF16 1 2 10K_0402_5%
@ RF15 VIN2/GPIO177 RF17 10K_0402_5%
VIN3/GPIO178 C5 1 2
1M_0402_5% A7 RF18 1 2 10K_0402_5%
VIN4/GPIO179
VIN5/GPIO180 B7
25MHZ_20PF_7A25000012 B8 RF20 1 @ 2 10K_0402_5%
1

SATA_X2 VIN6/GBE_STAT3/GPIO181 RF21 1


AC16
SATA_X2 VIN7/GBE_LED3/GPIO182
A8 2 10K_0402_5%
@ YF2
1 2

SPI ROM
1 1
FCH_SPI_DI J5 G27
@ CF7 @ CF8 FCH_SPI_DO SPI_DI/GPIO164 NC1
E2 Y2
FCH_SPI_CLK SPI_DO/GPIO163 NC2
22P_0402_50V8J 22P_0402_50V8J K4
2 2 FCH_SPI_CS1# SPI_CLK/GPIO162
K9
SPI_CS1_L/GPIO165
G2
PAD TF1 ROM_RST_L/GPIO161
218-0792006 A13-HUDSON-M1_FCBGA605 A31!

B B

+3VS For RF
UF24
FCH_SPI_CS1# 1 8 RF22 10K_0402_5% FCH_SPI_CLK 2 1 FCH_SPI_CLK_R
FCH_SPI_DI CS# VCC RF27 0_0402_5%
2 7 1 2 1
SO HOLD#
0.1U_0402_16V7K

+3VS 1 2 3 6 FCH_SPI_CLK_R
RF23 WP# SCLK FCH_SPI_DO CF9
4 5
10K_0402_5% GND SI
2 1
MX25L1606EM2I-12G_SO8
CF80
SA000041N00 2
33P_0402_50V8J

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/31 Deciphered Date Title
SATA,SPI,GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-7161P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 05, 2011 Sheet 12 of 43
5 4 3 2 1
5 4 3 2 1

Need confirm with BIOS +1.8VS +3VS

150P_0402_50V8J
CF77 1 2

1
PCIE_RST# RF48 2 1 33_0402_5% PCIE_RST#_R RF24
10K_0402_5%
150P_0402_50V8J

2
G
CF10 1 2 UF1E

2
P1 PCIE_RST_L PCICLK0 W2 PAD TF3

PCI CLKS
A_RST# RF25 2 1 33_0402_5% L1 W1 PCICLK1 <16> APU_PWRGD 3 1 APU_PWRGD_CORE <40>
A_RST_L PCICLK1/GPO36

D
W3 PCICLK2 <16>
UMI_C_RXP0 CF16 0.1U_0402_16V7K UMI_RXP0 PCICLK2/GPO37
1 2 AD26 W4 PCICLK3 <16>
UMI_C_RXN0 CF11 0.1U_0402_16V7K UMI_RXN0 UMI_TX0P PCICLK3/GPO38
1 2 AD27
UMI_TX0N PCICLK4/14M_OSC/GPO39
Y1 PCICLK4 <16>
UMI_C_RXP1 CF12 0.1U_0402_16V7K UMI_RXP1 QF2
D
1 2 AC28
UMI_TX1P D
<8> UMI_C_RXP[0..3] UMI_C_RXN1 CF17 1 2 0.1U_0402_16V7K UMI_RXN1 AC29 V2 PAD TF4 FDV301N_NL_SOT23-3~D
UMI_C_RXP2 CF18 0.1U_0402_16V7K UMI_RXP2 UMI_TX1N PCIRST_L
<8> UMI_C_RXN[0..3] 1 2 AB29
UMI_TX2P
UMI_C_RXN2 CF13 1 2 0.1U_0402_16V7K UMI_RXN2 AB28
UMI_C_RXP3 CF14 0.1U_0402_16V7K UMI_RXP3 UMI_TX2N
1 2 AB26 AA1
UMI_C_RXN3 CF15 0.1U_0402_16V7K UMI_RXN3 UMI_TX3P AD0/GPIO0
1 2 AB27
UMI_TX3N AD1/GPIO1
AA4 Link to Power IC

PCI EXPRESS I/F


AA3
UMI_C_TXP0 AD2/GPIO2
AE24 AB1
UMI_C_TXN0 UMI_RX0P AD3/GPIO3
AE23 AA5
UMI_C_TXP1 UMI_RX0N AD4/GPIO4
AD25 AB2
UMI_C_TXN1 UMI_RX1P AD5/GPIO5
<8> UMI_C_TXP[0..3] AD24 AB6
UMI_C_TXP2 UMI_RX1N AD6/GPIO6
<8> UMI_C_TXN[0..3] AC24 AB5
UMI_C_TXN2 UMI_RX2P AD7/GPIO7
AC25 AA6
UMI_C_TXP3 UMI_RX2N AD8/GPIO8
AB25 AC2
UMI_C_TXN3 UMI_RX3P AD9/GPIO9
AB24 AC3
UMI_RX3N AD10/GPIO10
AC4
RF26 1 PCIE_CALRP AD11/GPIO11
2 590_0402_1% AD29
PCIE_CALRP AD12/GPIO12
AC1
RF28 1 2 2K_0402_1% PCIE_CALRN AD28 AD1
+1.1VS PCIE_CALRN AD13/GPIO13
AD2
AD14/GPIO14
AA28 AC6
GPP_TX0P AD15/GPIO15
AA29 AE2
GPP_TX0N AD16/GPIO16
Y29 AE1
GPP_TX1P AD17/GPIO17
Y28 AF8
GPP_TX1N AD18/GPIO18
Y26 AE3
GPP_TX2P AD19/GPIO19
Y27 AF1
GPP_TX2N AD20/GPIO20
W28 AG1
GPP_TX3P AD21/GPIO21
W29 AF2
GPP_TX3N AD22/GPIO22 PCI_AD23
AE9 PCI_AD23 <16>
AD23/GPIO23 PCI_AD24
AA22 AD9 PCI_AD24 <16>
GPP_RX0P AD24/GPIO24

PCI I/F
Y21 AC11 PCI_AD25
GPP_RX0N AD25/GPIO25 PCI_AD25 <16>
AA25 AF6 PCI_AD26
GPP_RX1P AD26/GPIO26 PCI_AD26 <16>
AA24 AF4 PCI_AD27
GPP_RX1N AD27/GPIO27 PCI_AD27 <16>
W23 AF3
GPP_RX2P AD28/GPIO28
V24 AH2
GPP_RX2N AD29/GPIO29
W24 AG2
GPP_RX3P AD30/GPIO30
W25 AH3
GPP_RX3N AD31/GPIO31
AA8
CBE0_L
AD5
CBE1_L
AD8
CBE2_L
AA10
CBE3_L
C AE8 C
FRAME_L
AB9
DEVSEL_L
M23 AJ3
PCIE_RCLKP/NB_LNK_CLKP IRDY_L
P23 AE7
PCIE_RCLKN/NB_LNK_CLKN TRDY_L
AC5
RF33 2 CLK_APU_DP_R PAR
<7> CLK_APU_DP 1 0_0402_5% U29
NB_DISP_CLKP STOP_L
AF5
<7> CLK_APU_DP# RF34 2 1 0_0402_5% CLK_APU_DP#_R U28 AE6
NB_DISP_CLKN PERR_L
AE4
SERR_L
T26 AE11
NB_HT_CLKP REQ0_L
T27 AH5
NB_HT_CLKN REQ1_L/GPIO40
AH4
RF35 2 CLK_APU_R REQ2_L/CLK_REQ8_L/GPIO41
<7> CLK_APU 1 0_0402_5% V21 AC12 PAD TF12
RF36 2 CLK_APU#_R CPU_HT_CLKP REQ3_L/CLK_REQ5_L/GPIO42
<7> CLK_APU# 1 0_0402_5% T21 AD12
CPU_HT_CLKN GNT0_L
AJ5
GNT1_L/GPO44
V23 AH6
SLT_GFX_CLKP GNT2_L/GPO45
T23 AB12 PAD TF13
SLT_GFX_CLKN GNT3_L/CLK_REQ7_L/GPIO46 RF11 1
AB11 2 10K_0402_5%
RF37 1 CLK_PCIE_LAN_P_R CLKRUN_L
2 0_0402_5% L29 AD7
<21> CLK_PCIE_LAN_P RF38 1 CLK_PCIE_LAN_N_R GPP_CLK0P LOCK_L
2 0_0402_5% L28
GPP_CLK0N
<21> CLK_PCIE_LAN_N

CLOCK GENERATOR
AJ6
RF39 1 CLK_PCIE_WLAN_P_R INTE_L/GPIO32
2 0_0402_5% N29 AG6
<25> CLK_PCIE_WLAN_P RF40 1 CLK_PCIE_WLAN_N_R GPP_CLK1P INTF_L/GPIO33
2 0_0402_5% N28 AG4
<25> CLK_PCIE_WLAN_N GPP_CLK1N INTG_L/GPIO34
AJ4
RF41 1 CLK_PCIE_WWAN_P_R INTH_L/GPIO35
2 0_0402_5% M29
<25> CLK_PCIE_WWAN_P RF42 1 CLK_PCIE_WWAN_N_R GPP_CLK2P
2 0_0402_5% M28
GPP_CLK2N
<25> CLK_PCIE_WWAN_N RF43 1 2 0_0402_5% LPCCLK0 <16>
T25
GPP_CLK3P RF44
V25
GPP_CLK3N LPCCLK0
H24 1 2 22_0402_5% CLK_PCI_EC <17>

LPC
H25 CLK_DEBUG_PORT_R @ RF45 1 2 0_0402_5% CLK_DEBUG_PORT
LPCCLK1
L24 J27 LPC_LAD0 <17,25> RF45 footprint short
GPP_CLK4P LAD0
L23 J26 LPC_LAD1 <17,25>
GPP_CLK4N LAD1
H29 LPC_LAD2 <17,25>
LAD2
P25 H28 LPC_LAD3 <17,25>
GPP_CLK5P LAD3
M25 G28 LPC_LFRAME# <17,25>
GPP_CLK5N LFRAME_L
J25 CLK_DEBUG_PORT <16>
LDRQ0_L
P29 AA18
GPP_CLK6P LDRQ1_L/CLK_REQ6_L/GPIO49
P28 AB19
Place close to UF1 GPP_CLK6N SERIRQ/GPIO48 IRQ_SERIRQ <17>
CLK_DEBUG_PORT 1 2 CLK_DEBUG_PORT_1
CLK_DEBUG_PORT_1 <25>
RF Change to 33PF N26 @RF46
@ RF46 0_0402_5%
GPP_CLK7P
N27
B
CF20 33P_0402_50V8J GPP_CLK7N B
G21 APU_LDT_STP# <7>
ALLOW_LDTSTP/DMA_ACTIVE_L
CPU

2 1 T29 H21 FCH_PROCHOT# <7>


GPP_CLK8P PROCHOT_L
T28 K19 APU_PWRGD <7>
GPP_CLK8N LDT_PG
G22
RF47 LDT_STP_L
J24 LDT_RST# <7>
CLK_48M 2 CLK_48M_R LDT_RST_L
1 33_0402_5% L25
<22> CLK_48M 14M_25M_48M_OSC
Close to SB
C1 FCH_RTCX1
32K_X1 CF24
RTC

2 1 XTAL25_IN L26 C2 FCH_RTCX2 22P_0402_50V8J


25M_X1 32K_X2 FCH_RTCX1
2 1
1

CF21 1M_0402_5% D2 SUSCLK <17>


RTCCLK
1

22P_0402_50V8J YF1 B2 XF1


INTRUDER_ALERT_L

2
RF49 XTAL25_OUT L27 B1 +RTCVCC_R RF50 1 2 510_0402_5% +RTCVCC 3 4
22P_0402_50V8J 25M_X2 VDDBT_RTC_G W=20mils NC OSC RF51
CF22 1 2 1 20M_0603_5%
2

NC OSC

1
2 1 218-0792006 A13-HUDSON-M1_FCBGA605 A31! CF23
25MHZ_20PF_7A25000012 1U_0402_6.3V4Z CMOS1 @

1
SHORT PADS 32.768KHZ_12.5PF_9H03200413 CF25

2
2 2 1 FCH_RTCX2
for Clear CMOS
22P_0402_50V8J

SUSCLK

CF19 1
0.1U_0402_16V7K +3VALW
it can be swap if need @ CF83
2 1 10P_0402_50V8J
2
5

A A
PCIE_RST# 2 UF25 RF reserved
P

B
Y 4 PLT_RST# PLT_RST# <17,21,25>
A_RST# 1 A
G

NC7SZ08P5X_NL_SC70-5
3
1
100K_0402_5%

RF31
@ RF32 2 1 0_0402_5%
2

@ Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/31 Deciphered Date Title
UMI,PCIE,CLK,PCI,LPC,RTC,CPU

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 13 of 43
5 4 3 2 1
5 4 3 2 1

UF1A

+3VALW

USB MISC
J2 A10 PAD TF7
PCI_PME_L/GEVENT4_L USBCLK/14M_25M_48M_OSC

ACPI/WAKE UP EVENTS
K1 RI_L/GEVENT22_L
1 2 USB_OC2# D3 G19 USB_PCOMP 1 RF58 2 11.8K_0402_1%
RF57 10K_0402_5% SIO_SLP_S3# SPI_CS3_L/GBE_STAT1/GEVENT21_L USB_RCOMP
<17> SIO_SLP_S3# F1 SLP_S3_L
1 2 USB_OC1# <17> SIO_SLP_S5# SIO_SLP_S5# H1
RF52 10K_0402_5% PBTN_OUT# SLP_S5_L
<17> PBTN_OUT# F2 PWR_BTN_L
1 2 USB_OC0# EC_FCH_PWROK H5
<17> EC_FCH_PWROK PWR_GOOD

USB 1.1
RF59 10K_0402_5% G6 J10
FCH_SIC SUS_STAT_L USB_FSD1P/GPIO186
1 2 TF8 PAD B3 H11
RF53 10K_0402_5% TEST0 USB_FSD1N
TF5 PAD C4 TEST1/TMS
1 2 FCH_SID F6 H9
TF6 PAD TEST2 USB_FSD0P/GPIO185
RF60 10K_0402_5% GATEA20 AD21 J8
<17> GATEA20 GA20IN/GEVENT0_L USB_FSD0N
D 1 2 PCIE_WAKE# KB_RST# AE21 D
<17> KB_RST# KBRST_L/GEVENT1_L
RF61 10K_0402_5% SIO_EXT_SCI# K2 B12
<17> SIO_EXT_SCI# LPC_PME_L/GEVENT3_L USB_HSD13P
SIO_EXT_SMI# J29 A12
<17> SIO_EXT_SMI# LPC_SMI_L/GEVENT23_L USB_HSD13N
H2 GEVENT5_L
1 2 EC_LID_OUT# J1 F11
RF55 10K_0402_5% PAD TF9 PCIE_WAKE# SYS_RESET_L/GEVENT19_L USB_HSD12P
<17,21,25> PCIE_WAKE# H6 WAKE_L/GEVENT8_L USB_HSD12N E11
1 2 GBE_PHY_INTR F3
RF62 10K_0402_5% IR_RX1/GEVENT20_L
<7> APU_THERMTRIP# J6 THRMTRIP_L/SMBALERT_L/GEVENT2_L USB_HSD11P E14
1 2 GBE_MDIO NB_PWRGD AC19 E12
RF63 10K_0402_5% NB_PWRGD USB_HSD11N
EC_RSMRST# G1 J12
<17> EC_RSMRST# RSMRST_L USB_HSD10P
USB_HSD10N J14
AD19 CLK_REQ4_L/SATA_IS0_L/GPIO64
AA16 A13 USB20_P9 <20>
+3VS CLK_REQ3_L/SATA_IS1_L/GPIO63 USB_HSD9P
AB21
SMARTVOLT1/SATA_IS2_L/GPIO50 USB_HSD9N
B13 USB20_N9 <20> Camera
<21> CLKREQ_LAN# CLKREQ_LAN# AC18
CLK_REQ0_L/SATA_IS3_L/GPIO60
AF20 D13 USB20_P8 <22>
SATA_IS4_L/FANOUT3/GPIO55 USB_HSD8P
AE19
SATA_IS5_L/FANIN3/GPIO59 USB_HSD8N
C13 USB20_N8 <22> Card Reader
1 2 CLKREQ_LAN# <24> FCH_SPKR FCH_SPKR AF19
SPKR_GPIO66

GPIO

USB 2.0
RF64 10K_0402_5% <10,11> SMB_FCH_CK0 SMB_FCH_CK0 AD22 G12
CLKREQ_WLAN# SMB_FCH_DA0 SCL0_GPIO43 USB_HSD7P
1 2 <10,11> SMB_FCH_DA0 AE22
SDA0_GPIO47 USB_HSD7N
G14
RF65 10K_0402_5% SMB_FCH_CK1 F5
NB_PWRGD SMB_FCH_DA1 SCL1_GPIO227
1 2 F4
SDA1_GPIO228 USB_HSD6P
G16
RF66 4.7K_0402_5% CLKREQ_WWAN# AH21 G18
<25> CLKREQ_WWAN# CLK_REQ2_L/FANIN4_GPIO62 USB_HSD6N
1 2 SMB_FCH_CK0 CLKREQ_WLAN# AB18
<25> CLKREQ_WLAN# CLK_REQ1_L/FANOUT4_GPIO61
RF67 2.2K_0402_5% E1 D16
IR_LED_L/LLB_L/GPIO184 USB_HSD5P USB20_P5 <25>
1 2 SMB_FCH_DA0 AJ21 C16 MiniCard- WWAN
SMARTVOLT2/SHUTDOWN_L/GPIO51 USB_HSD5N USB20_N5 <25>
RF68 2.2K_0402_5% H4
DDR3_RST_L/GEVENT7_L
D5 B14 USB20_P4 <25>
GBE_LED0/GPIO183 USB_HSD4P
D7
GBE_LED1/GEVENT9_L USB_HSD4N
A14 USB20_N4 <25> MiniCard- WLAN
G5
GBE_LED2/GEVENT10_L
K3 E18
PEG_CLKREQ#_R GBE_STAT0/GEVENT11_L USB_HSD3P
AA20 E16
CLK_REQG_L/GPIO65_OSCIN USB_HSD3N
1 2 SCL2 J16
USB_HSD2P USB20_P2 <23>
RF71 10K_0402_5% H3 J18 USB Port 2
BLINK/USB_OC7_L/GEVENT18_L USB_HSD2N USB20_N2 <23>

USB OC
1 2 SDA2 EC_LID_OUT# D1
<17> EC_LID_OUT# USB_OC6_L/IR_TX1/GEVENT6_L
C RF73 10K_0402_5% E4 B17 C
USB_OC5_L/IR_TX0/GEVENT17_L USB_HSD1P USB20_P1 <23>
1 2 GBE_COL D4 A17 USB Port 1 (Sub-board)
USB_OC4_L/IR_RX0/GEVENT16_L USB_HSD1N USB20_N1 <23>
RF74 10K_0402_5% E8
GBE_CRS PAD TF16 USB_OC3_L/AC_PRES/TDO/GEVENT15_L
1 2 <23> USB_OC2# F7 A16 USB20_P0 <26>
RF76 10K_0402_5% USB_OC2_L/TCK/GEVENT14_L USB_HSD0P
<23> USB_OC1# E7
USB_OC1_L/TDI/GEVENT13_L USB_HSD0N
B16 USB20_N0 <26> USB Port 0 (Sub-board)
1 2 GBE_RXERR F8
<23> USB_OC0# USB_OC0_L/TRST_L/GEVENT12_L
RF78 10K_0402_5%
1 @ 2 PEG_CLKREQ#_R
RF79 10K_0402_5%

HD AUDIO
1 2 SMB_FCH_CK1 <24> HDA_BITCLK RF70 1 2 33_0402_5% FCH_HDA_BITCLK M3 D25 SCL2
RF80 10K_0402_5% RF72 1 FCH_HDA_SDOUT AZ_BITCLK SCL2/GPIO193 SDA2
<24> HDA_SDOUT 2 33_0402_5% N1 F23
SMB_FCH_DA1 FCH_HDA_SDIN0 AZ_SDOUT SDA2/GPIO194
1 2 <24> FCH_HDA_SDIN0 L2 B26 FCH_SIC <7>
RF81 10K_0402_5% AZ_SDIN0/GPIO167 SCL3_LV/GPIO195
<16> FCH_HDA_SDOUT M2 E26 FCH_SID <7>
EC_RSMRST# AZ_SDIN1/GPIO168 SDA3_LV/GPIO196
1 2 M1
AZ_SDIN2/GPIO169 EC_PWM0/EC_TIMER0/GPIO197
F25
RF82 2.2K_0402_5% M4 E22
@ FCH_HDA_BITCLK RF75 1 FCH_HDA_SYNC AZ_SDIN3/GPIO170 EC_PWM1/EC_TIMER1/GPIO198
1 2 <24> HDA_SYNC 2 33_0402_5% N2
AZ_SYNC EC_PWM2/EC_TIMER2/GPIO199
F22 EC_PWM2 <16>
RF83 10K_0402_5% <24> HDA_RST# RF77 1 2 33_0402_5% FCH_HDA_RST# P2 E21 EC_PWM3 <16>
@ FCH_HDA_SDIN0 AZ_RST_L EC_PWM3/EC_TIMER3/GPIO200
1 2
RF84 10K_0402_5% G24
GBE_COL KSI_0/GPIO201
T1 G25
GBE_CRS GBE_COL KSI_1/GPIO202
T4 E28
GBE_CRS KSI_2/GPIO203

EMBEDDED CTRL
L6 E29
GBE_MDIO GBE_MDCK KSI_3/GPIO204
L5 D29
GBE_MDIO KSI_4/GPIO205
T9 D28
GBE_RXCLK KSI_5/GPIO206

GBE LAN
U1 C29
HDA_SYNC HDA_BITCLK GBE_RXD3 KSI_6/GPIO207
U3 C28
GBE_RXD2 KSI_7/GPIO208
T2
GBE_RXD1
1 1 U2 B28
GBE_RXD0 KSO_0/GPIO209
T5 A27
CF81 CF82 GBE_RXERR GBE_RXCTL/RXDV KSO_1/GPIO210
V5 B27
GBE_RXERR KSO_2/GPIO211
10P_0402_50V8J 33P_0402_50V8J P5 D26
2 2 GBE_TXCLK KSO_3/GPIO212
@ M5 A26
GBE_TXD3 KSO_4/GPIO213
RF Change to 33PF P9
GBE_TXD2 KSO_5/GPIO214
C26
T7 A24
GBE_TXD1 KSO_6/GPIO215
P7 B25
GBE_TXD0 KSO_7/GPIO216
M7 A25
GBE_TXCTL/TXEN KSO_8/GPIO217
P4 D24
GBE_PHY_PD KSO_9/GPIO218
B M9 B24 B
GBE_PHY_INTR GBE_PHY_RST_L KSO_10/GPIO219
RF reserved V7
GBE_PHY_INTR KSO_11/GPIO220
C24
B23
KSO_12/GPIO221
PAD TF14
E23 A23
PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222
E24 D22
PAD TF15 PS2_CLK/SCL4/GPIO188 KSO_14/GPIO223
F21 C22
SPI_CS2_L/GBE_STAT2/GPIO166 KSO_15/GPIO224
PAD TF11
G29 A22
FC_RST_L/GPO160 KSO_16/GPIO225
B22
AC_OK# KSO_17/GPIO226
D27
PS2KB_DAT/GPIO189
F28
PS2KB_CLK/GPIO190
F29
PS2M_DAT/GPIO191
E27
PS2M_CLK/GPIO192
1

D
ACIN 2 QF3 218-0792006 A13-HUDSON-M1_FCBGA605 A31!
<17,34> ACIN
G
S
3

SSM3K7002FU_SC70-3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/31 Deciphered Date 2011/07/31 Title

www.vinafix.vn
USB,GPIO,GLAN,HDA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-7161P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 05, 2011 Sheet 14 of 43
5 4 3 2 1
A B C D E

+3VS 42mA UF1C POWER 979.4mA +1.1VS

10U_0603_6.3V6M
0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K
AH1 VDDIO_33_PCIGP_1 VDDCR_11_1 N13
+1.1VS

CORE S0
22U_0805_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
1 2 2 2 V6 VDDIO_33_PCIGP_2 VDDCR_11_2 R15 1 1 1 1 1

PCI/GPIO I/O
CF34

CF27

CF35

CF36

CF28

CF37

CF29

CF38

CF39
Y19 VDDIO_33_PCIGP_3 VDDCR_11_3 N17
AE5 VDDIO_33_PCIGP_4 VDDCR_11_4 U13
AC21 VDDIO_33_PCIGP_5 VDDCR_11_5 U17
2 1 1 1 2 2 2 2 2

330U_D2_2.5VY_R9M
AA2 VDDIO_33_PCIGP_6 VDDCR_11_6 V12

10U_0603_6.3V6M
AB4 VDDIO_33_PCIGP_7 VDDCR_11_7 V18 1
AC8 VDDIO_33_PCIGP_8 VDDCR_11_8 W12 1

CF30

CF31
AA7 W18 +
VDDIO_33_PCIGP_9 VDDCR_11_9
AA9
VDDIO_33_PCIGP_10
GPIO I/F implemented: tied to +1.8V_S0 AF7
VDDIO_33_PCIGP_11
382.9mA
2 2

CLKGEN I/O
1 GPIO I/F not implemented: tied to +VDDAN_11_CLK LF1 2 1
AA19 K28 1 +1.1VS
+1.8VS VDDIO_33_PCIGP_12 VDDAN_11_CLK_1

22U_0805_6.3V6M
0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K
@ RF87 +1.8V_S0 or 0 ohm to ground K29 1 1 1 1 1
VDDAN_11_CLK_2

CF40

CF32

CF41

CF42

CF43
1 2 +VDDIO_18_FC J28 FBMA-L11-201209-221LMA30T_0805
VDDAN_11_CLK_3
0_0603_5% 0.16mA VDDAN_11_CLK_4
K26
1

0_0402_5%

FLASH I/O
0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K
footprint short 2 2 2 VDDAN_11_CLK_5
J21
2 2 2 2 2
RF88

CF44

CF33

CF45
AF22 J20
VDDIO_18_FC_1 VDDAN_11_CLK_6
AE25 K21
VDDIO_18_FC_2 VDDAN_11_CLK_7
AF24 J22
@ 1 1 1 VDDIO_18_FC_3 VDDAN_11_CLK_8
AC22
2

VDDIO_18_FC_4
V1
VDDRF_GBE_S
22.5mA VDDIO_33_GBE_S M10

2.2U_0603_6.3V6K
LF2

PCI EXPRESS
+3VS 2 1 +VDDPL33_PCIE AE28
FBMA-L11-160808-221LMT_2P VDDPL_33_PCIE
1

GBE LAN
CF46
1115.6mA
U26 VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1 L7
V22 VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2 L9
2 V26
+1.1VS LF3 +PCIE_VDDAN VDDAN_11_PCIE_3
V27 VDDAN_11_PCIE_4
22U_0805_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K
2 1 V28 VDDAN_11_PCIE_5 VDDIO_GBE_S_1 M6
1U_0402_6.3V6K

FBMA-L11-201209-221LMA30T_0805 V29 P8
VDDAN_11_PCIE_6 VDDIO_GBE_S_2
1 1 2 2 W22 VDDAN_11_PCIE_7
CF47

CF48

CF49

CF50

W26 VDDAN_11_PCIE_8
15.5mA
2 2 1 1

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K
3.3V_S5 I/O
SERIAL ATA
+VDDPL_33_SATA AD14 49.5mA
VDDPL_33_SATA
VDDIO_33_S_1 A21 +3VALW
+AVDD_SATA AJ20 D21 1 1
VDDAN_11_SATA_1 VDDIO_33_S_2

CF51

CF52
AF18 VDDAN_11_SATA_4 VDDIO_33_S_3 B21
2 1354.2mA 2
AH20 VDDAN_11_SATA_2 VDDIO_33_S_4 K10
AG19 VDDAN_11_SATA_3 VDDIO_33_S_5 L10
2 2
AE18 VDDAN_11_SATA_5 VDDIO_33_S_6 J9
AD18 VDDAN_11_SATA_6 VDDIO_33_S_7 T6
AE16 VDDAN_11_SATA_7 VDDIO_33_S_8 T8

1U_0402_6.3V6K

1U_0402_6.3V6K
+1.1VALW
1 1

CORE S5

CF53

CF54
LF4
VDDCR_11_S_1
F26 165.2mA
2 1 +AVDD_USB A18 G26
+3VALW VDDAN_33_USB_S_1 VDDCR_11_S_2
A19
VDDAN_33_USB_S_2
15.3mA
2 2
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

FBMA-L11-201209-221LMA30T_0805 534.5mA A20


VDDAN_33_USB_S_3 VDDIO_AZ_S
M8 +VDDIO_AZ
1 1 1 1 1 B18
VDDAN_33_USB_S_4
58mA

USB I/O

0.1U_0402_16V7K

0.1U_0402_16V7K
CF55

CF56

CF57

CF58

CF59

B19 A11 LF5


VDDAN_33_USB_S_5 VDDCR_11_USB_S_1

10U_0603_6.3V6M
B20 B11 +VDDCR_11_USB 2 1
VDDAN_33_USB_S_6 VDDCR_11_USB_S_2 +1.1VALW
C18 1 1 1 FBMA-L11-201209-221LMA30T_0805
2 2 2 2 2 VDDAN_33_USB_S_7

CF60

CF61

CF62
C20
VDDAN_33_USB_S_8
46.5mA
D18 M21 +VDDPL33
VDDAN_33_USB_S_9 VDDPL_33_SYS
D19
VDDAN_33_USB_S_10
65.3mA
2 2 2

PLL
D20 L22 +VDDPL11
VDDAN_33_USB_S_11 VDDPL_11_SYS_S
E19
VDDAN_33_USB_S_12
16.1mA
F19 +AVDD_USB
VDDPL_33_USB_S
LF6 11.4mA
0.1U_0402_16V7K
2.2U_0603_6.3V6K

+1.1VALW 2 1 +VDDAN_11_USB C11 D6 +VDDAN33_HWM


VDDAN_11_USB_S_1 VDDAN_33_HWM_S LF7
D11
FBMA-L11-160808-221LMT_2P VDDAN_11_USB_S_2 +VDDXL_33_S
1 2 L20 2 1 +3VS
VDDXL_33_S
CF63

CF64

2.2U_0603_6.3V6K
88.6mA 5mA 1

CF65
218-0792006 A13-HUDSON-M1_FCBGA605 A31! FBMA-L11-160808-221LMT_2P
2 1
2

3 3

+AVDD_SATA +VDDIO_AZ +3VALW


+VDDPL_33_SATA LF8
+1.5V
22U_0805_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K

LF9 +1.1VS 2 1 footprint short


1U_0402_6.3V6K

1U_0402_6.3V6K

+3VS 2 1 FBMA-L11-201209-221LMA30T_0805 1 2
FBMA-L11-160808-221LMT_2P 1 1 1 1 1 @ RF89 0_0603_5%
CF66

CF67

CF68

CF69

CF70

1 2
1 RF90 @ 0_0603_5%
CF71 1 2 2.2U_0603_6.3V6K
2 2 2 2 2 CF72
2.2U_0603_6.3V6K
2

+VDDPL11 +VDDAN33_HWM
For 3V AZ device
LF11
LF10 @
+1.1VALW 2 1 +3VALW 1 2
FBMA-L11-160808-221LMT_2P
0.1U_0402_16V7K
2.2U_0603_6.3V6K

0_0603_5%
CF73 1 2 2.2U_0603_6.3V6K footprint short
1 2
4 4
CF74

CF75

@ 2 1 AMD: balls used as GPIOs: Decoupled with at least one (1) 0.1-ȝF ceramic capacitor
+VDDPL33
LF13
+3VS 2 1
FBMA-L11-160808-221LMT_2P Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/31 Deciphered Date 2011/07/31 Title
CF76 1 2 2.2U_0603_6.3V6K AMD: HWM not Implemented or HWM balls used as GPIOs: Bead not used.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH PWR

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 15 of 43
A B C D E
5 4 3 2 1

UF1D
Y14 AJ2 +3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VALW +3VALW
VSSIO_SATA_1 VSS_1
Y16 VSSIO_SATA_2 VSS_2 A28
AB16 VSSIO_SATA_3 VSS_3 A2

1
AC14 VSSIO_SATA_4 VSS_4 E5
AE12 D23 RF91 RF92 RF93 RF94 RF95 RF96 @ RF97 RF98 RF99
VSSIO_SATA_5 VSS_5 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
AE14 VSSIO_SATA_6 VSS_6 E25
AF9 E6 @ @ @ @
VSSIO_SATA_7 VSS_7 @ @
AF11 F24

2
VSSIO_SATA_8 VSS_8
AF13 VSSIO_SATA_9 VSS_9 N15 <14> EC_PWM3
AF16 VSSIO_SATA_10 VSS_10 R13
AG8 R17
VSSIO_SATA_11 VSS_11 <14> EC_PWM2
AH7 T10
VSSIO_SATA_12 VSS_12
AH11 P10
D VSSIO_SATA_13 VSS_13 <13> PCICLK1 D
AH13 V11
VSSIO_SATA_14 VSS_14
AH16 U15
VSSIO_SATA_15 VSS_15 <13> PCICLK2
AJ7 M18
VSSIO_SATA_16 VSS_16
AJ11 V19
VSSIO_SATA_17 VSS_17 <13> PCICLK3
AJ13 M11
VSSIO_SATA_18 VSS_18
AJ16 L12
VSSIO_SATA_19 VSS_19 <13> PCICLK4

GND
L18
VSS_20
A9 J7
VSSIO_USB_1 VSS_21 <14> FCH_HDA_SDOUT
B10 P3
VSSIO_USB_2 VSS_22
K11 V4
VSSIO_USB_3 VSS_23 <13> LPCCLK0
B9 AD6
VSSIO_USB_4 VSS_24
D10 VSSIO_USB_5 VSS_25 AD4
<13> CLK_DEBUG_PORT
D12 VSSIO_USB_6 VSS_26 AB7
D14 VSSIO_USB_7 VSS_27 AC9
D17 VSSIO_USB_8 VSS_28 V8

1
E9 VSSIO_USB_9 VSS_29 W9
F9 W10 @ RF100 RF101 RF102 RF103 RF104 RF105 RF106 RF107 RF108
VSSIO_USB_10 VSS_30 2.2K_0402_5% 2.2K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
F12 VSSIO_USB_11 VSS_31 AJ28
F14 B29 @ @
VSSIO_USB_12 VSS_32
F16 U4

2
VSSIO_USB_13 VSS_33
C9 VSSIO_USB_14 VSS_34 Y18
G11 VSSIO_USB_15 VSS_35 Y10
F18 VSSIO_USB_16 VSS_36 Y12
D9 VSSIO_USB_17 VSS_37 Y11
H12 VSSIO_USB_18 VSS_38 AA11 Watchdog timer on NB_PWRGD
H14 VSSIO_USB_19 VSS_39 AA12 enable for pull-up
H16 VSSIO_USB_20 VSS_40 G4 disable for pull-down
H18 VSSIO_USB_21 VSS_41 J4
J11 G8 20100527
VSSIO_USB_22 VSS_42
J19 VSSIO_USB_23 VSS_43 G9
K12 VSSIO_USB_24 VSS_44 M12
K14 VSSIO_USB_25 VSS_45 AF25
C C
K16 H7
K18
VSSIO_USB_26
VSSIO_USB_27
VSS_46
VSS_47 AH29 Net Name Description
H19 VSSIO_USB_28 VSS_48 V10
VSS_49 P6


N4
Y4
VSS_50
L4 CLK_PCI_EC_R
0 : Integrated Microcontroller (IMC) Disabled
EFUSE VSS_51
VSS_52 L8
D8
VSSAN_HWM 1 : Integrated Microcontroller (IMC) Enabled
M19 M20
VSSXL VSSPL_SYS

P21
VSSIO_PCIECLK_1 VSSIO_PCIECLK_14
H23 EC_PWM3 EC_PWM2 ROM TYPE
P20 H26
VSSIO_PCIECLK_2 VSSIO_PCIECLK_15
M22 AA21 EC_PWM3

VSSIO_PCIECLK_3 VSSIO_PCIECLK_16
M24
VSSIO_PCIECLK_4 VSSIO_PCIECLK_17
AA23
x 0 SPI ROM
M26 AB23
VSSIO_PCIECLK_5 VSSIO_PCIECLK_18
P22 AD23
VSSIO_PCIECLK_6 VSSIO_PCIECLK_19
P24
VSSIO_PCIECLK_7 VSSIO_PCIECLK_20
AA26 x x Reserved
P26 AC26
VSSIO_PCIECLK_8 VSSIO_PCIECLK_21 @ RF109 2.2K_0402_5%
T20 Y20 2 1
VSSIO_PCIECLK_9 VSSIO_PCIECLK_22 <13> PCI_AD23
T22
VSSIO_PCIECLK_10 VSSIO_PCIECLK_23
W21 EC_PWM2 0 0 Reserved
T24 W20 @ RF110 2 1 2.2K_0402_5%
VSSIO_PCIECLK_11 VSSIO_PCIECLK_24 <13> PCI_AD24
V20 AE26
VSSIO_PCIECLK_12 VSSIO_PCIECLK_25
J23
VSSIO_PCIECLK_13 VSSIO_PCIECLK_26
L21
<13> PCI_AD25
@ RF111 2 1 2.2K_0402_5%
0 x LPC ROM
K20
VSSIO_PCIECLK_27 @ RF112 2.2K_0402_5%
2 1
<13> PCI_AD26
218-0792006 A13-HUDSON-M1_FCBGA605 A31! @ RF113 2 1 2.2K_0402_5%
<13> PCI_AD27 0 : External clock mode.
CLK_DEBUG_PORT
B 1 : Integrated clock mode. B

0 : Force PCIe interface at Gen I mode.


PCICLK1
Net Name Description 1 : PCIe interface is at Gen II mode.
0 : Bypass internal PLL clock 0 : Disable the boot fail timer function.
PCI_AD27 PCICLK2
1 : Use internal PLL-generated PLL CLK 1 : Enable the boot fail timer function.

0 : ILA auto run enable 0 : Disable Debug Straps.


PCI_AD26 PCICLK3
1 : ILA auto run disable 1 : Select external Debug Straps.

0 : Bypass internal FC Clk 0 : Required setting for integrated clock mode.


PCI_AD25 PCICLK4
1 : Use internal PLL FC Clk 1(('&+(&. 1 : Reserved.

A 0 : Getting the value from I2C EPROM 0 : Required setting for integrated clock mode. A

PCI_AD24 1(('&+(&. HDA_SDOUT_R


1 : Disable I2C ROM 1 : Reserved (Hudson-1 does not support
the lower power mode).
PCI_AD23
0 : Reserved
Security Classification Compal Secret Data Compal Electronics, Inc.

1 : Required setting (use ROMTYPE straps to Issued Date 2010/07/31 Deciphered Date 2011/07/31 Title
GND
determine the ROM type) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-7161P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 05, 2011 Sheet 16 of 43
5 4 3 2 1
A B C D E

LE1
CLK_PCI_EC +3VALW +3VALW +3VALW
+3VALW +EC_AVCC FBMA-L11-160808-601LMT_2P BOARD ID Table
For RF

2
2 1

1
@ RE2 RE34
10_0402_5% 1 1 1 1 1 1 Ra 100K_0402_5%

0.1U_0402_16V7K
CE2

0.1U_0402_16V7K
CE3

0.1U_0402_16V7K
CE4
47K_0402_5%

CE1
4.7U_0603_6.3V6K
CE5 CE6
RE8

1
1 0.1U_0402_16V7K 4.7U_0603_6.3V6K AD_BID

2
2 2 2 2 2 2

1
EC_RST# @ CE7 ECAGND 2 1 1
22P_0402_50V8J RE3 0_0402_5% @ RE35 CE26
2 18K_0402_5%
Rb
2

111
125
1 CE8 2 0.1U_0402_16V4Z 1

22
33
96

67

2
UE20

9
0.1U_0402_16V7K

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
1

<14> GATEA20
GATEA20 1
GA20/GPIO00 INVT_PWM/PWM1/GPIO0F
21 ID BOARD ID Ra Rb Vab
KB_RST# 2 23 BEEP#
<14> KB_RST# IRQ_SERIRQ 3
KBRST#/GPIO01 BEEP#/PWM2/GPIO10
26 USB_PWR_EN#
BEEP# <24>
USB_PWR_EN# <23>
0 0.1(X00) NC 0 0V
<13> IRQ_SERIRQ LPC_LFRAME# SERIRQ# FANPWM1/GPIO12 ACOFF
4 27
<13,25> LPC_LFRAME#
<13,25> LPC_LAD3 LPC_LAD3 5
LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF <33,34> 1 0.2(X01) 100K 8.2K 0.25V
LPC_LAD2 LAD3
+3VALW <13,25> LPC_LAD2 7 LAD2 PWM Output 2 0.3(X02) 100K 18K 0.50V
LPC_LAD1 8 63 BATT_TEMP
<13,25> LPC_LAD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <32>
LPC_LAD0 10 LAD0 LPC & MISC 64
3 1.0(A00) 100K NC 3.3V
1
@ RE14
2 EC_MUTE#
10K_0402_5%
<13,25> LPC_LAD0

<13> CLK_PCI_EC
CLK_PCI_EC
PLT_RST#
12 PCICLK AD Input
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD3/GPIO3B
65
66
ADP_I
AD_BID
MSEN#
ADP_I <34> *
<13,21,25> PLT_RST# 13 PCIRST#/GPIO05 AD4/GPIO42 75 MSEN# <19>
1 2 LID_SW# EC_RST# 37 76 VGATE
SIO_EXT_SCI# ECRST# SELIO2#/AD5/GPIO43 VGATE <40> +5VS
RE15 10K_0402_5% 20
KSO1 <14> SIO_EXT_SCI# SCI#/GPIO0E
1 2 38 CLKRUN#/GPIO1D
RE16 47K_0402_5% 68
KSO2 DAC_BRIG/DA0/GPIO3C EN_DFAN1
1 2 EN_DFAN1/DA1/GPIO3D 70 EN_DFAN1 <27>
RE17 47K_0402_5% DA Output 71 IREF
IREF/DA2/GPIO3E IREF <34>
1 2 MSEN# KSI0 55 72 CHGVADJ CHGVADJ <34>
KSI0/GPIO30 DA3/GPIO3F

1
RE31 10K_0402_5% KSI1 56
ACIN_EC KSI2 KSI1/GPIO31 ACIN RE9 RE10
1 2 57
RE32 150K_0402_5% KSI3 KSI2/GPIO32 EC_MUTE# 4.7K_0402_5%
58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE# <24> 4.7K_0402_5%

0.1U_0402_16V7K
KSI4 59 84 USB_EN#
KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# <23>
PLT_RST# KSI5 60 85 1

2
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C USB_DET#_DELAY
Change RE32 to 150K 61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 USB_DET#_DELAY <23>
CE9
KSI7 62 87 TP_CLK
KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK
2 39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_CLK <29>
2 CE25 KSO1 40 2 TP_DATA 2
+5VALW KSO2 KSO1/GPIO21 TP_DATA <29>
0.1U_0402_16V7K 41 KSO2/GPIO22
KSO3 42 97
EC_SMB_CK1 1 KSO4 KSO3/GPIO23 SDICS#/GPXOA00 EN_WOL#
1 2 43 KSO4/GPIO24 SDICLK/GPXOA01 98 EN_WOL# <28>
RE18 4.7K_0402_5% KSO5 44 KSO5/GPIO25 Int. K/B 99
1
RE19
2 EC_SMB_DA1
4.7K_0402_5% Place close to EC
KSO6
KSO7
45
46
KSO6/GPIO26 Matrix
KSO7/GPIO27 SPI Device Interface
SDIDO/GPXOA02
SDIDI/GPXID0 109 LID_SW#
LID_SW# <29> KEYBOARD CONN.
(For ESD request) KSO8 47
KSO9 KSO8/GPIO28 FRD#SPI_SO ACES_88514-2401
48 119
KSO10 KSO9/GPIO29 SPIDI/RD# FWR#SPI_SI
49 120 26 GND2
KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK
50
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
126 25 GND1
KSO12 51 128 FSEL#SPICS#
KSO13 KSO12/GPIO2C SPICS# KSO15
52 24
+3VS KSO14 KSO13/GPIO2D KSO10 24
53 23
KSO15 KSO14/GPIO2E WLAN_RADIO_OFF# KSO11 23
54 73 22
EC_SMB_CK2 KSO15/GPIO2F CIR_RX/GPIO40 PS_ID WLAN_RADIO_OFF# <25> KSO14 22
1 2 81 74 21
RE23 2.2K_0402_5% KSO16/GPIO48 CIR_RLC_TX/GPIO41 FSTCHG PS_ID <33> KSO13 21
82 89 FSTCHG <34> 20
EC_SMB_DA2 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 EN_INVPWR KSO12 20
1 2 BATT_CHGI_LED#/GPIO52
90 EN_INVPWR <20> 19
19
RE24 2.2K_0402_5% 91 PWRSHARE_OE# PWRSHARE_OE# <23> KSO3 18
EC_SMB_CK1 CAPS_LED#/GPIO53 BATT_LOW_LED# KSO6 18
<32> EC_SMB_CK1 77
SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54
92 BATT_LOW_LED# <26> 17
17
EC_SMB_DA1 78 93 LCD_TEST KSO8 16
<32> EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 LCD_TEST <20> 16
EC_SMB_CK2 79 SM Bus 95 SYSON KSO7 15
<7,21,25> EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON <38> 15
EC_SMB_DA2 80 121 VR_ON DE2 KSO4 14
<7,21,25> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <40> 14
127 ACIN_EC 2 1 ACIN KSO2 13
AC_IN/GPIO59 ACIN <14,34> KSI0 13
12
+3VS ON/OFF_EC# RB751V-40_SOD323-2 KSO1 12
11
SIO_SLP_S3# EC_RSMRST# KSO5 11
<14> SIO_SLP_S3# 6 100 EC_RSMRST# <14> 10
SIO_SLP_S5# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_LID_OUT# KSI3 10
<14> SIO_SLP_S5# 14 101 EC_LID_OUT# <14> 9
BT_RADIO_OFF# SIO_EXT_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_ON KSI2 9
1 2 2 <14> SIO_EXT_SMI# 15
EC_SMI#/GPIO08 EC_ON/GPXO05
102 EC_ON <29,35> 8
8
RE26 4.7K_0402_5% CE29 APU_ALERT# 16 103 KSO0 7
<7> APU_ALERT# BT_RADIO_OFF# LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_PWROK_FCH KSI5 7
0.1U_0402_16V7K 17 104 6
<25> BT_RADIO_OFF# SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# KSI4 6
3 1
18
PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08
105 BKOFF# <20> 5
5 3
19 GPIO 106 WWAN_RADIO_OFF# WWAN_RADIO_OFF# <25> KSO9 4
INVT_PWM EC_PME#/GPIO0D WL_OFF#/GPXO09 LCD_VCC_TEST_EN KSI6 4
<20> INVT_PWM 25 107 LCD_VCC_TEST_EN <20> 3
FAN_SPEED1 EC_THERM#/GPIO11 GPXO10 PSID_DISABLE# KSI7 3
<27> FAN_SPEED1 28 108 PSID_DISABLE# <33> 2
CAM_ON/OFF# FAN_SPEED1/FANFB1/GPIO14 GPXO11 KSI1 2
Place close to EC <20> CAM_ON/OFF# 29
FANFB2/GPIO15
1
1
(For ESD request) EC_TX 30
XCLKI <25> EC_TX EC_RX EC_TX/GPIO16
<25> EC_RX 31 110
ON/OFF_EC# EC_RX/GPIO17 PM_SLP_S4#/GPXID1 EC_ENBKL JKB1 CONN@
32 112 EC_ENBKL <20>
<29> ON/OFF_EC# PWR_LED# ON_OFF/GPIO18 ENBKL/GPXID2 EC_EAPD
<26> PWR_LED#
34
PWR_LED#/GPIO19 GPXID3
114 EC_EAPD <24> DC020906103
1 2 XCLKO 36 GPI 115
NUMLED#/GPIO1A GPXID4 SUSP#
116 SUSP# <28,39,41>
@ RE20 20M_0603_5% GPXID5 PBTN_OUT#
117 PBTN_OUT# <14>
GPXID6 PCIE_WAKE#
118 PCIE_WAKE# <14,21,25>
32.768KHZ_12.5P_1TJE125DP1A000M XCLKI GPXID7
122
XCLK1
1 2 <13> SUSCLK 1 @ 2 XCLKO 123 124 V18R KSI1 KSI0
R858 0_0402_5% XCLK0 V18R
1 1
AGND
GND
GND
GND
GND
GND

1 1 1 1
CE12 XE1 CE13 SUSCLK CE10 CE11
27P_0402_50V8J 27P_0402_50V8J @ CE20 @ CE21
1

2 2 KB926QFE0_LQFP128 0.1U_0402_16V7K 4.7U_0603_6.3V6K 22P_0402_50V8J 22P_0402_50V8J


11
24
35
94
113

69

@ RE41 2 2 2 2
100K_0402_5%
ECAGND

KSO7 KSO8
1 1
2

@ CE22 @ CE23
@RE25
@ RE25 22P_0402_50V8J 22P_0402_50V8J
0_0402_5% 2 2
EC_PWROK_FCH 1 2 EC_FCH_PWROK <14>
1 KSO15
footprint short 1
CE14
FOR EC 128KB SPI ROM (150mil PACKAGE) SA00002C100 @ 0.47U_0603_16V7K @ CE24
4 2 22P_0402_50V8J 4
+3VALW
For RF 2 For EMI
SPI_CLK_R SPI_CLK
2 1
20mils 1
0_0402_5%
2
RE39
CE27 0.1U_0402_16V4Z 1
DELL CONFIDENTIAL/PROPRIETARY
1

@ CE28
10P_0402_50V8J
RE36
0_0402_5% @ RE37 UE1 10K_0402_5% 2 Compal Electronics, Inc.
FSEL#SPICS# 1 2 SPI_CS# 1 8 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
2

FRD#SPI_SO CS# VCC


1 2 SPI_SO 2 7 HOLD# TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
0_0402_5% @ RE38 3
DO
WP#
HOLD#
CLK 6 SPI_CLK_R BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ENE-KB926/KB Conn

www.vinafix.vn
4 5 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
GND DIO SPI_SI FWR#SPI_SI PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
footprint short 1 2
LA-7161P
MX25L2005CMI-12G SOP 0_0402_5% @ RE40 footprint short
Date: Wednesday, January 05, 2011 Sheet 17 of 43
A B C D E
5 4 3 2 1

D D

HDMI_TXD2P RV2 2 1 499_0402_1% HDMI_OUT_CLK-_CONN


<7> HDMI_TXD2P
HDMI_TXD2N RV4 2 1 499_0402_1% HDMI_OUT_CLK+_CONN
<7> HDMI_TXD2N
HDMI_TXD1P RV6 2 1 499_0402_1% HDMI_OUT_D0-_CONN
<7> HDMI_TXD1P

1
D
HDMI_TXD1N +5VS 2 QV2 RV7 2 1 499_0402_1% HDMI_OUT_D0+_CONN
<7> HDMI_TXD1N
G 2N7002KW _SOT323-3
HDMI_TXD0P S RV8 2 1 499_0402_1% HDMI_OUT_D1-_CONN
<7> HDMI_TXD0P

3
1
HDMI_TXD0N @ RV9 RV10 2 1 499_0402_1% HDMI_OUT_D1+_CONN
<7> HDMI_TXD0N
100K_0402_5%
HDMI_CLKP RV11 2 1 499_0402_1% HDMI_OUT_D2-_CONN
<7> HDMI_CLKP

2
HDMI_CLKN RV12 2 1 499_0402_1% HDMI_OUT_D2+_CONN
<7> HDMI_CLKN
PLACE PULL DOWN RESISTORS CLOSE TO
DIFFERENTIAL PAIRS CONNECTED TO SOLID
GROUND FLOOD WHICH IS CONTROLLED
BY THE FET
AVOID STUBS TO ALL DIFFERENTIAL TRACES

C C

Place close JHDMI1

RV14 1 2 0_0402_5%
+3VS
HDMI_CLKP 1 @ LV1 2 HDMI_OUT_CLK+_CONN
1 2
W CM-2012-900T_4P
HDMI_CLKN 4 HDMI_OUT_CLK-_CONN
4 3 3
1 2 +5VS
RV15 0_0402_5%

RV17 1 20_0402_5%
@
2

1
HDMI_TXD2P 1 @ LV2 2 HDMI_OUT_D2+_CONN PJP22
1 2

1
1 6 HDMI_SCL_SINK W CM-2012-900T_4P PAD-OPEN 43x79 FV1
<7> HDMICLK_UMA
HDMI_TXD2N 4 3 HDMI_OUT_D2-_CONN 1.5A_6V_1206L150PR~D
4 3
5

@ QV3A
2N7002KDW H_SOT363-6 1 2

2
4 3 HDMI_SDA_SINK RV19 0_0402_5%
<7> HDMIDAT_UMA
CV9
@ QV3B 1U_0402_6.3V6K JHDMI1 CONN@
B 2N7002KDW H_SOT363-6 RV20 1 B
20_0402_5% 1 2 +5VS_HDMI 18 +5V
TV1
HDMI_SDA_SINK 16 13
HDMI_TXD1P @ LV3 HDMI_OUT_D1+_CONN HDMI_SCL_SINK SDA CEC PAD
1 1 2 2 15 SCL Reserved 14
1 2 HDMI_HPD 19
<7> HDMI_HPD HP_DET
@ RV16 0_0402_5% W CM-2012-900T_4P 2
GND

1
HDMI_TXD1N 4 HDMI_OUT_D1-_CONN HDMI_OUT_CLK-_CONN
4 3 3 HDMI_OUT_CLK+_CONN
12 CK- GND 5
1 2 10 CK+ GND 8
@ RV21 0_0402_5% 1 2 RV66 HDMI_OUT_D0-_CONN 9 11
RV22 0_0402_5% 100K_0402_5% HDMI_OUT_D0+_CONN D0- GND
7 D0+ GND 20
HDMI_OUT_D1-_CONN 6 21

2
HDMI_OUT_D1+_CONN D1- GND
footprint short RV23 0_0402_5% 4 D1+ GND 22
1 2 HDMI_OUT_D2-_CONN 3 23
HDMI_OUT_D2+_CONN D2- GND
1 D2+ DDC/CEC_GND 17
HDMI_TXD0P 1 @ LV4 2 HDMI_OUT_D0+_CONN
1 2
W CM-2012-900T_4P SUYIN_100042MR019S153ZL
HDMI_TXD0N 4 HDMI_OUT_D0-_CONN 2 HDMI_HPD
4 3 3 1
@ CV10 1U_0603_10V6K DC232000900
1 2
RV24 0_0402_5%

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
HDMI Conn.
Size Document Number Rev

www.vinafix.vn
1.0
LA-7161P
Date: W ednesday, January 05, 2011 Sheet 18 of 43
5 4 3 2 1
5 4 3 2 1

Place close to JCRT1 for AMD

AMD@ AMD@ AMD@

CV40 CV41 CV42


0.47U_0402_16V4Z~D 0.47U_0402_16V4Z~D 0.47U_0402_16V4Z~D
CRT +3VS 1 2 1 2 1 2

D D

2
DV1 DV2 DV3
Change to BLM15BB470SS1D (47 OHM BEAD) DAN217_SC59-3
AMD@
DAN217_SC59-3
AMD@
DAN217_SC59-3
AMD@

1
VGA_CRT_R RV25 1 2 0_0402_5% CRT_R_RL 1 2 CRT_R_L
<7> VGA_CRT_R
LV5 BLM15BB470SS1D_2P

VGA_CRT_G RV26 1 2 0_0402_5% CRT_G_RL 1 2 CRT_G_L


<7> VGA_CRT_G
LV6 BLM15BB470SS1D_2P

VGA_CRT_B RV27 1 2 0_0402_5% CRT_B_RL 1 2 CRT_B_L


<7> VGA_CRT_B
4.7P_0402_50V8C

4.7P_0402_50V8C

4.7P_0402_50V8C
LV7 BLM15BB470SS1D_2P
150_0402_1%
RV30

150_0402_1%
RV29

150_0402_1%
RV40

6P_0402_50V

6P_0402_50V

6P_0402_50V
1 1 1 1 1 1
1

CV33

CV34

CV35

CV12

CV13

CV14
1 1 1

4.7P_0402_50V8C
CV15

4.7P_0402_50V8C
CV16

4.7P_0402_50V8C
CV17
For EMI
2 @ 2 @ 2 @ 2 @ 2 @ 2 @
2 2 2
2

W=40mils
SE00000AY80 +5VS +5VS_CRT +CRT_VCC
change to 6P_0402
C C
Need apply CIS symbol W=40mils DV11 FV2 W=40mils
2 1 1 2
1
PMEG2010ET_SOT-23 1.1A_8V_1206L110THYR
AMD check list Ver 1.03 CV11
Change to SCS00003H00 1U_0603_10V6K
use 2k pull up to +5V. 2

JCRT1 CONN@
AMD@ AMD@ 6
+CRT_VCC +CRT_VCC MSEN# 11
<17> MSEN# CRT_R_L
CV38 CV39 1
2K_0402_1%

2K_0402_1%

0.47U_0402_16V4Z~D 0.47U_0402_16V4Z~D 7
1

VGA_DDC_DATA 12
RV31

RV32

+3VS 1 2 1 2 CRT_G_L 2
8 G 16
HSYNC_L 13 17
G
CRT_B_L 3
2

9
3

2
VSYNC_L 14
DV8 DV9 4
DAN217_SC59-3 DAN217_SC59-3 10
VGA_DDC_DATA AMD@ AMD@ VGA_DDC_CLK 15
1 5

100P_0402_50V8J
CV18
1

1
VGA_DDC_DATA SUYIN_070546FR015M21TZR
<7> VGA_DDC_DATA
VGA_DDC_CLK 2
<7> VGA_DDC_CLK DC060004300
VGA_DDC_CLK
Place close to JCRT1 for AMD
B B

Place close to JCRT1 for AMD


AMD@ AMD@

CV19 +CRT_VCC CV43 CV44


0.1U_0402_16V7K 0.47U_0402_16V4Z~D 0.47U_0402_16V4Z~D
1 2
+3VS 1 2 1 2
5
1 OE#
P

VGA_CRT_HSYNC 2 4 D_CRT_HSYNC 1 2 RV33 HSYNC_L


<7> VGA_CRT_HSYNC A Y 0_0603_5%
G

2
UV18
74AHCT1G125GW_SOT353-5 DV12 DV13
3

D_CRT_VSYNC 1 2 RV34 VSYNC_L DAN217_SC59-3 DAN217_SC59-3


0_0603_5% AMD@ AMD@
+CRT_VCC 1 1
15P_0402_50V8J
CV21

15P_0402_50V8J
CV22

CV20

1
0.1U_0402_16V7K RV35 HSYNC_L
1 2 1 2
2 2 VSYNC_L
10K_0402_5%
5
1 OE#
P

VGA_CRT_VSYNC 2 4
A <7> VGA_CRT_VSYNC A Y A
G

UV19
74AHCT1G125GW_SOT353-5
3

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, VGA Conn.

www.vinafix.vn
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 19 of 43
5 4 3 2 1
A B C D E

+5VALW INVPW R_B+


@ LV8
W=60mils FBMA-L11-201209-221LMA30T_0805

1
B+ 2 1
+LCDVDD +5VALW +3VS B+ INVPW R_B+
RV59 RV60
LCD POWER CIRCUIT 100K_0402_5%
@
820_0805_1%
@

1
1 1

1 2
RV36 RV37
QV6 @ D
100_0805_5% 47K_0402_5% SI3457BDV-T1-E3_TSOP6 QV11 2 QV12
QV8 40mil 2N7002W -7-F_SOT323-3 G 2N7002W -7-F_SOT323-3
40mil

1 2

1
AO3419L_SOT23-3 D @
6 S

S
INVPW R_B+

3
3
QV7 D S
EN_INVPW R
G 4 5 2
SSM3K7002FU_SC70-3 2 RV38 2 1 56K_0402_5% 2 2 G

1000P_0402_50V7K
G W=60mils 1 S

3
1

G
DV5 S 1
D
1 1

1
2 1 +LCDVDD RV39
<7> ENVDD

3
CV25
CV24 100K_0402_5% CV23
RB751V-40_SOD323-2 0.1U_0402_16V7K 0.1U_0603_50V4Z

1
D 2 2 2

2
4.7U_0805_10V4Z

0.1U_0402_16V7K
2
G QV9 1 1 PW R_SRC_ON QV10 Discharg Circuit
S SSM3K7002FU_SC70-3 2N7002W -7-F_SOT323-3

CV27

CV28

S
1 2 1 3

1
DV10 RV42 100K_0402_5%
LCD_VCC_TEST_EN 2 1 RV41 2 2
<17> LCD_VCC_TEST_EN
10K_0402_5%

G
2
RB751V-40_SOD323-2 +3VS
<17> EN_INVPW R

2
1 2
RV61 0_0402_5% 1
@ CV26

2 0.1U_0402_16V7K 2
2
RO10 1 2 0_0402_5% Closed to JLVDS1
+3VS
+3VS
@ LO1
@ <14> USB20_N9 USB20_N9 1 1 2 USB20_N9_R
2
1 2 RV43 BKOFF# CV29 2 1 0.1U_0402_16V7K JLVDS1 CONN@
4.7K_0402_5% W=60mils 1
USB20_P9 USB20_P9_R USB20_P9_R 1
DV14 1 <14> USB20_P9 4 4 3 3 +LCDVDD 2 2 G1 41
3 3 G2 42
2 1 W CM2012F2S-900T04_0805 USB20_N9_R +3VS 4 43
@ RV44 4 G3
<17> LCD_TEST 5 44

2
4.7K_0402_5% 5 G4
1 2 6 45

0.1U_0402_16V7K

0.1U_0402_16V7K
<7> LDDC_CLK_MCH 6 G5
RB751V-40_SOD323-2 RO11 0_0402_5% 7 46

PJDLC05_SOT23-3
1 1 <7> LDDC_DATA_MCH
2

7 G6
DV6 <7> LVDS_A0- 8
@ CO6 CO7 8
<7> LVDS_A0+ 9
BKOFF# BL_OFF# DO4 9
<17> BKOFF# 1 2 10
AMD@ 2 AMD@ 2 10
<7> LVDS_A1- 11
AMD@ 11
<7> LVDS_A1+ 12
RB751V-40_SOD323-2 12
W=20mils 13
1

EC_ENBKL @ RO12 13
<7> LVDS_A2- 14

1
<17> EC_ENBKL RV51 +5VS_CAM 14
+5VS 1 2 +5VS_CAM <7> LVDS_A2+ 15
10K_0402_5% 0_0603_5% 15
DV7 16
@ 16
<7> LVDS_ACLK- 17
17
<7> ENBKL 1 2 1 2 Place close to JLVDS1 for AMD <7> LVDS_ACLK+ 18
2

RV45 0_0402_5% 18
19
19
3 20 3
RB751V-40_SOD323-2 USB20_P9_R 20
21
USB20_N9_R 21
22
22
Pop DV14 & RV51 +5VS_CAM 23
23
LO2 1 2 DMIC_CLK_R 24
Unpop DV6 & RV44 <24> DMIC_CLK 24
QO4 FBMA-L10-160808-301LMT_2P 25
+5VS SI2301CDS-T1-GE3_SOT23-3+5VS_CAM 25
<24> DMIC_DATA 26
26
W=20mils 1 27
27

S
CO3

D
3 1 1 28
CO2 28
1 29
100P_0402_50V8J 29
30
1

CO4 100P_0402_50V8J 2 30
Remove
G
1 2 31
CO5 0.1U_0402_16V7K 2 31
32
RO13 2 @ CE_ENABLE Pin.34 32
33
33
0.1U_0402_16V7K
2
DBC_ENABLE Pin.37 34
34
100K_0402_5% LCD_PW M 35
2

BL_OFF# 35
1 2 BL_OFF#_R 36
@ RV46 0_0402_5% 36
37
CAM_ON/OFF 37
1 2 footprint short 38
38
39
+3VS RV49 1K_0402_5% 39
INVPW R_B+ 1 1 40
1
@ D 40
RV47 1 2 0_0402_5% <17> CAM_ON/OFF# 2 QO5 CV30 CV31 STARC_107K40-000001-G2
2

G 2N7002_SOT23-3 68P_0402_50V8J 0.1U_0603_50V4Z


+3VS RV48 2 2
S SP01000XE00
3

10K_0402_5%
@
5

4 UO21 4
LV9
1

1
P

<17> INVT_PW M INA


4 LCD_PW M_L 1 2 LCD_PW M
<7> NB_LCD_PW M 2
O
1 DELL CONFIDENTIAL/PROPRIETARY
G

INB CV32
74AHC1G32GW _SOT353-5~D BLM18BB221SN1D_2P~D
Compal Electronics, Inc.
3

100P_0402_50V8J
2 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
1 2 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, LVDS/Cam Conn
RV50 0_0402_5% NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
@ PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
SA00000L310 AND GATE EMI:Add 220 ohm Bead at LCD_PWM (BLM18BB221SN) LA-7161P
Date: W ednesday, January 05, 2011 Sheet 20 of 43
A B C D E

www.vinafix.vn
5 4 3 2 1

+1.7_VDDCT JLAN1 CONN@


+1.7_LX

RL26 13 Unused
+1.7_VDDCT 1 2 +1.7_LX +3V_LAN LAN_ACTIVITY 1 2 LAN_ACTIVITY_R 12 Yellow LED+

1000P_0402_50V7K
10U_0805_10V4Z

LL1 4.7UH_SIA4012-4R7M_20%

0.1U_0402_16V4Z
510_0402_1% 14 Yellow LED-

100P_0402_50V8J
1 1 1 Note:
CL54

CL55

CL56
1 2 EC_SMB_DA2 2
Place Close to LAN chip @ RL44 4.7K_0402_5% CL37 8
@ @ PR4-
D 2 2 2 LL1 DCR< 0.15 ohm D
7 PR4+
Rate current of LL1 > 1A 1
Close to Pin40 RJ45_MIDI1- 6 PR2-
5 PR3-
4 PR3+
RJ45_MIDI1+ 3 PR2+
RJ45_MIDI0- 2 PR1-
GND 15
RJ45_MIDI0+ 1 PR1+
GND 16
no overclocking
RL35 PD 5.1K LAN_SK_LAN_LINK100# 11
5.1K_0402_5% Orange LED-
1 2 +3V_LAN 1 2 +3V_LAN_LED 10
UL1 LED0,1,2 intel Pull UP RL27 510_0402_1% Green LED+
Place Close to Chip LAN_SK_LAN_LINK10# 9 Green LED-
CL57 1 2 0.1U_0402_16V7K PCIE_FRX_DTX_N0_C 29 TX_N LED_0 38 LAN_ACTIVITY
<8> PCIE_NRX_LANTX_N0 LAN_SK_LAN_LINK100#
CL58 1 2 0.1U_0402_16V7K PCIE_FRX_DTX_P0_C 30
Atheros LED_1 39
16 LAN_SK_LAN_LINK10#
2
@ CL52
2
CL53
2
FOX_JM3611A-R5A53-7F
<8> PCIE_NRX_LANTX_P0 TX_P 8152-BL1A LED_2 CL84 100P_0402_50V8J 100P_0402_50V8J @
<8> PCIE_NTX_LANRX_N0 36 0.1U_0402_16V7K DC234004G00
RX_N LAN_MDI0- 1 1 1
TRXN0 12
35 11 LAN_MDI0+
<8> PCIE_NTX_LANRX_P0 RX_P TRXP0
15 LAN_MDI1-
TRXN1 LAN_MDI1+
<13> CLK_PCIE_LAN_N 32 REFCLK_N TRXP1 14
C
<13> CLK_PCIE_LAN_P 33 REFCLK_P TRXN2 18 ESD request C

TRXP2 17
PLT_RST# 2 21
<13,17,25> PLT_RST# PERST# TRXN3
TRXP3 20
PCIE_WAKE# 3 +3V_LAN
<14,17,25> PCIE_WAKE# W AKE#
<7,17,25> EC_SMB_CK2 @ RL32 1 2 0_0402_5% LAN_SMB_CK_R 25 SMCLK RBIAS 10 LAN_RBIAS 1 RL36 2 2.37K_0402_1%
LAN_SMB_DA_R

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z
<7,17,25> EC_SMB_DA2 1 2 26 SMDATA
@ RL33 0_0402_5% +3V_LAN

1U_0402_6.3V4Z
28 TEST_RST VDD33 1
+1.7_LX
CL59 & CL60 Close pin1 < 200mil 1 1 1 1

CL59

CL60

CL61

CL62
27 @
TESTMODE CL61 & CL62 Close pin < 400mil
40 +1.7_LX
LAN_XTALO LX +1.7_VDDCT 2 2 2 2
7 XTLO
LAN_XTALI 8 XTLI +1.7_VDDCT
VDDCT 5 Place Close to LAN chip
1
CL63 1 2 0.1U_0402_16V4Z 4
CLKREQ_LAN#_R VDDCT_REG +1.1_DVDDL CL64 1
<14> CLKREQ_LAN# 1 2 23 CLKREQn DVDDL 24 2 0.1U_0402_16V4Z CL65 49.9_0402_1%
@ RL34 0_0402_5% 37 CL66 1 2 1U_0402_6.3V4Z 0.1U_0402_16V4Z LAN_MDI0+ RL37 1 2 @ CL67 1000P_0402_50V7K
DVDDL_REG CL68 1 2
9B/$1 1 2 footprint short 13 NC 2 0.1U_0402_16V4Z 49.9_0402_1%
@ RL38 4.7K_0402_5% 19 LAN_MDI0- RL39 1 2 1 2 CL69 0.1U_0402_16V4Z
NC
31 AVDDL Near Pin37 49.9_0402_1%
34 22 LAN_MDI1+ RL40 1 2 @ CL70 1000P_0402_50V7K
+1.1_AVDDL AVDDL AVDDH 49.9_0402_1%
6 AVDDL_REG AVDDH_REG 9
LAN_MDI1- RL41 1 2 CL71 0.1U_0402_16V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

2 1
1 1 1 1 +2.7_AVDDH

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
41 GND
1 1 1
CL72

CL73

CL74

CL75

B 2 2 2 2 AR8152-BL1A-R_QFN40_5X5 B
CL76

CL77

CL78
LAN_XTALI
2 2 2
Near Near Near LAN_XTALO
Pin31 Pin34 Pin6 YL1
1 2 Near Near
Pin9 Pin22 footprint short
27P_0402_50V8J

25MHZ_20PF_7A25000012
27P_0402_50V8J

1 1
CL79

CL80

@ RL42
+1.7_VDDCT 2 1
0_0603_5%
2 2 2 1
CL81 1U_0402_6.3V4Z
@
TRL1
CL82 1000P_0402_50V7K
1 2 LAN_MDI1+ 1 16 RJ45_MIDI1+
LAN_MDI1- RD+ RX+ RJ45_MIDI1- RL20 75_0402_5%
2 RD- RX- 15
1 2 +1.7_VDDCT_R 3 14 RJ45_CT0 1 2 +TRCT
CL42 0.1U_0402_16V7K CT CT
4 NC NC 13
CL83 1000P_0402_50V7K 5 12
NC NC RJ45_CT1
1 2 6 CT CT 11 1 2 1
LAN_MDI0+ 7 10 RJ45_MIDI0+ RL21 75_0402_5% CL51
LAN_MDI0- TD+ TX+ RJ45_MIDI0- 1000P_1206_2KV7K
1 2 8 TD- TX- 9
CL44 0.1U_0402_16V7K
2
350uH_NS681695
SP050006N00
A A
EMI: Change TRL1 to SP050006N00

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/31 Deciphered Date 2011/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN-8152
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 21 of 43
5 4 3 2 1

www.vinafix.vn
5 4 3 2 1

D D

+3VS +3VSIN
@ RB1
1 2
1 1
0_0805_5% +CARD_3V +CARD_3V
footprint short CB1 CB2
0.1U_0402_16V7K 4.7U_0603_6.3V6K
2 2 JCARD1 CONN@
2 1 +CARD_3V 3 21 +CARD_3V CB4 2 1 0.1U_0402_16V7K
CB3 0.1U_0402_16V7K XD-VCC SD-VCC +CARD_3V CB5
MS-VCC 28 2 1
SDCLK_MSD2_XD0 32 0.1U_0402_16V7K
SD5_MSD0_XD1 XD-D0 SDCLK_MSD2_XD0
10 XD-D1 7 IN 1 CONN SD_CLK 20
SDCMD_XD2 9 14 SD0_MSD7_XDCLE
SD4_MSD4_XD3 XD-D2 SD-DAT0 SD1_XDCE
8 XD-D3 SD-DAT1 12
SD3_MSD1_XD4 7 30 SD2_MSD5_XD5
@ SD2_MSD5_XD5 XD-D4 SD-DAT2 SD3_MSD1_XD4
6 XD-D5 SD-DAT3 29
1 2 +CRREFE MSBS_XD6 5 XD-D6 SD-DAT4 27 SD4_MSD4_XD3
CB6 100P_0402_50V8J UB11 XD7 4 23 SD5_MSD0_XD1
XD-D7 SD-DAT5 SD6_MSD6_XDW P
For EMI RB2
1 2
6.2K_0402_1%~D
1 REFE
SDCD_XDW E SD-DAT6 18
SD7_MSD3_XDALE
GPIO0 17 34 XD-WE SD-DAT7 16
<14> USB20_N8 RB6 1 2 0_0402_5% USB20_N8_R 2 DM SD6_MSD6_XDW P 33 25 SDCMD_XD2
RB7 XD-WP SD-CMD
C
<14> USB20_P8 1 2 0_0402_5% USB20_P8_R 3 DP CLK_IN 24 CLK_48M
CLK_48M <13>
SD7_MSD3_XDALE 35 XD-ALE SD-CD-SW 1 SDCD_XDW E C
XDCD 40
+3VSIN XD7 SDW P_MSCLK_XDRDY 39 XD-CD SDW P_MSCLK_XDRDY
+3VSIN 4 3V3_IN XD_D7 23 XD-R/B SD-WP-SW 2
+CARD_3V +CARD_3V 5 MSINS_XDRE 38
+V18CR CARD_3V3 MSBS_XD6 SD1_XDCE XD-RE
2 1 6 V18 SP14 22 37 XD-CE
CB7 1U_0402_6.3V6K 21 SD2_MSD5_XD5 SD0_MSD7_XDCLE 36 26 SDW P_MSCLK_XDRDY
XDCD SP13 SD3_MSD1_XD4 XD-CLE MS-SCLK SD5_MSD0_XD1
7 XD_CD# SP12 20 MS-DATA0 17
19 SD4_MSD4_XD3 11 15 SD3_MSD1_XD4
SDW P_MSCLK_XDRDY SP11 SDCMD_XD2 7IN1 GND MS-DATA1 SDCLK_MSD2_XD0
8 SP1 SP10 18 31 7IN1 GND MS-DATA2 19
MSINS_XDRE 9 16 SD5_MSD0_XD1 24 SD7_MSD3_XDALE
SD1_XDCE SP2 SP9 SDCLK_MSD2_XD0 MS-DATA3 MSINS_XDRE
10 SP3 SP8 15 MS-INS 22
SD0_MSD7_XDCLE EPAD SD6_MSD6_XDW P MSBS_XD6
11 SP4 SP7 14 MS-BS 13
SD7_MSD3_XDALE 12 13 SDCD_XDW E 41
SP5 SP6 7IN1 GND
42 7IN1 GND
RTS5138-GR_QFN24_4X4
25

TAITW _R015-B10-LM_NR

SP07000GW00

USB20_N8_R

USB20_P8_R

1 1
AMD@ AMD@
CB10 CB11 CLK_48M Place close to JCARD1 for EMI
0.1U_0402_16V7K 0.1U_0402_16V7K
B 2 2 SDCLK_MSD2_XD0 SDW P_MSCLK_XDRDY B

1
Place close to UB11 for AMD RB8 @ RB4 @ RB5
10_0402_5% 10_0402_5% 10_0402_5%
2

2
1 1 1
CB12 @ CB8 @ CB9
22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J
2 2 2

Place closed to UB11

(For RF request)

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Card Reader RTS5138
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

www.vinafix.vn
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: W ednesday, January 05, 2011 Sheet 22 of 43
5 4 3 2 1
5 4 3 2 1

+USB_SIDE_PW R
USB CONN +USB_VCCA
W=80mils
CI1
0.1U_0402_16V7K

75K_0402_1%
RI2
UI12 1 2 <14> USB20_N2 USB20_N2 1

150U_B2_6.3VM_R35M

0.1U_0402_16V4Z
1 2 <14> USB20_P2 USB20_P2 1
1 10 RI3 100K_0402_5% +
<14> USB20_P1 1D+ VCC +3VALW

CI2

CI3
RI1
D 43.2K_0402_1% 2 9 PW RSHARE_OE# D
<14> USB20_N1 1D- S PW RSHARE_OE# <17> 2 2
1

1 USB_CHARGE_D+ 3 2D+ D+ 8 PW SUSB_P1 <26> 1 2


RI7 0_0402_5%
USB_CHARGE_D- 4 7 PW SUSB_N1 <26>
2D- D- @ LI1 JUSB1 CONN@
2

5 GND OE# 6 1 1 2 2 4 VCC


RI4 RI5 USB20_N2 USB20_N2_R 3
49.9K_0402_1% 49.9K_0402_1% USB20_P2 USB20_P2_R D-
2 D+
4 4 3 3 1 GND
TS3USB221RSER_QFN10_2x1P5~D
1

W CM2012F2S-900T04_0805 5 GND
6 GND

3
1 2 7

0.1U_0402_16V7K

0.1U_0402_16V7K
S OE# Function RI6 0_0402_5% GND
1 1 AMD@ 8

PJDLC05_SOT23-3
GND
X H Disconnect CI12 CI13
L L D=1D AMD@ DL1 SUYIN_020173MR004S50TZL
2 2
H L D=2D DC233003W00

1
(For ESD request)

RTCVREF RTCVREF RTCVREF RTCVREF @ FUSEI1


80 mils
5A_32V_0467005.NR~D
C 1 2 2.0A +USB_VCCA
C

1
1

UI13
220K_0402_5%

SDMK0340L-7-F

CI10 +5VALW PJP23 @


RI8 0.1U_0402_16V7K PAD-OPEN 43x79
80 mils 1 8 USB_OC2#
RI9 DI1 51ON# +5VALW _F1 GND OC1# USB_OC2# <14>
51ON# <29,33> 1 2 2 IN OUT1 7
10K_0402_5% 2 CLOSE TO UI16
3 EN1# OUT2 6
<17> USB_EN# 4 5
2

EN2# OC2#

10U_1206_16V4Z

0.1U_0402_16V7K
1 1
5

CI4 CI5 TPS2062ADR_SO8~D


CI11
1
D
1
P

USB_DETECT# NC QI1
2 1 2 A Y 4 2
2 2
SA00002AS0L
G 2N7002LT1G_SOT23-3
CIS LINK OK
G

2.2U_0603_10V7K~D S
3

UI16
3

TC7SZ14FU_SSOP5~D RI11
USB_DETECT# <26>
100K_0402_5%

@ FUSEI2
2

5A_32V_0467005.NR~D
From connector detect 1 2

2 1 1 2 USB_DET#_DELAY
@ RI10 0_0402_5% USB_DET#_DELAY <17> +5VALW PJP24 @
DI2 JUMP_43X79
SDMK0340L-7-F footprint short 1 2 +5V_USB

UI14
B B

10U_1206_16V4Z
1 8 USB_OC0#
Power share

0.1U_0402_16V7K
+5VALW _F2 GND OC1# USB_OC0# <14>
1 1 2 IN OUT1 7
3 EN1# OUT2 6
CI7 CI6 <17> USB_EN# 4 5
EN2# OC2#
2 2 TPS2062ADR_SO8~D

@ FUSEI3
5A_32V_0467005.NR~D
1 2 +USB_SIDE_PW R

+5VALW PJP25 @ UI15


PAD-OPEN 43x79 1 8 USB_OC1#
GND OC1# USB_OC1# <14>
1 2 +5VALW _F3 2 7
IN OUT1
3 EN1# OUT2 6
10U_1206_16V4Z

<17> USB_PW R_EN# 4 EN2# OC2# 5

0.1U_0402_16V7K
1 1
TPS2062ADR_SO8~D
CI8 CI9
2 2

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB/POWER Share
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

www.vinafix.vn
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: W ednesday, January 05, 2011 Sheet 23 of 43
5 4 3 2 1
5 4 3 2 1

80mil +5VS +5VS_PVDD


CC7 near Pin9 CC9 near Pin25 LC1
+5VS_PVDD 2 1
+3VS
CC8 near Pin1 CC10 near Pin38

10U_0805_10V6K
+VDDA 1 1 BLM21PG600SN1D_0805~D
1 1 1

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
D CC4 D
20mil CC1 CC2 CC3 CC5

10U_0805_10V6K
LC2
40mil 2 1
2 2 2 2 2
1 1 1 +5VS

.1U_0402_16V7K

.1U_0402_16V7K
CC6 1 1 1

10U_0805_10V6K

.1U_0402_16V7K

.1U_0402_16V7K
CC7 CC8 FBMA-L11-160808-800LMT_0603
CC9 CC10 CC11
+MIC1_VREFO_R +MIC1_VREFO_L 2 2 2 10U_0805_10V6K

39

46

25

38
1

9
UC1 2 2 2
CC3 near Pin39

DVDD_IO

PVDD1

PVDD2

AVDD1

AVDD2
DVDD
CC5 near Pin46
1
1

RC20 RC21
2.2K_0402_5% 2.2K_0402_5% 23 40 SPKOUT_L+
LINE1_L SPK_OUT_L+ SPKOUT_L-
24 LINE1_R SPK_OUT_L- 41
30mil
2
2

4.7U_0603_6.3V6K 14 45 SPKOUT_R+
LINE2_L SPK_OUT_R+ SPKOUT_R-
RC1 1K_0402_1%
10mil CC12 15 LINE2_R SPK_OUT_R- 44

<26> MIC1 MIC1 1 2 MIC1_R 1 2 C_MIC1 21 MIC1_L HP_OUT_L 32 HP_OUTL


HP_OUTL <26>
Beep sound
22 33 HP_OUTR
MIC2 1 2 MIC2_R 1 2 C_MIC2 MIC1_R HP_OUT_R HP_OUTR <26> 10mil
<26> MIC2
16
RC2 1K_0402_1%
CC13 17
MIC2_L
MIC2_R
EC Beep RC3
10 HDA_SYNC 1 2
4.7U_0603_6.3V6K SYNC HDA_SYNC <14> <17> BEEP#
47K_0402_5%
RC5 DMIC_DATA 2 6 HDA_BITCLK_R 1 2
<20> DMIC_DATA GPIO0/DMIC_DATA BCLK HDA_BITCLK <14>
0_0402_5% RC4 0_0402_5%
1 2 DMIC_CLK_L 3
<20> DMIC_CLK GPIO1/DMIC_CLK
SDATA_OUT 5 HDA_SDOUT
HDA_SDOUT <14>
PCI Beep RC6
1 1 2 1 2 MONO_IN
C <14> FCH_SPKR C
@ CC15 PD# 4 8 HDA_SDIN0_R 1 RC7 2 47K_0402_5% CC14 1U_0603_10V4Z
PD# SDATA_IN FCH_HDA_SDIN0 <14>
33_0402_5%
100P_0402_50V8J
2 HDA_RST# 11 47
<14> HDA_RST# RESET# EAPD EC_EAPD <17>

1
SPDIFO 48
MONO_IN 12 RC8 1
PCBEEP

.1U_0402_16V7K
20
MONO_OUT

10K_0402_5%
CC16
RC9 39.2K_0402_1% SENSEA 13

2
HP_JD SENSEA SENSE A 2
<26> HP_JD 1 2 MIC2_VREFO
29

MIC_JD 1 2
18
SENSE B
30
10mil
<26> MIC_JD MIC1_VREFO_R +MIC1_VREFO_R
RC10 20K_0402_1% 36 28 +LDO_CAP
CBP LDO_CAP
1 2 35 27 +AC97_VREF 10mil
CC17 CBN VREF

2.2U_0603_10V6K
2.2U_0603_10V6K 31 19 +AC_JDREF 1 2 2 1 1
+MIC1_VREFO_L MIC1_VREFO_L JDREF

10U_0805_10V6K
.1U_0402_16V7K
RC11 20K_0402_1% @
10mil

CC21
43 34 +CPVEE 1 2 CC19 CC20
PVSS2 CPVEE CC18
42
PVSS1 2.2U_0603_10V6K 1 2 2
49 26
DVSS2 AVSS1
7 37
DVSS1 AVSS2
ALC259-GR_QFN48_7X7 HDA_BITCLK_R EMI
ALC259-VB5-GR:SA00003QR10 Change CC19 to 2.2uF for pop noise or class D noise HDA_BITCLK
DGND AGND

22_0402_5%
1
1
1 2 RC13
RC12 0_0603_5% CC22
1 2 @ 10P_0402_50V8J
B RC14 0_0603_5% 2 B

2
1 2
RC15 0_0402_5% 1
1 2
RC16 0_0402_5% CC23
10P_0402_50V8J
2
GND AGND

Speaker Connector
For Power on/off de-pop circuit and system booting warning signal:
Please system BIOS Engineer Note: JSPEK1
SPKOUT_L- 1
+5VS SPKOUT_L+ 1
1.If you want the system make warning signal after power on 2
2
SPKOUT_R- 3 5
SPKOUT_R+ 3 GND
Please let EC_MUTE# high first 4
4 GND
6

2.When you want to exit your BIOS programming code 0_0402_5% ACES_87213-0400G
2

2
RC17 1 2 CONN@
Please let EC_MUTE# Low. +3VS
RC18 @
CC24 1K_0402_5%
(The programming is difference from before) @
1 2 SP02000GC00 LINK OK
1
5

UC2 @
1 @ D3 @ D4
P

A <17> EC_MUTE# INA .1U_0402_16V7K A


4 PD#
O PJDLC05_SOT23-3 PJDLC05_SOT23-3
<14> HDA_RST# 2
1

1
INB
G

74AHC1G32GW_SOT353-5~D
3

DELL CONFIDENTIAL/PROPRIETARY
1 2 Compal Electronics, Inc.
@ PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
RC19 0_0402_5% TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Codec ALC259

www.vinafix.vn
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 24 of 43
5 4 3 2 1
A B C D E

+1.5VS

SIM Card

WWAN@ CM1

WWAN@ CM2

WWAN@ CM3

WWAN@ CM4
0.01U_0402_25V7K

0.1U_0402_16V7K

4.7U_0805_10V4Z

0.047U_0402_16V4Z
1 1 1 1
WWAN PCIE MiniCard UM22 @

2 2 2 2 UIM_RESET 1 6 UIM_VPP

+1.5VS
2 5 +UIM_PWR
JWWAN1CONN@
PCIE_WAKE# 1 2
<14,17,21> PCIE_WAKE# 1 2 +3VS

CM5

CM6

CM7

CM8

WWAN@ CM9
0.01U_0402_25V7K
0.047U_0402_16V4Z
3 4 1 UIM_CLK 3 4 UIM_DATA
3 4
110 mils

330U_D2E_6.3VM_R25M
0.1U_0402_16V7K
4.7U_0805_10V4Z
5 6 1 1 1
5 6

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J
1
7 8 + 1
<14> CLKREQ_WWAN# 7 8 +UIM_PWR

CM10

CM11

CM12

CM13
9 10 UIM_DATA 1 1 1 1
9 10 UIM_CLK

WWAN@

WWAN@

WWAN@

WWAN@
<13> CLK_PCIE_WWAN_N 11 12 SRV05-4.TCT_SOT23-6~D
11 12 UIM_RESET 2 2 2 2
<13> CLK_PCIE_WWAN_P 13 14
13 14 UIM_VPP @ @ @ @
15 16
15 16 2 2 2 2

17 18
17 18 WWAN_RADIO_OFF#
19 20 WWAN_RADIO_OFF# <17>
19 20 PLT_RST#
21 22 PLT_RST# <13,17,21>
21 22 +UIM_PWR
23 24
<8> PCIE_NRX_WWANTX_N2 23 24
25 25 26 26
<8> PCIE_NRX_WWANTX_P2

1U_0603_10V6K
27 28 @
27 28 WWAN_SMB_CK_R 1
29 29 30 30 2 0_0402_5% RM1 EC_SMB_CK2 <7,17,21> 1

CM14

WWAN@
<8> PCIE_NTX_WWANRX_N2 31 32 WWAN_SMB_DA_R 1 2 0_0402_5% RM2 EC_SMB_DA2 <7,17,21>
31 32 @
<8> PCIE_NTX_WWANRX_P2 33 33 34 34
35 36 USB20_N5_R
35 36 USB20_P5_R 2
37 37 38 38
+3VS 39 39 40 40
41 41 42 42
43 44 JSIM1 CONN@
43 44

0.1U_0402_16V7K

0.1U_0402_16V7K
45 45 46 46 4 GND VCC 1
47 48 1 1 UIM_VPP 5 2 UIM_RESET
47 48 UIM_DATA VPP RST UIM_CLK
49 49 50 50 6 I/O CLK 3
51 52 CM23 CM24 WWAN@ 7
51 52 RM3 DET
1 2 0_0402_5%
53 54 AMD@ 2 AMD@ 2
GND1 GND2 @ LM1
55 NC NC 56
check layout symbol USB20_P5 1 2 USB20_P5_R 8
<14> USB20_P5 1 2 GND
GND 9
BELLW_80052-1021
USB20_N5 4 3 USB20_N5_R
2 <14> USB20_N5 4 3 2
DC040006S00 Place close to JWWAN1 for AMD
WCM2012F2S-900T04_0805

1 2 TAITW_PMPAT6-06GLBS7N14N0
RM4 0_0402_5%
WWAN@ SP07000FV00
WLAN/WIMAX PCIE Mini Card
Primary Power Aux Power
+3V_WLAN
40 mils +1.5VS
20 mils PWR
Rail
Voltage
Tolerance
0.01U_0402_25V7K

0.1U_0402_16V7K

4.7U_0805_10V4Z

0.047U_0402_16V4Z

+3VS 2 1 Peak Normal Normal


RM5 0_1206_5% 1 1 1 1 1 1 1 1
0.01U_0402_25V7K

0.1U_0402_16V7K
0.047U_0402_16V4Z

4.7U_0805_10V4Z

+3.3V +-9% 1000 750


2 2 2 2 2 2 2 2
CM19

CM20

CM21

CM22

250 (Wake enable)


CM15

CM16

CM17

CM18

+3.3Vaux +-9% 330 250 5 (Not wake enable)

+1.5V +-5% 500 375 NA


@
RM19 1 2 0_0402_5% BT_DISABLEB#
<13> CLK_DEBUG_PORT_1
@
BT_RADIO_OFF# RM20 1 2 0_0402_5%
<17> BT_RADIO_OFF#

+3V_WLAN RM12 1 2 0_0402_5%


+1.5VS
3 JWLAN1 CONN@ @ LM2 3
PCIE_WAKE# USB20_P4 USB20_P4_R
@
1
3
1
3
2
4
2
4 For Compal LPC debug card <14> USB20_P4 1
1 2
2

BT_RADIO_OFF# RM17 1 2 0_0402_5% BT_ACTIVE_OFF 5 6


CLKREQ_WLAN# 5 6 LPC_LFRAME# USB20_N4 USB20_N4_R
7 8 LPC_LFRAME# <13,17> <14> USB20_N4 4 3
<14> CLKREQ_WLAN# 7 8 LPC_LAD3 4 3
9 10 LPC_LAD3 <13,17>
9 10 LPC_LAD2 WCM2012F2S-900T04_0805
<13> CLK_PCIE_WLAN_N 11 12 LPC_LAD2 <13,17>
11 12 LPC_LAD1
<13> CLK_PCIE_WLAN_P 13 14 LPC_LAD1 <13,17>
13 14 LPC_LAD0
footprint short 15
15 16
16 LPC_LAD0 <13,17> 1 2
PLT_RST# 1 2 17 18 RM13 0_0402_5%
BT_DISABLEB# @ RM6 0_0402_5% 17 18 WLAN_RADIO_OFF#
19 20 WLAN_RADIO_OFF# <17>
19 20 PLT_RST#
21 22
PCIE_NRX_WLANTX_N1 21 22
23 24
<8> PCIE_NRX_WLANTX_N1 PCIE_NRX_WLANTX_P1 23 24
25 26
<8> PCIE_NRX_WLANTX_P1 25 26 0_0402_5% @
27 28
27 28 WLAN_SMB_CLK_R
29 30 1 2 RM7 EC_SMB_CK2 <7,17,21>
PCIE_NTX_WLANRX_N1 29 30 WLAN_SMB_DAT_R
<8> PCIE_NTX_WLANRX_N1 31 32 1 2 RM8 EC_SMB_DA2 <7,17,21>
PCIE_NTX_WLANRX_P1 31 32 0_0402_5% @
<8> PCIE_NTX_WLANRX_P1 33 34
33 34 USB20_N4_R
35 36
35 36 USB20_P4_R
37 38
37 38
+3V_WLAN 39 40
39 40
0.1U_0402_16V7K

41 42
41 42
0.1U_0402_16V7K

@ 43 44
BT_RADIO_OFF# RM18 1 BT_DISABLE 43 44
2 0_0402_5% 45 46 1 1
45 46 AMD@ AMD@
47 48
RM10 1 0_0402_5% 47 48 CM25 CM26
<17> EC_TX 2 49
49 50
50
<17> EC_RX RM11 1 2 0_0402_5% 51 52
51 52 2 2
53 54
GND1 GND2
1 2 RM9 100K_0402_5%

ACES_88910-5204
4 BT_RADIO_OFF# RM21 1 SP01000MO0L 4
2 1K_0402_5%
SP01000I100 CIS LINK OK
Place close to JWLAN1 for AMD
DELL CONFIDENTIAL/PROPRIETARY

RF:Andros MLK will use DW1702 combo card Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT WLAN/WWAN/BT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev

www.vinafix.vn
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7161P
Date: Wednesday, January 05, 2011 Sheet 25 of 43

A B C D E
A B C D E

BATT CHARGE
+5VALW

1 BATT_LOW_LED#_D 1

1
1

100K_0402_5%
RO4 RO6

100K_0402_5%
RO5 300_0402_5%

2
2

2
6 pin

3
QO2B D
JWTB1 5
1 G
1 PWSUSB_N1 <23>
2 PWSUSB_P1 <23> DMN66D0LDW-7_SOT363-6
2
3 S

4
3

6
QO2A D
4 4 USB20_N0 <14>
7 G1 5 5 USB20_P0 <14> <17> BATT_LOW_LED# 2
8 6 G
G2 6 DMN66D0LDW-7_SOT363-6
S

1
ACES_88460-00601-P01
CONN@

SP010013W00
Power LED

+5VALW

2 2

DO1
HT-210UD5-BP5_AMBER-WHITE

100K_0402_5%
RO1 100K_0402_5%
White
RO3

1
1 2 PWR_LED#_D 2

820_0402_5% 1 +5VALW
BATT_LOW_LED#_D 3

RO2
Amber

3
QO1B D
5
G
DMN66D0LDW-7_SOT363-6
S

4
6
QO1A D
20 pin
<17> PWR_LED# 2
JWTB2 G
21 DMN66D0LDW-7_SOT363-6
GND 1 1
2 2 MIC2 <24> S

1
3 3 MIC1 <24>
4 4 MIC_JD <24>
5 5
6 6 HP_OUTR <24>
7 7 HP_OUTL <24>
8 8 HP_JD <24>
9 9
10 10
11 11
12 12
3 +5V_USB 3

13 13
14 14 HD LED
15 15
16 16 +USB_SIDE_PWR
17 17
18 18
19 19 +5VS
22
GND 20 20 USB_DETECT# <23>
ACES_87213-2000G
CONN@
DO3
100K_0402_5%

RO9
SP02000BJ00
1

1 2 SATA_LED#_D 1 2 +5VS

820_0402_5% HT-121BP_WHITE
2

RO8

QO3B D
5
G
DMN66D0LDW-7_SOT363-6
S
4
6

QO3A D

<12> SATA_ACT#_R 2
G
DMN66D0LDW-7_SOT363-6
S
1

4 4

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

www.vinafix.vn
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, WTB Conn/LED
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 26 of 43
A B C D E
5 4 3 2 1

Pleace near HDD CONN (JHDD1)


+5VS

HDD Connector

1000P_0402_50V7K
1 1 1 1

10U_0805_10V4Z

0.1U_0402_16V7K

0.1U_0402_16V7K
CONN@ JHDD1 Near CONN side. CH1 CH2 CH3 CH4
2 2 2 2
D
GND 1 D
A+ 2 SATA_STX_DRX_P0 <12>
A- 3 SATA_STX_DRX_N0 <12>
GND 4
5 SATA_SRX_DTX_N0_R CH5 1 2 0.01U_0402_16V7K SATA_SRX_DTX_N0 <12>
B- SATA_SRX_DTX_P0_R CH6
B+ 6 1 2 0.01U_0402_16V7K SATA_SRX_DTX_P0 <12>
GND 7

V33 8
9 +3VSHDD
V33
V33 10
11 +3VS +3VSHDD
GND
GND 12
13 PJP21
GND +5VS JUMP_43X118
V5 14
V5 15 1 1 2 2
16
V5
17
40 mils
GND
18
Open
DAS/DSS
GND 19

10U_0805_10V4Z

0.1U_0402_16V7K
23 GND V12 20

0.1U_0402_16V7K
24 GND V12 21
V12 22 1 1 1

@ CH7

@ CH8

@ CH9
SUYIN_127043FR022G196ZR
2 2 2
DC010005A00
C C

FAN Control circuit


+FAN_POW ER
40mil
+3VS
+FAN_POW ER CONN@
1000P_0402_50V7K

1 1
10U_1206_16V4Z

B CF1 CF2 B

1
JFAN1
2 2 +5VS RF1
40mil
1 1
CF3 10U_1206_16V4Z 10K_0402_5% 2 2
1 2 3 3

2
<17> FAN_SPEED1 4 GND
UF23 5 GND
1 VEN GND 8
2 VIN GND 7 1 ACES_85204-0300N
3 VO GND 6
<17> EN_DFAN1 EN_DFAN1 4 5 CF4
VSET GND 0.01U_0402_16V7K
2
SP02000JR00
RT9027BPS SO 8P
CIS SYMBOL OK

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, FAN/HDD
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

www.vinafix.vn
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: W ednesday, January 05, 2011 Sheet 27 of 43
5 4 3 2 1
5 4 3 2 1

+5VALW to +5VS Transfer +1.5V to +1.5VS Transfer +3VALW to +3V_LAN Transfer


B+_BIAS +5VALW QZ3 QZ12 rDS=5.2mOHM
W=40mils
NTMS4107NR2G_SO8~D +5VS +1.5V +1.5VS
B+_BIAS SI4634DY-T1-E3_SO8~D QZ11
1 8 1
7 2 8 1 +3VALW SI3456DDV-T1-GE3_TSOP6
RZ3 6 3 7 2 +3V_LAN

D
100K_0402_5% 5 1 6 3 1 6 W=40mils

S
CZ2
10U_0805_10V4Z

10U_0805_10V4Z

1U_0603_10V6K
RZ6 RZ15 5 RZ16 5 4

CZ18
20K_0402_5% 100K_0402_5% 2
2

20K_0402_5%

22U_0805_6.3V6M

22U_0805_6.3V6M

0.1U_0402_16V7K
D 5V_RUN_ENABLE D
1 1

4
2 2

G
2

CZ11
B+_BIAS 1 1

3
1.5V_RUN_ENABLE
1

D 2

390K_0402_5%

CZ9

CZ10

CZ12
QZ5

2M_0402_5%~D

470K_0402_5%
SUSP 2 SSM3K7002FU_SC70-3 1

1
G CZ4 2 @ 2
1

1
RZ29 D RZ31 CZ19
S
3

RZ13
@ 0.1U_0402_25V6 SUSP 2 QZ14
2 G SSM3K7002FU_SC70-3 0.1U_0402_25V6
2

S 2 CZ15

2
EN_WOL 1 2

1
D 2200P_0402_50V7K

1
<17> EN_WOL# 2 QZ13
G SSM3K7002FU_SC70-3 RZ14
S 1.5M_0402_5%

3
+3VALW to +3VS Transfer

2
+3VALW QZ8 +3VS
B+_BIAS NTMS4107NR2G_SO8~D
8 1
7 2
1

1
6 3 1 @
10U_0805_10V4Z

RZ10 5 RZ12
CZ5

100K_0402_5% 20K_0402_5% RTCVREF +COINCELL


4

2
2

1
C 3.3V_RUN_ENABLE RZ28 C
1K_0402_5% +5VALW
2M_0402_5%~D
1

D
1

1
SUSP 2 QZ10 RZ30 CZ8
G SSM3K7002FU_SC70-3 RZ7

2
S 0.01U_0402_25V7K 100K_0402_5%
3

2 DZ3
2

BAT54CW_SOT323-3~D

2
SUSP
+RTCVCC SUSP <37>

SSM3K7002FU_SC70-3
1
D

QZ6
2
+1.1VALW to +1.1VS Transfer 1
<17,39,41> SUSP#
G
S

3
CZ24 1 2
QZ15 rDS=5.2mOHM 1U_0603_10V6K RZ8 10K_0402_5%
B+_BIAS +1.1VALW 2
SI4634DY-T1-E3_SO8~D +1.1VS
8 1
1

7 2
RZ21 6 3
1

470K_0402_5% 5 1
10U_0805_10V4Z

RZ25
CZ20

20K_0402_5%
2

1.1V_RUN_ENABLE
2
2
1

D QZ16
Discharg Circuit
2M_0402_5%~D

B SUSP SSM3K7002FU_SC70-3 B
2
1

G 1
S RZ32 CZ21 +5VS +1.5VS +3VS +1.1VS +0.75VS +1.05VS
3

0.1U_0402_25V6

1
2

@
@ @
2

RZ19 RZ23 RZ24 RZ20 RZ18 RZ35


1K_0402_5% 1K_0402_5% 39_0402_5% 39_0402_5% 22_0603_5% 470_0603_5%

2
+5V_RUN_CHG

+1.5V_RUN_CHG

+3.3V_RUN_CHG

+1.1V_RUN_CHG

+1.05V_RUN_CHG
+DDRVTT_CHG
+1.05V to +1.05VS Transfer

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3
QZ22 rDS=5.2mOHM @ @ @

1
D D D D D D

QZ18

QZ19

QZ20

QZ21

QZ23

QZ25
B+_BIAS +1.05V
SI4634DY-T1-E3_SO8~D +1.05VS SUSP 2 SUSP 2 SUSP 2 SUSP 2 SUSP 2 SUSP 2
8 1 G G G G G G
1

7 2 S S S S S S

3
RZ22 6 3
1

470K_0402_5% 5 1
10U_0805_10V4Z

RZ33
CZ26

20K_0402_5%
2

1.05V_RUN_ENABLE
2
2
1

D QZ17
2M_0402_5%~D

SUSP 2 SSM3K7002FU_SC70-3
1

A G A
1
S RZ34 CZ27
3

0.1U_0402_25V6
2
DELL CONFIDENTIAL/PROPRIETARY
2

Compal Electronics, Inc.


PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DC/DC (Power control)

www.vinafix.vn
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 28 of 43
5 4 3 2 1
A B C D E

+3VALW
MB_Power On/Off SW

1
+3VALW RZ26

JPWR1 100K_0402_5%
H2 H3 H5 H6 H7 H8 H9 H19

2
H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 CONN@ 1 DZ1
1 LID_SW#
2 LID_SW# <17> 2 ON/OFF_EC# <17>
2 ON/OFFBTN#
3 1
3
4 3 51ON# <23,33>
1

1
4
1 1
5 DAN202UT106_SC70-3
GND
6
H10 H11 H12 GND
H_3P2 H_3P2 H_3P2 1
ACES_88514-0401 CZ22

FD1 FD2 FD3 FD4 SP01000R400 0.1U_0402_25V6 QZ24


1

1
2

1000P_0402_50V7K
2N7002LT1G_SOT23-3 1

1
@ @ @ @ D CZ23 DZ2
CIS SYMBOL OK
<17,35> EC_ON 2
1

1
G

2
S 2 GLZ20A_LL34

2
ON/OFFBTN# RZ27
+3VALW LID_SW#
10K_0402_5%

PESD24V_SOT23-3

1
1
ZZZ CZ25

DZ4
0.1U_0402_25V6
2

1
H15 H16
H_4P0 H_4P0
PCB
DAZ0I800100 Place closed to JPWR1
1

(For ESD request)


10/08 ESD: Change DZ4 to SCA00000R00
H17 H18
H_3P4x3P9 H_3P4
2 2
1

Touch/B Connector JTP1


CONN@ Vendor pin defined
+5VS 1
VCC 1. VDD
<17> TP_CLK 2
NC
2 <17> TP_DATA 3
4
Num_Lock 2. PS2CLK
CE15 GND
1 1 3. PS2DATA

100P_0402_50V8J

100P_0402_50V8J
1U_0402_6.3V6K CE16 CE17 5
1 GND
6
2 2
GND 4. GND
ACES_88514-0401

SP01000R400

3 3

4 4

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

www.vinafix.vn
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SW/TP/PWR/SCREW
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 29 of 43
A B C D E
5 4 3 2 1

9HUVLRQ&KDQJH/LVW 3,5/LVW
,WHP 3DJH 7LWOH 'DWH 5HTXHVW ,VVXH'HVFULSWLRQ 6ROXWLRQ'HVFULSWLRQ 5HY
2ZQHU
ıIJ ıĸ ōŗŅŔ ıĺİijĹ ņņ ōńŅġőŢůŦŭġťŪŴűŭŢźġŢţůŰųŮŢŭ ŔŸŢűġōŗŅŔġőŰųŵ ıįij

ıij ijı ōŗŅŔ ıĺİijĹ ņŎŊ ōńŅŠőŘŎ łťťġijijıġŰũŮġŃŦŢťġŢŵġōńŅŠőŘŎġĩŃōŎIJĹŃŃijijIJŔŏĪ ıįij


D D

ıĴ IJĸ ŃŰŢųťġŊŅ ıĺİijĹ ņņ ńũŢůŨŦġŃŰŢųťġŊŅġŵŰġřıIJ ńũŢůŨŦġœņĴĶġŵŰġĹįijŌ ıįij

ıĵ IJĸ łńŊŏ ıĺİijĹ ņņ ńũŢųŨŦġŭŦťġŢŭŸŢźŴġŭŪŨũŵġŸũŦůġŶůűŭŶŨġłń ńũŢůŨŦġœņĴijġŵŰIJĶıŌ ıįij

ıĶ ijĺ őŰŸŦųġŃŶŵŵŰůġņŔŅ IJıİıĹ ņŔŅ őŰŸŦųġŃŶŵŵŰůġņŔŅġőųŰŵŦŤŵŪŰů ńũŢůŨŦġŅśĵġŵŰġŔńłıııııœıı ıįij

ıķ IJĺ ŗňł IJıİıĹ ņŎŊ ńœŕġņŎŊġŏŰŪŴŦ ńũŢůŨŦġōŗĶļōŗķļōŗĸġŵŰġŔŎıIJıııŇőıı ıįij

ıĸ ijIJ ōłŏ IJıİıĹ ņŎŊ ōłŏġņŎŊġŏŰŪŴŦ ńũŢůŨŦġŕœōIJġŵŰġŔőıĶıııķŏıı ıįij

ıĹ IJĴļIJĵ Ňńʼn IJıİIJIJ œŇ œŇġŏŰŪŴŦ łťťġńŇijıġħġńŇĹijġĴĴőŇ ıįij

ıĺ ıĺ łőŖġőŘœ IJıİIJĵ ņņ łŎŅġńœŃġœŦŷġńġŶűťŢŵŦ ōŖIJĭġōŖijĭġōŖĵġŤũŢůŨŦġŵŰġıŠıĹıĶ ıįij

IJı ıĸ ōŕŅőŠłŖř IJIJİıij ņņ łŎŅġńũŦŤŬġŭŪŴŵġŶűťŢŵŦ œŖIJĵĭœŖIJĶĭœŖijĴĭœŖijķġŤũŢůŨŦġŵŰġijŌġŰũŮġűŶŭŭġŶűġŵŰġĬĶŗŔ ıįĴ

IJIJ ıĸ ōŕŅőıŠʼnőŅ IJIJİıij ņņ łŎŅġńũŦŤŬġŭŪŴŵġŶűťŢŵŦ łťťġœŖijijġIJııŬġŰũŮġġűŶŭŭġŶűġŵŰġĬĶŗŔ ıįĴ


C C

IJij IJĸ ŃŰŢųťġŊŅ IJIJİIJĸ ņņ ńũŢůŨŦġŃŰŢųťġŊŅġŵŰġřıij ńũŢůŨŦġœņĴĶġŵŰġIJĹŌ ıįĴ

IJĴ IJıļIJIJ ŅŅœŊŊŊĮŔŐŅŊŎŎ IJIJİijij ņŎŊ ŅŅœġņŎŊġŏŐŊŔņ őŐőġńŅĺĭńŅIJıĭńŅIJIJĭńŅIJijĭńŅIJĴĭńŅIJĵĭńŅĴIJĭńŅĴijĭńŅĴĴĭńŅĴĵĭńŅĴĶĭńŅĴķ ıįĴ

IJĵ IJĸ ņŏņĮŌŃĺijķ IJIJİijij ņŔŅ ņŔŅ łťťġıįIJŶŇġŤŢűŴġŰůġńņijĶġħġńņijĺ ıįĴ

IJĶ IJĹ ʼnŅŎŊ IJIJİijij ņŔŅ ņŔŅ łťťġıįIJŶŇġŤŢűŴġńŗĴķġŰůġĬĴŗŔġŵųŢŤŦġŰŧġŵŰűġŴŪťŦġŭŢźŰŶŵį ıįĴ

IJķ ijIJ ōłŏ IJIJİijij ņŔŅ ņŔŅ łťťġıįIJŶŇġŤŢűŴġńōĹĵġŰůġĬĴŗŠōłŏġŵųŢŤŦġŰŧġŵŰűġŴŪťŦġŭŢźŰŶŵį ıįĴ

IJĸ ijij ńŢųťġœŦŢťŦų IJIJİijĴ œŇ œŇġŏŰŪŴŦ ŎŰŶůŵġœŃĹľIJıĭńŃIJijľijijő ıįĴ

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B IJĺ IJĺ ŗňł IJIJİĴı ņņ łŎŅġńũŦŤŬġŭŪŴŵġŶűťŢŵŦ ńũŢůŨŦġœŗĴIJġħġœŗĴijġŧųŰŮġĵįĸŌġŵŰġijŌ ıįĴ B

ijı IJĸ ŃŰŢųťġŊŅ IJijİIJı ņņ ńũŢůŨŦġŃŰŢųťġŊŅġŵŰġłıı ŖůűŰűġœņĴĶ IJįı

ijIJ IJĺ ŗňł IJijİIJı ŔŢŧŦŵź ōőŔġŵŦŴŵġŧŢŪŭ ŅŦŭŦŵŦġœŗķĸġįġőŰűġŇŗij IJįı

ijij ijĹ ŅńİŅń IJijİIJķ ŔŢŧŦŵź ŔŢŧŦŵźġœŕńġţŢŵŵŦųźġŵŦŴŵġŧŢŪŭ łťťġœśijĹġţŦŵŸŸůġĬńŐŊŏńņōōġŢůťġŅśĴġűŪůij IJįı

ijĴ ijı ōŗŅŔ IJijİijĴ ņņ ņńġťŢŮŢŨŦ ŅŦűŰűġŅŗķġħġœŗĵĵġįġőŰűġŅŗIJĵġħġœŗĶIJġ IJįı

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title

http://hobi-elektronika.net
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

www.vinafix.vn
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, HW PIR
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 30 of 43
5 4 3 2 1
5 4 3 2 1

Power block
CPU OTP
Page 33
D D

Turn Off

Input B+
DC IN Switch Page 34 +3VALWP TDC= 4.6A Ipeak= 6.56A
MAINPWON
+5VALWP TDC= 6.22A Ipeak= 8.88A

RT8205E Page 36
CHARGER
CC:0A~3.3A
CV:13.05V(6/9cell) +3VALW for Vin +1.8VP TDC= 1.51A Ipeak= 2.15A
+5VALW for VCNTL SUSP#

C
ISL6251AHAZ-T Page 35 APL5912 Page 40 C

Battery

+1.1VALWP TDC= 3.5A Ipeak= 5A


SPOK

TPS51218DSCR Page 37

+1.5VP TDC= 4.36A Ipeak= 6.23A


SYSON
B B

TPS51218DSCR Page 39

+1.5VP for Vin


+3VALW for VCNTL
+0.75VSP TDC= 0.35A Ipeak= 0.5A SUSP

+APU_CORE(1.375V~1.5V) APL5336 Page 38

TDC=7.7A
VR_ON
Ipeak=11A

+APU_CORE_NB
TDC=7A
Ipeak=10A
+1.05VP TDC= 4A Ipeak= 5.7A
A ISL6265AHRTZ-T Page 42
SUSP# A

TPS51218DSCR Page 43

Title
POWER BLOCK DIAGRAM
http://hobi-elektronika.net
www.vinafix.vn
Size Document Number Rev
LA7161
Date: Wednesday, January 05, 2011 Sheet 31 of 43
5 4 3 2 1
A B C D

CPU OTP

1
@ PD2
PH1 under CPU botten side :
@ PD1
PJSOT24C_SOT23-3 PJSOT24C_SOT23-3 CPU thermal protection at 90 +-3 degree C
BATT+ Recovery at 50 +-3 degree C
BATT++

3
BATT+

1 1
PL1 VL
1 2 BATT++ VL
+3VALWP

2
100K_0402_1%_TSM0B104F4251RZ
SMB3025500YA_2P

100P_0402_50V8J
1

1
100P_0402_50V8J

PR1

PC2
PC1
1

47K_0402_1%
PC3

PC4
1000P_0402_50V7K
2

2
0.01U_0402_25V7K

2
PR4
2

1
1
PR2
Place clsoe to EC pin 47K_0402_1%
PR3 PH1 1 2
47K_0402_5%
1 2 BATT_TEMP BATT_TEMP <17>

1
1K_0402_1%~D

2
2
@ PC5
PJPB1 battery connector VS
0.1U_0402_16V7K

1
ME@ PJBAT1

1 1 MAINPW ON <33,35>
60$57 2 2
3 PR5
%DWWHU\ 3
4 4
3S <34>
2 1 PR6
5 1 2 PR7
5 +3VALWP

8
6 1K_0402_1%~D 13.7K_0402_1% PQ1
%$7 6 6.49K_0402_1%~D

1
D
7 1 2 3

P
7 +
%$7 10
11
GND 8 8
9 TM_REF1 2
O 1 2
G SSM3K7002FU_SC70-3
,'
GND 9 -

G
PR8 PU1A S

3
LM393DG_SO8
%, SUYIN_200275MR009G186ZL 1 2 EC_SMB_DA1 <17>

4
100_0402_1%
76

1000P_0402_50V7K
16.9K_0402_1%
60'

1
0.22U_0603_25V7K
1

1
60&

PR11
2 2
2 1
VL

PC6

PC7
PR10
*1' 1 2 EC_SMB_CK1 <17> PR9

1
*1'
100K_0402_1%
100_0402_1%

2
PR12
100K_0402_1%

2
PQ2
TP0610K-T1-E3_SOT23-3 COIN RTC Battery
3 1
B+ B+_BIAS ME@
PJRTC1
0.22U_0603_25V7K
1

@
1

PR13
PC8

100K_0402_1% @ PC9
0.1U_0603_25V7K
2

3 3
2

+COINCELL 1 + - 2
+5VALW
PR14
1 2
22K_0402_1%
2

PR15
100K_0402_1%
LOTES_AAA-BAT-054-K01_2P_BATT
1

PR16 D
<35,36> SPOK 1 2 2 PQ3
G SSM3K7002FU_SC70-3
0_0402_5%
S
3
1

@
PC10
2

0.1U_0402_16V7K~D

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/31 Deciphered Date 2011/07/31 Title
BATTERY CONN / OTP / B+_BIAS / RTC

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA7161 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, January 05, 2011 Sheet 32 of 43
A B C D
A B C D

ADPIN VIN +3VALW


+5VALW

PL2
DC_IN_S1 1 2
SMB3025500YA_2P

2
ME@ PJDC1 @ PR18
1 2 PR19

1
1 PC12 PC13
1 PC14 PC15 0_0402_5% 2.2K_0402_5%~D
2 2 100P_0402_50V8J 1000P_0402_50V7K
3 1000P_0402_50V7K 100P_0402_50V8J

1
3 PD4
4

1
1
4 1

5 PR20 DA204U_SOT323~D
5 DOCK_PSID

S
6 6 1 3 1 2 PS_ID <17>
GND 7 PQ4 33_0402_5%~D
GND 8
FDV301N_NL_SOT23-3~D

G
2
100K_0402_1%
ACES_88299-0600 +5VALW

2
PL3 +5VALW

PR21
FBM-L11-160808-601LMT 0603~D
2 1 DOCK_PSID

10K_0402_1%

DA204U_SOT323~D
1

2
1
2

1
C

PR22
@ PD6
2 PQ5
B MMST3904-7-F_SOT323~D

15K_0402_1%~D
@

2
PR25 E

2
PR23
1 2

1
1K_1206_5% @

1
@ PQ6 PD5 @ PR24
TP0610K-T1-E3_SOT23-3 SM24_SOT23 1 2
@ PD7

1
@ PSID_DISABLE# <17>
VIN 1
PR26
2 2 1 3 1
B+ 10K_0402_1%

1K_1206_5%
RLS4148_LL34-2
@ PR27
1 2

100K_0402_5%

100K_0402_5%
1K_1206_5% 1
ACIN

1
PR28

@ PR30

PR29
Precharge detector

2
1 2
VIN1 1K_1206_5% @ @ Min. typ. Max.
2

2
2 2

H-->L 14.589V 14.84V 15.243V


L-->H 15.562V 15.97V 16.388V

1
BATT ONLY
PR31 @
1

@ PQ7
100K_0402_5% Precharge detector
@ PD8 DTC115EUA_SC70-3
Min. typ. Max.
1 2

<17,34> ACOFF 2
1 2
3 PQ8 @ H-->L 6.138V 6.214V 6.359V
DTC115EUA_SC70-3
L-->H 7.196V 7.349V 7.505V
+5VALW RB715F_SOT323-3 2
3

B+
VL @ PR167
3

2 1
2.2M_0402_5%

1
VS PR168 @
VIN 499K_0402_1%

1
@ PR171

2
2

100K_0402_1%
3
PU1B 3

PD9
LM393DG_SO8

8
RLS4148_LL34-2 @ PD16
2 5

P
PD10 <32,35> MAINPW ON +
1

1 7 O
BATT+ 2 1 <34> ACON 3 6

G
-

1
1

PR165 @

1000P_0402_50V7K

1
RLS4148_LL34-2 PR32 PR33 RB715F_SOT323-3 @ PR166 PC93 @

4
Pre_V

1
68_1206_5% 68_1206_5% PC137 @ 191K_0402_1%

PC136
PQ9 499K_0402_1% 0.01U_0402_25V7K
0.1U_0603_25V7K

2
TP0610K-T1-E3_SOT23-3

PRG++ 2

2
2

PR163 @
CHGRTCP 1 2 3 1
200_0603_5% VS
1

PQ42 @ @ PR170
1
1

PR34

1
@ PR169 D RHU002N06_SOT323-3 47K_0402_5%
100K_0402_1% PC17
2 1 2 2 1
PC16 0.1U_0603_25V7K RTCVREF PACIN <34>
2
2

G
34K_0402_1%

1
0.22U_0603_25V7K
2

S @

3
PR35 PQ45
<23,29> 51ON# 1 2
DTC115EUA_SC70-3
22K_0402_1%
2 +5VALW

RTCVREF
1

3
PR164
PU10
200_0603_5%
4 G920AT24U_SOT89 4

3.3V
2

3 2 N2
OUT IN
1

GND PC134
PC135 1U_0805_25V6K
10U_0805_6.3V6M 1
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2010/07/31 Deciphered Date 2011/07/31 Title


DCIN & DETECTOR

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA7161 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, January 05, 2011 Sheet 33 of 43
A B C D
A B C D

CP = 90%*Iadapter (rating); CP = 3.003A

B+ PQ10
Iada=0~3.34A(65W) AO4407A_SO8
ADP_I = 19.9*Iadapter*Rsense
1 8
2 7
PQ11 PQ12 PL13 453215-121LMA90T 1812 3 6
P2
AO4407A_SO8 SI4459ADY-T1-GE3_SO8 PR36 1 2 5
P3 CHG_B+
0.02_2512_1%
VIN 8 1 1 8 @ PJP1

4
1 1

7 2 2 7 1 4 2 2 1 1
6 3 3 6
5 5 2 3 JUMP_43X118 CSIN

2200P_0402_25V7K
0.1U_0603_25V7K
CSIP

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
4

4
VIN VIN1 PR37

1
1 2

PC19

PC21
PC18

PC22
PC20
1

1
VIN

5600P_0402_25V7K
PR40 @ PR41 47K_0402_1%

0.1U_0603_25V7K
PR38 1 2 1 2

2
1

2
PR39 6251VDD 0_0402_5% 0_0402_5%
PC23

1
PC24
47K_0402_1% 200K_0402_1% @ PD12

2.2U_0603_6.3V6K

2
1 2 ACOFF

PC25
ACOFF <17,33>
2

1
PD11 PR42

1
PR43
RB751V-40_SOD323-2 191K_0402_1%~D 10K_0402_1% 1SS355TE-17_SOD323-2
ACSETIN

1000P_0402_50V7K
2

2
3

PQ13 ACSETIN

1
DTA144EUA_SC70-3 @ PR45

1
PC26
10_1206_5%~D
1SS355TE-17_SOD323-2

15K_0402_1%~D
1 2 VIN

1
PR44
2 1 2 PQ14 200K_0402_1%

1
PR46
PD13 DTC115EUA_SC70-3

2
PR47 @ PD14
10K_0402_5%

2
<17> FSTCHG 2 1 PU2 1SS355TE-17_SOD323-2

2
1

PC29 2 1 2 @ PQ17
1

PC27
PR48 1 2 1 24 DCIN 2 1

0.1U_0603_25V7K
VDD DCIN RHU002N06_SOT323-3

1
100K_0402_1%
6251VDD 1 2

1
V1 0.1U_0603_25V7K D

PC28
47K_0402_5% 0.1U_0402_16V7K

PR49
1

1
2 2 23 ACPRN 2 PACIN <33>
ACPRN <35>

3
ACSET ACPRN

2200P_0402_50V7K~D
PQ15 PQ16 G
DTC115EUA_SC70-3 DTC115EUA_SC70-3 @

100K_0402_5%
PR50 S

3
5
6
7
8
6251_EN CSON

1
3 EN CSON 22 1 2
1

1
D
2
20_0603_5% 2

PC31
<32> 3S 2 PC30

PR52
3

2 0.047U_0603_16V7K PQ19
G PR51 CSOP
4 21 1 2

2
CELLS CSOP
S PQ18 150K_0402_1% PR53 20_0603_5% SI4128DY-T1-GE3 @
3

1
@ D

2
RHU002N06_SOT323-3 PC32 4
2

1 2 5 ICOMP CSIN 20 2 1 V1 PQ20 2ACPRN ACPRN <35>

2
6800P_0402_25V7K G
PC34 PC33 PR54 20_0603_5%
SSM3K7002FU_SC70-3
PR55 0.1U_0603_25V7K S

3
1 2 1 2 6 19 1 2

3
2
1
VCOMP CSIP PR58
10K_0402_1% PR56 2.2_0603_5% PL4
0.01U_0402_25V7K PR57 10UH_PCMB063T-100MS_4A_20% 0.02_2512_1%
BATT+
1 2 7 18 LX_CHG 1 2 CHG 1 4
ICM PHASE
1

D
PR59 100_0402_1%
<33> PACIN 1 2 2 PQ21 2 3

1
22K_0402_5% G RHU002N06_SOT323-3 6251VREF 8 17 DH_CHG
<17> ADP_I VREF UGATE

5
6
7
8
S PC35 PR61
3

PC38
10U_0805_25V6K
1 PC37

1 PC39
10U_0805_25V6K
PC36 PQ22

10U_0805_25V6K
1 2 PR62 4.7_1206_5%
PR60 9 16 BST_CHG 1 2 BST_CHGA 2 1 SI4128DY-T1-GE3
CHLIM BOOT

1
2 1 0.1U_0402_16V7K 2.2_0603_5%
<33> ACON <17> IREF

1 2

1
PD15 0.1U_0603_25V7K
0.01U_0402_25V7K

150K_0402_1%
6251ACLIM 10 15 6251VDDP RB751V-40TE17_SOD323-2 4
ACLIM VDDP PC40
1

680P_0603_50V_NPO

2
PR64
1

PQ23 26251VDD
PC41

2
DTC115EUA_SC70-3 PR63 DL_CHG
11 VADJ LGATE 14 4.7_0603_5%

2
100K_0402_1%
2

3
2
1
ACOFF 2 PC42
<17,33> ACOFF
2

12 13 4.7U_0805_6.3V6K

1
GND PGND
PR65
6251VREF 1 2 ISL6251AHAZ-T_QSOP24
3

11.5K_0402_1%
1

3 3

PR66
2.74K_0402_1%~D
CP mode
2

Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05)
Vaclim=2.39*((2.74K//152K)/((2.74K//152K)+(11.5K//152K)))
PR67
<17> CHGVADJ 1 2
6251VDD
18.2K_0402_1%
1

PR71
CC=0.6~3.3A

1
PR68 10K_0402_1%
31.6K_0402_1% PR69 PR70
CHGVADJ CV mode 47K_0402_1% 10K_0402_1%
1 2 ACIN <14,17>
IREF=1*Icharge
2

2
IREF=0.6V~3.3V 0V 3.99V per cell PACIN <33>

1
D

<35> ACPRN 2 ACPRN PR72


G 14.3K_0402_1%
1.91V 4.2V per cell PQ24 S

2
SSM3K7002FU_SC70-3

3.3V 4.35V per cell


4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/31 Deciphered Date 2011/07/31 Title
- CHARGER

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA7161 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, January 05, 2011 Sheet 34 of 43
A B C D
5 4 3 2 1

Note:
Use RT8205E to replace TPS51125 IC can remove RTC refernece LDO
Use RT8205E to replace TPS51427 IC must keep RTC refernece LDO 2VREF_RT8205E 5VALWP
Thermal Design Current=6.22A
3.3VALWP Peak Current =8.88A

1U_0603_10V6K~D
Thermal Design Current=4.6A OCP min=11.55A
H/S RDS(on) 27m ohm(typ),35m ohm(max)

1
Peak Current=6.56A

PC43
OCP min=8.53A L/S RDS(on) 11.7m ohm(typ),14.2m ohm(max)

2
D
H/S RDS(on) 27m ohm(typ),35m ohm(max) FSW 300KHz D

L/S RDS(on) 11.7m ohm(typ),14.2m ohm(max) Delta_Iin=2.4598A


FSW 375KHz Delta_Io=5.6333A
PR73 PR74
Delta_Iin=0.8306A 13K_0402_1%~D 30K_0402_1%~D
+3VALWP 1 2 1 2 +5VALWP
Delta_Io=2.2154A
PR75 PR76
RT8205E_B+ 20K_0402_1%~D 20K_0402_1%~D
1 2 1 2 RT8205E_B+
Typ: 175mA
PJP2
B+ 2 1 +3VLP ENTRIP2 ENTRIP1
2 1
0.1U_0603_25V7K

0.1U_0603_25V7K
2200P_0402_50V7K~D

2200P_0402_50V7K~D
4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D
JUMP_43X118 PR77 PR78
105K_0402_1% 124K_0402_1%
PC44

PC52
1 2 1 2

4.7U_0805_10V6K~D
1

1
PC45

PC46

PC47

PC50

PC48

PC51

PC53
8
7
6
5

5
6
7
8
PU3
2

2
PC49

TONSEL
ENTRIP2

FB2

FB1

ENTRIP1
REF
1
PQ25
AO4466_SO8 25 PQ26
P PAD
AO4466_SO8

2
4 4
7 VO2 VO1 24 SPOK <32,36>
C C
PC54 8 23 PC55
0.1U_0603_25V7K VREG3 PGOOD 0.1U_0603_25V7K
1 PR79 PR80
2
3

3
2
1
2 1 1 2 BST_3V 9 22 BST_5V 1 2 2 1
BOOT2 BOOT1
PL5 0_0603_5%
UG_3V 10
VFB=2.0V 21 UG_5V
0_0603_5%
PL6
3.3UH_PCMB064T-3R3MS_7A_20% UGATE2 UGATE1 2.2UH_PCMC063T-2R2MN_8A_20% +5VALWP
2 1 LX_3V 11 20 LX_5V 1 2
+3VALWP PHASE2 PHASE1
8
7
6
5

5
6
7
8

1
LG_3V 12 19 LG_5V

330U_D_6.3VM_R18M~D

330U_D_6.3VM_R18M~D
LGATE2 LGATE1 PQ28
1

PQ27 PR82

SKIPSEL
PR81 AO4710_SO8 AO4710_SO8 4.7_1206_5%

VREG5
4.7_1206_5% @ PR129 1 1

GND
330U_D_6.3VM_R18M~D

VIN

NC
RT8205EGQW _W QFN24_4X4

EN
1 <32,33> MAINPW ON 1 2

2
+ +

PC57

@ PC58
4 0_0402_5% 4
2

+
PC56

13

14

15

16

17

18

1
@ PR83
PC60
1

499K_0402_1%~D 2 2
2 PC59 1 2 680P_0402_50V7K~D
1
2
3

3
2
1

2
680P_0402_50V7K~D
B+
2

1
100K_0402_1%
1 2

1U_0603_10V6K~D
VL

1
PC61

1
PR84

PC62
@ PR85 Typ: 175mA

22U_0805_6.3V6M
PR86 0_0402_5%
VS

2
499K_0402_1%~D

2
1 2

ENTRIP1 ENTRIP2 @ PR87


Pre_V

1
B 499K_0402_1%~D B

1 2
RT8205E_B+

0.1U_0603_25V7K
2
3

PC63
PQ29B PQ29A
2VREF_RT8205E
DMN66D0LDW -7 2N SOT363-6 DMN66D0LDW -7 2N SOT363-6
5 2
4

2 1
VL
1

PR88
100K_0402_1%
PJP3
<32,33> MAINPW ON 1 PR89 2 2 2 2 1 1
PR90 0_0402_5%
1 2 JUMP_43X118
VS PQ30 PJP4
40.2K_0402_1%~D

2.2U_0603_16V5K~D

100K_0402_1%
DTC115EUA_SC70-3 2 2
+5VALW P 1 1 +5VALW
3
1

PC64
PR91

PQ31 JUMP_43X118
2
1

PR92 D
RHU002N06_SOT323-3

<34> ACPRN 1 2 2
2

G
100K_0402_1%
1

S
3

A A

<17,29> EC_ON 2 PJP5


2 1
2 1 Security Classification Compal Secret Data Compal Electronics, Inc.
PQ32 JUMP_43X118 2010/07/31 2011/07/31 Title
Issued Date Deciphered Date
+5VALWP/+3VALWP
3

DTC115EUA_SC70-3 PJP6
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+3VALW P 2 1 +3VALW Size Document Number Rev
2 1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom LA7161 1.0

www.vinafix.vn
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
JUMP_43X118 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, January 05, 2011 Sheet 35 of 43

5 4 3 2 1
A B C D

1 1

B+
B+

2200P_0402_50V7K~D

0.1U_0603_25V7K

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D
1

1
PC69
PC66

PC67

PC68
PC65
2

2
+1.5VP

5
6
7
8
@ PR93 @ PR94

D
D
D
D
0_0402_5% 100K_0402_1% PQ33
PR95 PC70
1 2 1 2 FDS6298_SO8~D
2

2 2.2_0603_5% 0.22U_0603_25V7K 2
4 G
PU4
PG_1.1VALW P 1 10 BST_1.1VALW P
PGOOD VBST

S
S
S
PR96
1 2 TRIP_1.1VALW P 2 9 UG_1.1VALW P

3
2
1
TRIP DRVH PL7
PR97 36.5K_0402_1%
1 2 EN_1.1VALW P 3 8 SW _1.1VALW P 1 2
<32,35> SPOK EN SW +1.1VALWP
0_0402_5%
FB_1.1VALW P V5IN_1.1VALW P 2.2UH_PCMC063T-2R2MN_8A_20%
4 VFB V5IN 7 +5VALW
1

5
6
7
8

1
@ PC71

10U_0805_6.3V6M~D
RF_1.1VALW P 5 6 LG_1.1VALW P PQ34

0.1U_0402_10V7K~D
0.1U_0402_16V7K RF DRVL 1
SI4634DY-T1-E3_SO8 PR98
1 1
2

1
4.7_1206_5% +

PC74
TP 11 PC75
1

PC72

PC73
2
TPS51218DSCR_SON10_3X3~D 1U_0603_6.3V6M~D 4 330U_D2_2.5VY_R9M

2
2 2 2
PR99

1
470K_0402_5%~D
PC76
2

680P_0603_50V_NPO

3
2
1

2
PR100 PR101
1 2 2 1
3
20K_0402_1%~D 11.5K_0402_1% 3

@ PC77
1 2
0.1U_0603_25V7K
PJP8
JUMP_43X118
+1.1VALWP 1 1 2 2 +1.1VALW

+1.1VALWP
Thermal Design Current=3.5A
Peak Current=5A
OCP min=6.5A
Fsw=290KHZ

Delta I=1.6269A
L/S MOS Rds(on)=5.5m ohm (Typ) ; 6.7m ohm(Max)
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/31 Deciphered Date 2011/07/31 Title
+1.1VALWP

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA7161 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 05, 2011 Sheet 36 of 43
A B C D
A B C D

+1.5V

1
PJP10

1
JUMP_43X79

2
2
PU5
1

1 VIN VCNTL 6 +3VALW 1

2 GND NC 5

1
PC79

1K_0402_1%~D
PC78

1
4.7U_0805_6.3V6K 3 VREF NC 7 1U_0603_10V6K~D

2
PR102 4 8
VOUT NC
9

2
TP
APL5336KAI-TRL_SO8
PQ35

0.1U_0402_16V7K
SSM3K7002F_SC59-3 0.75V +0.75VSP

1
D

1K_0402_1%~D
PR103

PC80
<28> SUSP 1 2 2

1
10K_0402_1% G PR104

2
PC81

0.1U_0402_16V7K
PC82 S

3
10U_0603_6.3V6M~D

2
2
PJP11
+0.75VSP 2 2 1 1 +0.75VS
JUMP_43X118
2 2

+0.75VSP
Thermal Design Current=0.35A
Peak Currnet=0.5A
OCP min=0.65A

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/31 Deciphered Date 2011/07/31 Title
+0.75VSP

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA7161 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 05, 2011 Sheet 37 of 43
A B C D
5 4 3 2 1

D D

PJP12
+1.5VP_B+ 2 1
2 1 B+
JUMP_43X118

2200P_0402_50V7K~D

0.1U_0603_25V7K

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D
1

1
PC84

PC86
PC85
PC83
2

2
+1.5VP

5
6
7
8
1

1
PQ36

D
D
D
D
@ PR105 @ PR106 FDS6298_SO8~D
0_0402_5% 100K_0402_1% PC87
PR107
1 2 1 2 4
2

G
2

2.2_0603_5%
0.22U_0603_25V7K

S
S
S
C C
PU6
PG_1.5VP BST_1.5VP

3
2
1
1 PGOOD VBST 10
PR108
1 2 TRIP_1.5VP 2 9 UG_1.5VP
TRIP DRVH PL8
PR109 45.3K_0402_1%
1 2 EN_1.5VP 3 8 SW_1.5VP 1 2
<17> SYSON EN SW +1.5VP
0_0402_5% 2.2UH_PCMC063T-2R2MN_8A_20%
FB_1.5VP V5IN_1.5VP

330U 2.5V Y D2 LESR15M CX H1.9


4 7 +5VALW
VFB V5IN
1

5
6
7
8

10U_0805_6.3V6M~D
0.1U_0402_10V7K~D
@ PC88 RF_1.5VP 5 6 LG_1.5VP 1
RF DRVL PQ37
1 1
2

0.1U_0402_16V7K PR110

PC91

PC92
11 +
TP PC89 SI4634DY-T1-E3_SO8 4.7_1206_5%
1

PC90
TPS51218DSCR_SON10_3X3~D 1U_0603_6.3V6M~D

2
PR111 2 4 2 2
470K_0402_5%~D

1
PC94
2

680P_0402_50V7K~D

3
2
1

2
PR112 PR113

14.3K_0402_1% 16.5K_0402_1%
1 2 2 1

B @ PC95 B
1 2
0.1U_0603_25V7K

PJP13
JUMP_43X118
1
1 2 2

PJP14
JUMP_43X118
1
+1.5VP 1 2 2 +1.5V

+1.5VP
Thermal Design Current=4.36A
Peak Current=6.23A
OCP min=8.1A
Fsw=290KHZ
A
Delta I=2.1702A A

L/S MOS Rds(on)=5.5m (Typ) ; 6.7m (Max)

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date Deciphered Date Title
+1.5VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA7161
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 05, 2011 Sheet 38 of 43
5 4 3 2 1
A B C D

1 1

+3VALW

+5VALW

1
PJP15

1
JUMP_43X79

2
PC96

2
1U_0402_6.3V6K

2
6

1
PU7 PC97
5

VCNTL
VIN 4.7U_0805_6.3V6K
7

2
POK
VOUT 4

VOUT 3 +1.8VP
PR114

1
<17,28,41> SUSP# 1 2 8 EN FB 2 PC99

1
GND
10K_0402_1% PR115

1
PC98 22U_0805_6.3V6M
9

2
VIN 1.58K_0402_1%

1
PC100 0.01U_0402_25V7K

2
@ PR116 APL5912KAC-TRL_SO8
2.2U_0402_6.3V6M

2
47K_0402_5%

2
0.8V

1
2
PJP16 2

PR117
1 1 2 2 +1.8VS
1.27K_0402_1% +1.8VP

2
JUMP_43X79

+1.8VP
Thermal Design Current=1.51A
Peak Currnet=2.15A
OCP min=2.8A

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/31 Deciphered Date 2011/07/31 Title
+1.8VP

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA7161 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 05, 2011 Sheet 39 of 43
A B C D
5 4 3 2 1

CPU_B+ PL9
HCB4532KF-800T90_1812
1 2 B+
PC101

4.7U_0805_25V6K~D
33P_0402_50V8J~N PQ38
1

5
2 1 @

SI7686DP-T1-E3_SO8

1
+

PC104
PC103 PC102
PR118
2 1 2 1 68U_25V_M_R0.36

2
2
44.2K_0402_1%
UGATE_NB 4
1000P_0402_50V7K

PR119 PL10
1 2 PC105 1UH_PCMC063T-1R0MN_11A_20%
+5VS

3
2
1
D D
10_0603_5% 1000P_0402_50V7K PHASE_NB 1 2
2 1 +APU_COREP_NB
PQ39

1
PC106 PR120 PC107
0.1U_0603_16V7K~N PR122 BOOT_NB
1 2 1 2 PR121

SI7170DP-T1-GE3_POWERPAK8-5
2 1 0_0603_5% 4.7_1206_5%

2
22K_0402_1% 0.22U_0603_10V7K 1
PR123

1 2
1 2 +APU_COREP_NB LGATE_NB 4 + PC108
PR124
1 2 10_0402_5% PC109 330U_D2_2.5VY_R9M
CPU_B+ 680P_0603_50V_NPO
10_0603_5% PR125 2
2 1 APU_VDDNB_RUN_FB_H <7>

2
0_0402_5% +APU_COREP_NB

3
2
1
+5VS +3VS PR126
2 1 PHASE_NB TDC=7A
7.15K_0402_1%
LGATE_NB Peak Current=10A

1
PC110
0.1U_0603_25V7K PHASE_NB OCP min=13A
1

2
PR127 @ PR128 UGATE_NB Iripple= 3.4598A
0_0402_5% 105K_0402_1%
APU_VDDNB_RUN_FB_L Fsw=300KHZ
2

2
1

2
PR132
L/S MOS Rds(on)=3.6m (Typ) ; 4.5m (Max)
PR130 @ PR131
105K_0402_1% 0_0402_5% CPU_B+
10K_0402_1%
1

48

47

46

45

44

43

42

41

40

39

38

37
2

1
@ PR133 PU8
105K_0402_1%

VIN

VCC

FB_NB

COMP_NB

FSET_NB

VSEN_NB

RTN_NB

OCSET_NB

PGND_NB

LGATE_NB

PHASE_NB

UGATE_NB
C C

4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
5
2

<17> VGATE VGATE 1 36 BOOT_NB


OFS/VFIXEN BOOT_NB +APU_CORE_NB
+APU_COREP_NB PJP20

PC112
1

1
PC111
<13> APU_PW RGD_CORE 2 35 BOOT0 PQ40 JUMP_43X118
PGOOD BOOT0
PR134 1 1 2 2
UGATE0 SI7686DP-T1-E3_SO8
2 1 3 34

2
<7> APU_SVD PWROK UGATE0 UGATE0 4
PR135 0_0402_5%
<7> APU_SVC 2 1 4 33 PHASE0
SVD PHASE0
0_0402_5% PR136 PHASE0 PL11
<17> VR_ON 2 1 5 SVC PGND0 32 +5VS

3
2
1
0_0402_5% PR137 PC113 0.36UH_PCMC104T-R36MN1R17_30A_20%
6 31 LGATE0
ENABLE ISL6265AHRTZ-T_TQFN48_6X6 LGATE0 BOOT0 1 2 1 2 1 4
PR139 PR138 +APU_CORE
2 1 2 1 7 30 0_0603_5%
RBIAS PVCC 0.22U_0603_10V7K 2 3
54.9K_0402_1% 61.9K_0402_1% ISP0_1
8 29

1
1
OCSET LGATE1

2
9 28 PC114 PR140
VDIFF0 PGND1 1U_0603_10V6K~D PQ41 PR141

2
4.7_1206_5%
10 27 3.65K_0805_1%
FB0 PHASE1 SI7170DP-T1-GE3_POW ERPAK8-5

1 2

1
11 26 LGATE0 4 PR142
COMP0 UGATE1 PC115
1 2
12 VW0 BOOT1 25 47K_0402_1%
680P_0603_50V_NPO
COMP1
VDIFF1

2
VSEN0

VSEN1
RTN0

RTN1

PC116
ISN0

ISN1
ISP0

VW1

ISP1

3
2
1
FB1

TP
2 1
0.1U_0603_16V7K~N
13

14

15

16

17

18

19

20

21

22

23

24

49 @ PR143 @ PH2
B ISP0 2 1 2 1 B
ISN0 10_0402_5%
ISN0
ISP0

10K_0603_5%_TSM1A103J4302RE
PR144

ISN0
<7> APU_VDD0_RUN_FB_H 2 1 VSEN0
0_0402_5%

ISP0
PR145
+APU_CORE 2 1
10_0402_5%
<7> APU_VDD0_RUN_FB_L 2 PR146 1 RTN0 RTN1
0_0402_5%
+APU_CORE
1
2
10_0402_1%
PR147

PR148 Thermal Design Current=7.7A


0_0402_5%
Peak Current=11A
2
1

+1.8VS OCP min=14.3A


Fsw=300KHZ
PR149
<7> APU_VDD0_RUN_FB_H 2 1VSEN1
0_0402_5%
Choke DCR=1.1 ± 7% mȍ
DIFF_0 VW 0

PR150 PC117 PC118 PC119


2 1 2 1 FB_0 2 1 COMP0 2 1
255_0402_1% 1000P_0402_50V7K
220P_0402_50V8J
2200P_0402_50V7K~D
A A

PR151 PR152 PC120 PR153


2 1 2 1 2 1 2 1
1K_0402_1%~D 54.9K_0402_1% 6.81K_0402_1%
1000P_0402_50V7K

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/31 Deciphered Date 2011/07/31 Title
+APU_CORE/+1.0VALWP

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA7161 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 05, 2011 Sheet 40 of 43
5 4 3 2 1
A B C D

1 1

PJP18
+1.05VP_B+ 2 1 B+
2 1
JUMP_43X118

2200P_0402_50V7K~D

0.1U_0603_25V7K

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D
1

1
PC122
PC121

PC123

PC124

PC125
2

2
1 +3VALW

5
6
7
8
@ PR154 PR155 @
0_0402_5% 100K_0402_1%
PC126 PQ43
PR156
2

1 2 1 2
2

2 2
2.2_0603_5%
0.22U_0603_25V7K 4 AO4466_SO8
PU9
PG_1.05VP 1 10 BST_1.05VP
PGOOD VBST
PR157
1 2 TRIP_1.05VP 2 9 UG_1.05VP

3
2
1
TRIP DRVH PL12
PR158 36.5K_0402_1%
1 2 EN_1.05VP 3 8 SW _1.05VP 1 2
<17,28,39> SUSP# EN SW +1.05VP
0_0402_5% 3.3UH_PCMC063T-3R3MN_6A_20%
FB_1.05VP 4 7 V5IN_1.05VP
VFB V5IN +5VALW
1

5
6
7
8
@ PC127

10U_0805_6.3V6M~D
RF_1.05VP 5 6 LG_1.05VP PQ44

0.1U_0402_10V7K~D
0.1U_0402_16V7K RF DRVL 1
1 1
2

1
+ PC130

PC129
11 PC131 PR159
TP
1

PC128
AO4456_SO8 4.7_1206_5%
1U_0603_6.3V6M~D 220U_D2_4V15M
TPS51218DSCR_SON10_3X3~D 4

2
PR160 2 2 2
470K_0402_5%~D

1
2

PC132

3
2
1
680P_0402_50V7K~D

2
PR161 PR162
3 1 2 2 1 3

20K_0402_1%~D 10K_0402_1%

@ PC133
1 2
0.1U_0603_25V7K

PJP17
2 1 +1.05V
+1.05VP 2 1
JUMP_43X118

+1.05VP
Thermal Design Current=4A
Peak Current=5.7A
OCP min=7.41A
Fsw=290KHZ

Delta I=1.0381A
L/S MOS Rds(on)=4.5m (Typ) ; 5.6m (Max)
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/31 Deciphered Date 2011/07/31 Title
+1.05VP

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA7161 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 05, 2011 Sheet 41 of 43
A B C D
5 4 3 2 1

9HUVLRQ&KDQJH/LVW 3,5/LVW
,WHP 3DJH 7LWOH 'DWH 5HTXHVW ,VVXH'HVFULSWLRQ 6ROXWLRQ'HVFULSWLRQ 5HY
2ZQHU
+APU_CORE/ Depop PC102 (P/N : SF000000W00) X01
1 40 2010/10/04 Compal PC102(H=5.8mm) will impact ME
+APU_COREP_NB logic lower
D D

1. Add PR163, PR164 (P/N : SD013200080) (S RES 1/10W 200 +-5% 0603); X01
PU10 (P/N : SA009200010) (S IC G920AT24U SOT89 REG 3.3V );
PC134 (P/N : SE000001380) (S CER CAP 1U 25V K X5R 0805 H1.25);
HW power share no function PC135 (P/N : SE093106M80) (S CER CAP 10U 6.3V M X5R 0805 H1.25)
2 33 DCIN 2010/10/12 Compal when system at S5 ony with
battery without AC. 2. Modify PD3.pin3 net name, change from +3VLP to RTCVREF
32 BATTERY CONN
/OTP/B+_BIAS 3. Delete PD3, PR17, PC11 =>Cause HW side has alike RTC circuitry
(DZ3 and CZ24)

BATTERY CONN Change PU1A.pin8 net-name from Pre_V to VS X01


3 32 2010/10/18 Compal For reduce S5,S4 power leakage
/OTP/B+_BIAS when system only with battery

C C

BATTERY CONN Change PJRTC1 P/N from SP02000IA00(with Cable) to SP07000H700(w/o cable) X01
4 32 2010/10/18 Compal for ME team change RTC battery
/OTP/B+_BIAS connector.

CHARGER 1. Depop PR52 (P/N : SD02810030L), PQ20 (P/N : SB000009610) X01


5 34 2010/10/18 Compal follow compal power team

忋≽
/DETECTOR new AC-IN, Pre-charge circuits
with circuits, need change 2. Pop item:
design to original pre-charge PD12 (P/N: SC1SS355010)S DIO 1SS355TE-17 SOD323
design and ADP/BAT switch PD14 (P/N: SC1SS355010)S DIO 1SS355TE-17 SOD323
circuits. PR45 (P/N: SD034200380)S RES 1/16W 200K +-1% 0402
PC28 (P/N: SE042104K80)S CER CAP .1U 25V K X7R 0603
PQ17 (P/N: SB502060000)S TR RHU002N06 1N SOT323

CHARGER follow compal power team 1. Pop PQ20 (P/N: SB000009610) (S TR SSM3K7002FU 1N SC70-3)) X02
6 34 2010/10/22 Compal

忋≽
B
/DETECTOR new AC-IN, Pre-charge circuits B
with circuits, need change
design to original pre-charge
design and ADP/BAT switch
circuits.
QAD team highlight BITS issue Add @PR129 (P/N: SD028000080) (S RES 1/16W 0 +-5% 0402)
7 35 +3VALWP 2010/11/24 Compal X03
DF434417: [Rel, PT] OTP (PH1)
/+5VALWP
recovery temperature can't
meet spec.

The recovery temperature spec


is 50 +/- 3degree C.

8 33 DCIN 2010/11/24 Compal follow compal power team 1. Depop : PD7, PD8, PQ6, PQ7, PQ8, PR25, PR26, PR27, PR28, PR29, PR30, PR31 X03
34 CHARGER
/DETECTOR
with 忋≽
new AC-IN, Pre-charge circuits
circuits, need change
design to original pre-charge
2. Add @PC93, @PC136, @PC137, @PD16, @PQ42, @PQ45, @PR165, @PR166, @PR167
, @PR168, @PR169, @PR170, @PR171
design and ADP/BAT switch
circuits. 3. Depop PR41, pop PR40 (P/N: SD028000080) (S RES 1/16W 0 +-5% 0402)
A A
4. Pop PR52 (P/N: SD028100380) (S RES 1/16W 100K +-5% 0402)
, depop PC28, PC31, PD12, PD14, PQ17, PQ20, PR45

5. Change PQ21.2 net name to "ACON" DELL CONFIDENTIAL/PROPRIETARY


Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title

http://hobi-elektronika.net
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

www.vinafix.vn
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PWR PIR
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 42 of 43
5 4 3 2 1
5 4 3 2 1

9HUVLRQ&KDQJH/LVW 3,5/LVW
,WHP 3DJH 7LWOH 'DWH 5HTXHVW ,VVXH'HVFULSWLRQ 6ROXWLRQ'HVFULSWLRQ 5HY
2ZQHU

庫⭡㖻㩊㷔↢㗗⏎
for support DFX team and SMT follow DFX team-Chen. Daniel suggestion: to use the pad length 3.6*2.5mm X03
9 P35 Compal
䨢䂲䎦尉
3VALWP/5VALWP 2010/11/24 PCB footprint for the PL6, PL7, PL8, PL10, PL12 material as PL5 .
AOI detect:
P36 +1.1VALWP
D
Change D

P38 PL6 footprint from (CYNTE_PCMC063T-2R2MN_2P) to (CYNTE_PCMB064T-3R3MS_2P)


+1.5VP PL7 footprint from (CYNTE_PCMC063T-2R2MN_2P) to (CYNTE_PCMB064T-3R3MS_2P)
P40 PL8 footprint from (CYNTE_PCMC063T-2R2MN_2P) to (CYNTE_PCMB064T-3R3MS_2P)
+APU_CORE PL10 footprint from (CYNTE_PCMC063T-1R0MN_2P) to (CYNTE_PCMB064T-3R3MS_2P)
/+APU_COREP_NB PL12 footprint from (CYNTE_PCMC063T-3R3MN_2P) to (CYNTE_PCMB064T-3R3MS_2P)
P41
+1.05VP

CHARGER 2010/11/26 Compal Support EMC team to reduce Add @PL13 and lyaout footprint co-layout with PJP1 X03
10 34
/DETECTOR nosie

CHARGER 2010/12/14 Compal Support EMC team to reduce 1. Pop PL13 (P/N: SM01000DJ00) ( S SUPPRE_ FBMA-L11-453215-121LMA90T 1812) A00
C 11 34 C
/DETECTOR nosie this bead value= 120 ohm(Current rating=9A)

2. Depop PJP1

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title

http://hobi-elektronika.net
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

www.vinafix.vn
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PWR PIR
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 43 of 43
5 4 3 2 1

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