Large Area GTO

Thyristor Development

Ranbir Singh
ranbir.singh@genesicsemi.com
GeneSiC Semiconductor Inc.
43670 Trade Center Place
Suite 155, Dulles VA 20166
703-996-8200 (ph)
Outline

 Rationale for Silicon Carbide for Utility Power

 Goals for SBIR Program
 2D Device Simulations
 Layout Design
 Conclusions & Next Steps

2
Why Silicon Carbide Power Devices?
 FY07 Phase I SBIR from DoE Started Jul 07
 Design of >10kV, 20 KHz switch

Lower On-state Voltage drop for 5-20

Higher Efficiency of circuits
kV Devices (2-3X than Si)

Faster switching speeds (100-1000X Smaller inductors, capacitors;

smaller turn-off times) Compact circuits

Higher Chip temperatures (250- Smaller packages, Smaller thermal

300oC instead of 125oC) management mass

Higher Thermal Conductivity (3.3-4.5

Higher pulsed power, Higher
W/cmK vs 1.5 W/cmK)
continuous current densities
Widebandgap (1016X smaller ni)
3
Applicability of Power Devices
0 2kV 4kV 6kV 8kV 10kV 20kV 40kV

Si MOSFET/Schottky Diode

Si IGBT/PiN Diode

Si GTO

Si Thyristor

SiC MOSFET/JFET/Schottky

SiC BJT/IGBT

SiC GTO Thyristor

4
Size and Weight advantages for Naval
SST
Conventional 2.7 MVA transformer

2.7 MVA Solid-state transformer

Size:10 m3 Estimated Size:3.4 m3

Courtesy: Prof. Alex Huang

5
Goals: Specifications for Devices/Modules

 Voltage 10-16 kV (Phase II Target)

 Current >200 Amp
 Frequency >20 kHz
 Fully Soldered Packaging on all terminals

6
 High Voltage SiC Epitaxial Design


 Epitaxial thickness determines Blocking Voltage

 Major technical challenge from materials growth standpoint
 Anode Area determines continuous Current rating
 Material challenge from defect standpoint

7
 Yield vs Defects Curve
100
Desired
80 Yield
1 .
Yield (%)

60
5
40
10
20 20
30
100 50
0
0 5 10 15 20 25 30 35 40
Device Area (mm2)
8
Epitaxial Design Curves
12000
100m
4H-SiC Assuming
4 0.1361
10000 Ec=1.4408X10 ND
14 -0.7278
BVpp=5.7365X10 ND
Ideal Breakdown Voltage (V)

10 -0.8639
70m W c,pp=7.963X10 ND
8000

6000
40m

4000

15m
2000
8m

0
14 15 16
10 10 10
-3
Doping (cm )
9
 2D Device Simulations for Optimum GTO
Thyristor Design
Net Doping

-2
Signed Log

Accurately predict Blocking 19

0
 17
16

2
Voltage 15
14.65

4
-14.65

 Accurately predict Switching -15

6
-17
-18.99

characteristics

8
10
 Process:

12
 Initial Mesh Design

14
SiC modeling parameters

16


18
 Numerical Methods choice
20

 Simulation Experiments
22
24
26

-8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28

10
Breakdown Voltage Optimization
 Electric Field crowding determines
BV
 BV near junction, or at the edge
results in premature BV

11
 On-State operation of GTO Thyristors
3.5V forward bias taun0=taup0=1 (0.5, 0.25) us
18
10 500
0.34 s
0.76 s
1.28 s
400 0.34 s
1.36 s
electron concentration (cm )
-3

17
10 0.68 s

current (A/cm )
2
300

10
16 200

100

15
10
0
0 20 40 60
2.0 2.5 3.0 3.5 4.0

depth (m) bias (V)

 High Carrier injection results in low on-state drop in

GTO Thyristors
 On-State Voltage drop depends on Carrier Lifetime
12
 Turn-Off Simulations

+ 4000 400
-

3000 300
400K
Turn-Off speed

c u rre n t (A /c m 2 )

v o lta g e (V )

depends on Gate 2000 200

Current cathode voltage

cathode current
 1.6 – 2 micro- 1000 100
seconds typical for
Cathode I = Gate I
0 0
(pulse) 0 -6
1x10 2x10
-6 -6
3x10 4x10
-6

time (s)

13
Cellular and Involute Designs

14
Fabrication Challenges
ideally a double-step sloped edge

anode
n-base

p-base

substrate

 A major fabrication challenge is achievement of sloped

sidewall for high breakdown voltages

15
SEM Pictures of Dry Etching

“Ideal”
Profile
Achieved

Pitting

12o slope
Measured

Trenching
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 Conclusions & Future Work
 Extensive 2D device simulation completed
 Major Experiments on Fabrication completed
 Improved Layouts designed

 Demonstrate GTO devices with good on-state

and switching characteristics
 Package largest area chips for highest current
per chip

17