The CMOS Inverter

Slides adapted from:

N. Weste, D. Harris, CMOS VLSI Design,

© Addison-Wesley, 3/e, 2004
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Outline
Robustness of CMOS Inverter – The Static
Behavior
Switching threshold
Noise Margins

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 Q&A
1.If the width of a transistor increases, the current will
increase decrease not change
2.If the length of a transistor increases, the current will
increase decrease not change
3.If the supply voltage of a chip increases, the maximum transistor
current will
increase decrease not change
4.If the width of a transistor increases, its gate capacitance
will
increase decrease not change
5.If the length of a transistor decreases, its gate capacitance will
increase decrease not change
6. If the supply voltage of a chip increases, the gate capacitance of
each transistor will
increase decrease not change
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 Q&A
1.If the width of a transistor increases, the current will
increase decrease not change
2.If the length of a transistor increases, the current will
increase decrease not change
3. If the supply voltage of a chip increases, the maximum
transistor current will increase decrease not change
4. If the width of a transistor increases, its gate
capacitance will increase decrease not change
5. If the length of a transistor increases, its gate
capacitance will increase decrease not change
6. If the supply voltage of a chip increases, the gate capacitance of
each transistor will
increase decrease not change

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CMOS Inverter Static
Behavior: DC Analysis

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 CMOS Inverter: DC Analysis
DC Response: Vout vs. Vin for a gate Inverter
When Vin = 0 Vout = VDD
When Vin = VDD Vout = 0

In between, Vout depends on transistor current

By KCL, must settle such that
Idsn = |Idsp|
We can solve equations
Graphical solution gives very good insight

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 Transistors operation regions

Current depends on transistor’s operation

region
For what Vin and Vout are nMOS and pMOS
in
 Cutoff ?
 Linear ?
 Saturation ?

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nMOS and pMOS operation

Vgsn = Vin Vgsp = Vin - VDD

Vdsn = Vout Vdsp = Vout - VDD

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Graphical derivation of the inverter DC
response: I-V Characteristics

Make pMOS wider than nMOS such that βn = βp

For simplicity let us assume

Vtn = -Vtp

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Graphical derivation of the inverter DC
response: current vs. Vout, Vin
Load Line Analysis:
For a given Vin: Plot Idsp Vs Vout

Vout must be where |currents| are equal equal

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Graphical derivation of the inverter DC response: Load Line
Analysis
Vin = 0

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Vin = 0.2 VDD

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Vin = 0.4 VDD

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Vin = 0.6 VDD

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Vin = 0.8 VDD

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Vin = VDD

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DC Transfer Curve
Transcribe points onto Vin vs. Vout plot

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DC transfer curve: operating
regions

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Beta Ratio
If βp / βn ≠ 1, switching point will move from VDD/2

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Calledskewed gate

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Noise Margins
How much noise can a gate input see before it does
not recognize the input ?

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Noise Margins
To maximize noise margins, select logic levels at
unity gain
point of DC transfer characteristic

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DC parameters

Input switching threshold: VTH

Minimum high output voltage: VOH

Maximum low output voltage: VOL
Minimum HIGH input voltage: VIH
Maximum LOW input voltage: VIL

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Properties of CMOS Inverter:

High noise margins: VOH and VOL are at VDD and

GND, respectively.
No static power consumption: There never exists a
direct path between VDD and VSS (GND) in steady-
state mode.
Comparable rise and fall times: (under the appropriate
scaling conditions)

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