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Debugging Mechanism
I. INTRODUCTION
In recent years, on-chip bus architecture becomes the Fig. 1 AHB Protocol Checker Architecture
major integration method for implementing a SoC. On-chip
bus specification provide a standard interface that enables IPs
can communicate with each others. Designer just integrates checkers can find errors on real-time environment, we need
his own IPs with third party IPs into the system to more efficient ways to debug the system, only violated rules
significantly reduce design cycles. Thus how to efficiently cannot help designer to rapidly find errors.
make sure the IP functionality works correctly after
We propose an AMBA AHB bus protocol checker based
integrating to dedicate bus architecture is a great challenge.
on monitor-based method. There are total 73 rules we have
There are many verification works based on formal that include master, slave, reset, bus components, and
verification [1] [2] [3] [4] [5] [6]. DUTs are modeled as finite performance issue. In order to improve debugging ability, we
state transition and the properties are written by using propose two debugging mechanisms. An error reference table
Computation Tree Logic (CTL) [7], then uses verification can summarize total errors that have been occurred in
tools [8] [9] [10] to verify DUT’s behaviors. Formal simulation. A windowed trace buffer can capture multiple
verification can verify DUT’s behavior thoroughly, but it error bus signals, which designer can find protocol errors
needs to model all environment components not only the according to these waveforms.
DUTs we want to verify. The other verification is monitor-
based approaches [11] [12] [13] [14]. The specification is II. AHB PROTOCOL CHECKER ARCHITECTURE
defined as a set of rules, and then DUT is checked cycle by Fig. 1 shows AHB Protocol Checker (HPChecker)
cycle during simulation to make sure DUT obeys all these architecture, which contains four main function blocks:
rules. This method is efficient when we integrate several IPs Protocol Checker, Configuration Registers, ERROR
into a pre-verification environment. Reference Table, and Windowed Trace Buffer. We will
But many errors may occur in real-time that monitor-based introduce these four blocks individually.
approaches often cannot find errors in simulation environment.
Thus several commercial verification IPs provide hardware
protocol check to solve this problem. Although protocol
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Fig. 3 The concept of traditional backward tracing and windowed trace
buffer Fig. 5 AMBA EASY verification environment
AHB Bus
Signals[191:0]
Data
Trace
Data Buffer
Write
DataWrite
Error Flag Trace Buffer
Write Controller
Write
ErrorWrite
ERROR[72:0]
Trace
Error Buffer
Data
capture recently three cycle bus signals. Trace Buffer Write 3) Synopsys VIP: The software is available from the
Controller (TBWC) receives Error Flag, when Error Flag Synopsys. It can also verify the IP protocol and also can
asserted, TBWC asserts DataWrite for three cycles that we generate the correct behavior of IP. We use the generated
can store latest three cycle bus signals and ErrorWrite for one correct behavior to correct our HPChecker. This step is used
cycle that we can store what errors occurred. to avoid out misunderstanding on AMBA AHB protocol or
some unconsidered conditions.
In conclusion, we need total 649 (192 * 3 + 73 = 649) bits
per error occurred. If we use 1 KByte memory as trace buffer, We run the simulation on the ARM EASY (Example
we can store up to 20 error occurrences, which can AMBA SYstem) environment like Fig. 5. For every rule, the
significantly reduce the debugging time than traditional constructed case will add to the bus as a master or slave IP and
backward tracing mechanism. then run the simulation.
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TABLE III. SYNTHESIS RESULTS
time T0 T1 T2 T3 T4 T5 T6 T7 REFERENCES
3D(RM)
HCLK
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