techfile vs TLUPlus file extraction difference in ICC,and when are these to be used?

Hi,

techfile (.tf) contains parasitic model & TLUPlus also has this info. Then when does ICC use
these files and what difference does it make in using either of these files?
techfile has additional info like tile, DRC rules, color, lines...etc....

looks like there is slight confusion here

.tf --> there are 2 techfiles one is often called as milkyway.tf while other is cadence.tf
1. milkyway.tf contains all the metal & via info required for router in ICC.
2. cadence.tf contains DRC rules, color, stream_layers, via & metal info etc. This used for
Virtuoso & other cadence tools.

TLUplus VS milkyway.tf
TLUplus -- will contain resistance & cap info about all layer including active , poly , metal
layers ets. -- mostly used by parasitic extraction tools
milkyway.tf -- contains info abt via & metal layers only .predominantly required for place &
route tools

milkyway.tf may also contains parasitic model of wires (as TLUplus files). If you specify in
ICC the TLUplus files, then ICC uses TLUplus files (and did not read parasitic info from .tf
file). If you did not specify TLUplus, then ICC use parasitic info from milkyway.tf.

The advantage of TLUplus is that is is more accurate (than .tf) and you may have different
TLUplus for different RC corners (not PVT corners). And you may specify for ICC different
TLUplus for different scenarios. While milkyway.tf contains parasitic info only for one RC
corner.

Difference between LEF and DEF:

LEF is more metal specific where as DEF is placement specific. DEF defines the absolute location of the
cells as well where as LEF does it only for the layers used. ".lib" is the library or reference book for the
pnr tool to extract timing and logic info required for the cells used in the design.

Library Exchange Format (LEF) is a specification for representing the physical layout of an
integrated circuit in an ASCII format. It includes design rules and abstract information about
the cells. LEF is cadence propitiatory. Design Exchange Format (DEF) represents the
complete physical layout of an integrated circuit while it is being designed. DEF is used to
exchange layout across various physical design tools or with in same tool. So you can call a
DEF as layout exchange format.
Def could contains netlist, routing, placement, scan info, port...
Lef is a simplify view of macro/pad views instead using GDS, that should contain the pin
(metal position size type) and obstruction to allow the PnR to route it.