IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO.
6, NOVEMBER 2008
Power Stage Design of Fourth-Order DC–DC
Converters by Means of Principal
Components Analysis
Antonietta De Nardo, Nicola Femia, Marco Nicolò, Giovanni Petrone, and Giovanni Spagnuolo, Member, IEEE
Abstract—The design of fourth-order dc-dc converters is dis-
cussed in this paper. The Principal Components Analysis is applied
to find the set of passive components which allows to avoid double
resonance in the control-to-output transfer function. The design
of a synchronous SEPIC converter has been studied as an applica-
tion of the proposed design methodology by using a database of real
passive components. The performances of the SEPIC converter de-
signed with the proposed methodology are verified through both
time domain and frequency domain simulations and they are com-
pared with those ones achieved by standard ripple-based design
procedures.
Index Terms—Fourth-order converters, power stage design,
principal components analysis, SEPIC converter.
I. INTRODUCTION
WITCH-MODE dc–dc converters operation is based on the
S temporary storage of the energy inside reactive elements
which is taken from the source and then transferred to the load
through switching devices. The total number of inductors and
capacitors determines the order of the overall system dynamics
in terms of its poles and zeroes.
The use of fourth-order converters, such as SEPIC and Cuk
ones, is often unwelcome because of the possibility to have two
resonance peaks in the control-to-output transfer function, but
also because of a larger number of components as well as a
higher complexity with respect to the most common second-
order converters (e.g. flyback, buck-boost) [1]–[5].
Nevertheless, fourth-order converters often exhibit higher
performances with respect to second-order ones [1]–[3]. For
instance, the noninverting step-up-down output to input ratio
of the SEPIC converter shown in Fig. 1 makes it quite suitable
for LEDs and portable power applications [6] (cell phones,
PDA, and notebook battery interfaces and chargers). This
kind of applications requires very efficient power conversion
in order to avoid the overheating of the portable devices and
Manuscript received November 02, 2007; revised February 13, 2008. Current
version published December 09, 2008. Recommended for publication by Asso-
ciate Editor J. Cobos.
A. De Nardo, N. Femia, G. Petrone, and G. Spagnuolo are with the DIIIE-
University of Salerno, 84084 Fisciano (SA), Italy (e-mail: adenardo@unisa.it;
femia@unisa.it; gpetrone@unisa.it; gspagnuolo@unisa.it).
M. Nicolò is with the National Semiconductor GmbH, Livry-Gargan-Strasse
10, 82256 Fürstenfeldbruck, Germany.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2008.2001914
0885-8993/$25.00 © 2008 IEEE
2867
Fig. 1. SEPIC converter.
to improve the battery life. The need for very low parasitic
resistances in a fourth-order converter results in a system
with two possible high resonance peaks. Unfortunately, the
double resonance phenomenon makes the design of a Voltage
Mode compensation network more involved and prevents from
obtaining high cross-over frequencies, thus resulting in a low
bandwidth system. This is made worse by the very high-quality
factors1 which lower the gain margin of the closed-loop transfer
function.
In the last years many efforts have been made in order to
provide optimized design of power converters: minimization of
the converter weight as well as the optimization of efficiency
and switching frequency is obtained using Lagrangian penalty
in [7]–[9], while a design procedure oriented to power elec-
tronics circuits based on an evolutionary algorithm is introduced
in [10]. The aim of this paper is to present a novel technique
for selecting the passive components for the power stage of
fourth-order dc-dc converters. The proposed approach is not
only based on classical design constraints purely expressing the
voltages and currents ripples limitation [11]–[13], but it is also
aimed at the optimization of the system frequency response. By
following a modern approach to converters design [14], [15],
the optimization technique presented in this paper is able to pro-
vide a set of solutions, selected within all the possible combina-
tions in a database of real components available on the market,
that are suitable for good trade-offs in terms of efficiency, com-
ponents sizes, quality factor as well as dynamics order2 exhib-
ited by the control-to-output frequency response. As usual in
Multi-Objective optimization procedures [17], a set of objec-
tive functions for evaluating the goodness of any design solu-
tion is defined: the Principal Components Analysis (PCA) [18]
is useful in evaluating the quality of the solutions in terms of
1In the frequency response, represents the height of the resonance peak ex-
pressed in dB.
2Meanwhile the system has basically a fourth-order dynamics, under certain
conditions it can present a reduced order behavior, see also [16].
2868 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 6, NOVEMBER 2008

Fig. 2. Voltage mode control scheme. Fig. 3. Power losses budget distribution.

their control-to-output frequency response shape through an an-

alytical manipulation of the state space representation.
The proposed approach allows to obtain a converter dynamic
behaviour that is very similar to that one of a second-order
system: this makes it simpler the design of a voltage mode
compensation network so that a current mode one is no longer
needed.
The paper is organized as follows. Section II describes the
application example that is used in order to illustrate the design
procedure. Section III introduces some basic elements of the
PCA-based approach in order to define the main figures of merit
adopted in the design and optimization approach. In Section IV
the three performance functions are collected, the design space
is defined and the results of the optimization are presented. Fi-
nally, in Section V the best solutions are compared and the im-
provements with respect to solutions obtained by standard de-
sign techniques are highlighted. Conclusions end the paper. Fig. 4. Control-to-output transfer function.

II. THE SEPIC CASE STUDY

In order to illustrate the design procedure introduced in this • , ;
paper, a pilot example consisting in a typical PDA battery inter- • , ;
face application is considered: • , .
• down to 2.7 V; These real values have been retrieved from Coilcraft and
• ; Kemet databases; furthermore, by employing two Renesas
• up to 0.25 A. MOSFET devices with and ,
The change is due to a 4.2-V Li-ion battery discharge the overall efficiency will hit 91.9%. The unwanted outcome
characteristic while the variation can be ascribed to abrupt is represented by the open-loop control-to-output transfer
changes of the PDA state, from standby to full performances function which exhibits two high resonance peaks, as shown
condition and vice-versa. Low-voltage and high-efficiency re- in Fig. 4, where Q factor is 12 at frequency (see also
quirements need of a synchronous rectifier in order to eliminate [22]–[24]).
the inconvenient diode drop losses; besides, slow line transient In practical designs, such problem is overcome by adopting
added to fast load transient requirements induce to choose the the Current-Mode Control method [25]–[27], through a separa-
voltage mode control (see Fig. 2). tion of the complex poles and zeroes that cancels out the reso-
The converter power stage is usually designed according to nance peak, but necessarily leads to an increase in the overall
a set of typical specifications regarding current and voltage rip- system complexity. This means that, regardless of the feedback
ples. The well known ripple-based design [19]–[21] is expressed network design (the Gc(s) in Fig. 2), the crossover frequency
as cannot be placed between and [21]. In fact,
• ; if a minimum gain margin of 10 dB is needed, the must be
• ; placed one decade before . On the other hand, if is
• ; pushed between and , the input voltage changes and
• ; the tolerances of the passive components values lead to an un-
• (Efficiency). certainty on the right side of the zero crossing, where the phase
At the same time, the losses budget distribution, usually repre- value changes suddenly. Consequently, by using the factor
sented by means of a pie plot as in Fig. 3, is accounted for. technique [28], in order to place at 1 kHz, 10 kHz and 50
By assuming a value of the switching frequency kHz, the following solutions are obtained:
, the following passive components specifications are • , ;
find out: • unstable system;
• , ; • , ;
DE NARDO et al.: POWER STAGE DESIGN OF FOURTH-ORDER DC–DC CONVERTERS BY MEANS OF PCA 2869

Fig. 5. Closed loop TF with (a) f = 1 kHz, (b) f = 50 kHz.

where and represent the phase margin and gain margin if the system is asymptotically stable, the following matrices can
respectively, as in Fig. 5. The third solution seems to be the be defined:
suitable in terms of dynamic performances but, as can be de-
duced from Fig. 5(b), there is a dangerous approaching of the
loop gain to the 0 dB line which can cause multiple crossover
(2)
points. Since the frequency response is susceptible of parame-
ters values variations due to tolerances and drifts and also de-
pends on the varying working conditions through the duty cycle
value, the presence of multiple crossover points can lead to the (3)
system instability.
The goal of this paper is to show how to select an optimal as the Controllability and Observabilty Gramian matrices
combination of passive components in order to avoid the which respectively generate the subspaces of controllable and
problem of double crossover and to make the voltage mode observable states [29], [30].
control design easier and effective. Any Gramian matrix defined as
(4)
III. PCA IN SYSTEM ANALYSIS
has the following properties:
The PCA [18] is a mathematical theory inherited from statis- 1) is symmetric and positive semidefinite;
tics and used to obtain low-dimensional approximate descrip- 2) the eigenvelues are real, nonnegative and sorted in de-
tions for multidimensional systems. PCA is mathematically de- creasing order ;
fined as an orthogonal linear transformation that transforms the 3) the eigenvectors are orthonormal ;
data to a new coordinate system such that the greatest variance 4) the eigenvalues are given by
by any projection of the data comes to lie on the first coordi-
nate (called the first principal component), the second greatest
variance on the second coordinate, and so on. It involves the
where is the -row of the matrix .
computation of the eigenvalue decomposition or Singular value
Since the Gramian is symmetric it is also diagonalizable
decomposition of a data set. Such a theory can be adapted to the
Linear Systems (LS) [18] in order to find a new representation (5)
useful for the order reduction. Let it be considered a -order
system Input-State-Output (I-S-O) model: and
(1) (6)

Furthermore, by considering: .. .. .. .. (7)

• state transition matrix; . . . .
• impulse response matrix;
• output transition matrix; where are called principal components values.
2870
If, for example, the new coordinate system based on the
transformation matrix , which diagonalizes the controlla-
bility gramian : peak. Let it be considered the model of a SEPIC converter ob-
(8)
(9)
where
(10)
is defined, the eigenvalues represent the power densities re-
lated to each impulsive response included in the set, while
the eigenvectors represent the associated natural directions.
In this way the new state variables projections are propor-
tional to the energies of state impulsive responses. Now if for a
certain it happens that the first are dominant:
(11)
then it means that the first dimensions of the z-space are most
solicited by an impulsive set of inputs. On the other hand if the
same reasoning with the observability gramian is done
(12)
it can be highlighted that in the new coordinate system if the
(12) is verified then the first k dimensions of the z-space are
dominant in soliciting the output. Combining the two results in
a unified internally balanced3 representation
(13)
it can be found out that the dimensions in the new z-space which
are dominant because contemporarily most affected by an im-
pulsive set of inputs and most determining on the output vari-
ables. With this final transformation, if a dominant subset of
is determined, the first dimensions of the State Space are
much more controllable and observable then the other ones, in
this way the system will practically show a reduced -order dy-
namics.
In conclusion, in a -order system it can be found a transfor-
mation such that in the new state space the diagonal values of
the transformed gramian matrix stand for the weights of each
state space dimension in determining the system dynamics, as
for the gramian properties are in decreasing order, if the first
are much higher then the remaining , the system be-
havior is close to a -order dynamics.
IV. PCA APPLIED TO DC-DC CONVERTERS DESIGN
PCA is often used in order to obtain a simplification in system
analysis with lower order approximations of the data set or of
the system representation. In switching converters analysis and
design an approximation of the model is not needed, but the de-
signer can take advantage of this theory strength in evaluating
if, under certain conditions, the converter shows a reduced order
dynamics. In other words, considering a fourth-order dc-dc con-
verter, one could understand for which values of the parameters
3The existence of the internally balanced representation is demonstrated. The
transformation matrix P can be obtained through different algorithms, see [31].
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 6, NOVEMBER 2008
the system shows the same behavior of a second-order converter,
thus eliminating all the undesired effects of a double resonance
tained through the Averaging State Space technique
(14)
where
(15)
In (15) represents the duty cycle of the SEPIC converter
and the matrices matrices have been obtained by
applying Kirchhoff current and voltage laws to the circuit.
Using the Matlab function BALREAL [31], the internally bal-
anced representation and the matrix related to the system are
obtained. Finally, by defining:
(16)
as the separation threshold value between the dominant prin-
cipal components values and weak ones, the designer can estab-
lish how much the system approaches a second-order behavior
based on how much is greater than one:
means second-order dynamics. (17)
In this way, the optimization of the overall system frequency
response can be redirected to the power stage optimization in-
stead of stressing a compensation network only to patch up a
bad power design. This means that the solution of the problem
is made easier by choosing the passive components smartly. The
idea is to build two sets of components, capacitors and induc-
tors, taken from the same series of the previously selected ones
and with values close to the ripple-based design ones. Then the
circuit performances can be evaluated for all possible combina-
tions of the four reactive elements among the components in the
database through the figures of merit defined as follows:
• separation Threshold ;
• efficiency4;
• damping factor.5 (defined as 1/Q)
Such figures of merit have been considered as the objective
functions of the optimization procedure aimed at their concur-
rent maximization.
The space of parameters that has been considered for the opti-
mization is discretized, in order to account for real components
values allowable on the market. The database of real values
taken from producers’ catalogues and shown in Table I has been
considered.
Consequently, the total number of combinations is
(18)
4Efficiency has been evaluated in Matlab for each combination of parame-
ters considering the losses of all passive components as well as the losses of
switching devices according to [32].
5Damping factor was obtained directly extracting and inverting the value of
the Q factor from the control-to-output transfer function evaluated in Matlab.
DE NARDO et al.: POWER STAGE DESIGN OF FOURTH-ORDER DC–DC CONVERTERS BY MEANS OF PCA 2871

Fig. 6. Solutions set: (a) V , (b) V . Sidebar PCA log(Th)

Fig. 7. Optimal solutions set: (a) V and (b) V . Sidebar gives the efficiency value.

TABLE I
DATABASE OF THE COMMERCIALLY AVAILABLE PARAMETERS
The solutions can be laid out in the three-dimensional
space of the performances or into the four-dimensional space
of parameters.
The design procedure has been conducted at both the extreme
values of the input voltage fixed at the beginning of Section II
for the SEPIC case study, namely, 2.7 and 4.2 V, in the sequel
referred to as and . havior because their higher Th factor make their corresponding
After the exhaustive search, the two Pareto-optimal fronts
[17], composed of a total of four solutions at and eight
solutions at , together with all the 4096 possible solu-
tions have been plotted in Fig. 6. In order to have a simpler inter-
pretation, the solution sets shown in Fig. 6 in the three-dimen-
sional space have been represented by using two bidimensional
plots, shown in Fig. 7, wherein the “Efficiency” dimension was
compressed and shown in the gray-scale palette.
The Pareto front is [17] the set of design solutions that are
nondominated, in the sense that no other solutions exhibit an
improvement of at least one performance figure without wors-
ening the others.
In Fig. 7 the ripple-based design solution introduced in
Section II is compared with the Pareto-optimal ones at both
the input voltage values. The Pareto front obtained at
consists of four solutions, while eight solutions give the Pareto
front at . As can be deduced from Fig. 7 and Table II,
solutions in the upper left sides of the fronts are suitable for
small Q factor, and therefore maximum damping factor, while
solutions in the lower right sides show the best dynamic be-
Bode diagram of the open loop transfer function closer to
that one typical of a second-order circuit. It is worth noting
2872
TABLE II
(a) FIGURES OF MERIT OF THE SOLUTIONS BELONGING TO THE PARETO FRONT
@V . (b) FIGURES OF MERIT OF THE SOLUTIONS BELONGING TO THE
PARETO FRONT @ V
Fig. 8. Comparison among the solutions belonging to the two Pareto fronts in
the space of parameters (C = 4:7 F for all of them): triangles = solutions
@V , circles = solutions @ V . The global best solution should be determined even by means
that Fig. 7(a) and 7(b) show the same 4096 possible design
solutions which have different values of the figures of merit
because of the different value of the input voltage considered
in the two figures. Such a different working condition of the
SEPIC converter leads to almost different values of the damping
factor—solutions of the Pareto front at show a damping
factor that is almost doubled with respect to that one of the
solutions of the Pareto front at —but similar values of
the separation threshold Th and of the efficiency.
Fig. 7 and Table II show the comparison among the solutions
belonging to the two Pareto fronts in the space of performance
functions; Fig. 8 and Table III propose the same comparison in
the space of parameters. This makes it evident that three out of
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 6, NOVEMBER 2008
TABLE III
(a) COMPONENTS VALUES OF THE SOLUTIONS BELONGING TO THE PARETO
FRONT @ V . (b) COMPONENTS VALUES OF THE SOLUTIONS BELONGING
TO THE PARETO FRONT @ V
four solutions (shaded in Table III(a)) of the Pareto front de-
picted in Fig. 7(a), in particular in the left high side, coincide
with three solutions (shaded in Table III(b)), even in this case in
the left high side, of the Pareto front in Fig. 7(b). Such remark
suggests that such solutions represent the tradeoff, because they
exhibit best performances for both values of the input voltage.
On the other hand, if the designer looks at the best solution in
terms of damping, solution #4 in Fig. 7(a) gives the best result
at and solution #8 in Fig. 7(b) gives the best result at
. Solution #3 appears to be a good tradeoff of the three
figures of merit at both voltages. Furthermore, it shows an evi-
dent improvement with respect to the solution obtained by the
classical approach. Better solutions exist, especially if the de-
signer looks at one voltage value only, but they do not show a
high average quality at both low and high input voltages.
of an optimization procedure that does not account for a single
value of at a time, but checking the values of the figures of
merit at and at simultaneously.
V. RESULTS
In this section, a comparison between the solutions belonging
to both the Pareto fronts at different input voltages and the clas-
sical design is introduced by means of frequency domain and
time domain analyses.
By looking at Tables IV(a) and IV(b) it results that at
the current ripple affecting the two inductors is smaller than at at
, but the opposite conclusion holds as far as the voltage
ripples on the capacitors is concerned.
Tables II, III and IV show that all the solutions belonging
to the Pareto fronts have quality factor values (Table II) that
DE NARDO et al.: POWER STAGE DESIGN OF FOURTH-ORDER DC–DC CONVERTERS BY MEANS OF PCA 2873

Fig. 9. (a) PCA Threshold (sidebar) vs. ripples ratios @ V , (b) damping Factor (sidebar) vs. ripples ratios @ V .

TABLE IV
(a) RIPPLES VALUES CORRESPONDING TO THE SOLUTIONS BELONGING TO THE
PARETO FRONT @ V . (b) RIPPLES VALUES CORRESPONDING TO THE
SOLUTIONS BELONGING TO THE PARETO FRONT @ V

are better than the one obtained by the ripple based design and
this is obtained with lower values of inductances (Table III). Fig. 10. (a) Open-loop frequency response of the four selected solutions and
An important issue is that in order to get low values of and (b) magnification to highlight the differences.
high values of (lower order behavior) the values of C1 and
C2 tend to reach the minimum and the maximum capacitance
respectively, meanwhile the inductance values L1 and L2 tend , it can be put in evidence that equalization of the values
to be equalized. Looking at the pictures in Figs. 8, 9, referred to of the current ripples leads the system to
2874 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 6, NOVEMBER 2008

Fig. 11. (a) Open-loop frequency response of four (#1,#4,#6,#8) selected solutions @ V and (b) magnification to highlight the differences.

Fig. 12. Bode diagrams of the best solutions in terms of Th value: (a) @ V , (b) V .

Fig. 13. Bode diagrams corresponding to the solution #3: (a) @ V , (b) @ V .

approach better Th values, while an increased value of the ratio The previous analysis helps the designer in understanding the
gives better values of the damping factor. behavioral dependence from the ripples values as well as from
the components values: this is usually not possible by a simple
DE NARDO et al.: POWER STAGE DESIGN OF FOURTH-ORDER DC–DC CONVERTERS BY MEANS OF PCA
Fig. 14. Bode diagrams corresponding to the solution #3 in presence of a
boundaries, gray = nominal solution (a) @ V , (b) @ V .
Fig. 15. Load step-up transient Vo response, Io = 25 mA ! 250 mA, @
V .
analysis of the transfer function in terms of its poles and zeroes
especially because of its involved symbolic form.
The features of the best solutions in frequency domain can be
also analyzed by looking at Figs. 10 and 11 for both values.
In order to distinguish the different curves corresponding to the
solutions of the Pareto front, only four out of eight of them have
been depicted in Fig. 11 for . and at
As it can be seen in Fig. 10, the transfer functions corre-
sponding to the four solutions at show a much better
shape with respect to those ones depicted in Fig. 4 and refer-
ring to ripple-based designed solutions. There are no high res-
onance peaks and the dynamics is very similar to that one of a
second-order system. By looking at the sequence of solutions,
from #1 to #4, a slight increase in the first resonance peak is
observed, which is related to the increasing efficiency (as evi-
denced in Table II), while the second resonance peak tends to
disappear, as it was expected due to the higher PCA threshold
value. The same comments can be referred to the solutions at
2875
610% tolerance affecting the four reactive parameters: black = upper and lower
Fig. 16. Load step-up transient Vo response, comparison among selected solu-
tions @ V .
, even if such solutions show a higher quality factor (see
Fig. 7). The best solutions in terms of values obtained at
, thus the solutions #8 and #4 respec-
tively, have been also compared in the frequency domain with
the ripple based design solutions.
Diagrams shown in Fig. 12 confirm that each solution opti-
mized for a given input voltage value (#4 @ and #8 @
) exhibits the best behavior at that input voltage value
(#8 in Fig. 12(a) and #4 in Fig. 12(b)). Nevertheless, even if
they deteriorate at the value different with respect to that
one for which they are optimized (#8 in Fig. 12(b) and #4 in
Fig. 12(a)), they keep better than those ones obtained by means
of the ripple based approach. Figs. 13 and 14 show that solu-
tion #3 in both Pareto fronts (see Fig. 7), corresponding to the
2876
same set of parameters at both and , represents
a good compromise and exhibits a small sensitivity with respect
to large uncertainties, e.g., 10%, affecting inductance and ca-
pacitance values.
The four solutions at have been also compared in the
time domain by using PSIM software: a control loop ensuring a
30-kHz crossover frequency and 52 of phase margin for each
one of them [28] has been designed. A load step from 25 to
250 mA has been applied and in Fig. 15 the transient response
given by the Pareto-optimal combinations is compared that one
corresponding to the traditional design. The higher cross-over
frequency shown by the four solutions improves the settling
time during the transient, while the higher resonance peak of
the ripple-based solution has a detrimental effect on the corre-
sponding response even if has a 12 dB attenuation (Fig. 5(a)).
A final look to solutions #1 to #4 at evidences a
reduction of the voltage ripple due to the increasing value of
the inductance and the reduced effect of the second resonance
peak in terms of the pseudo-oscillation inspired by the transient
(Fig. 16), while the total voltage undershoot remains almost the
same.
In conclusion the fourth solution shows a better frequency
response and a higher efficiency than the others, but this is ob-
tained with higher inductance values of the two inductors,
and , whilst the first solution still guarantee good perfor-
mances by using the lowest values of inductance. The solutions
between the first one and the fourth one represent different trade-
offs.
VI. CONCLUSION
In this paper, the problem of the selection of passive compo-
nents of the power stage of fourth-order dc-to-dc converters is
addressed. A novel design procedure based on Principal Com-
ponents Analysis has been introduced, which improves the con-
trol-to-output transfer function of the converter. Passive com-
ponents are selected by PCA-based design so that the frequency
responses of the fourth-order converter, which exhibit couples of
complex poles and zeroes and complicated dependencies on cir-
cuit parameters, is made similar to a second-order system. The
PCA-based design method is supported by a multiobjective op-
timization algorithm which works on a database of real compo-
nents taken from manufacturers’ components lists. PCA-based
design solutions obtained for SEPIC converter result to be much
better compared with those ones given by the usual ripple-based
design approach, both in time and frequency domains.
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Antonietta De Nardo was born in Salerno, Italy, in
1980. She received the M.S. degree in electronic en-
gineering from University of Salerno in September
2005 and she is working towards the Ph.D. degree in
electronic engineering.
Her main research interests are analysis and design
of switching converters.
Nicola Femia (M’94) was born in Salerno, Italy,
in 1963. He received the Doctor degree (honors)
in engineering of industrial technologies (section
Electronics) from the University of Salerno, Italy, in
1988.
From 1990 to 1998, he was an Assistant Professor,
from 1998 to 2001 an Associate Professor and since
2001 he is a Full Professor of Electrotechnics at the
Faculty of Engineering, the University of Salerno.
His main scientific interests are in the fields of circuit
theory and applications and power electronics. He
is coauthor of about 80 scientific papers published in the proceedings of
international symposia and in international journals. He has been Associate
Editor of IEEE TRANSACTIONS ON POWER ELECTRONICS from 1995 to 2003.
2877
Marco Nicolò received the M.E. degree in electrical
engineering from the University of Salerno, Italy, in
the 2005.
In 2007 he joined National Semiconductor Corpo-
ration, Fuerstenfeldbruck, Germany, as Design Engi-
neer. Currently, he is working in the NSC Application
Design Center and his main interest is in power elec-
tronics.
Giovanni Petrone was born in Salerno, Italy, in
1975. He received the “Laurea” degree in electronic
engineering from the University of Salerno, Italy, in
2001 and the Ph.D. degree in electrical engineering
from the University of Napoli “Federico II”, Italy, in
2004.
Since January 2005, he has been an Assistant Pro-
fessor of Electrotechnics at the University of Salerno.
His main research interests are in the analysis and de-
sign of switching converters for telecommunication
applications, renewable energy sources in distributed
power systems, and tolerance analysis of electronic circuits.
Giovanni Spagnuolo (M’98) was born in Salerno,
Italy, in 1967. He received the “Laurea” Degree
in electronic engineering from the University of
Salerno, Italy, in 1993 and the Ph.D. degree in
electrical engineering from the University of Napoli
“Federico II”, Italy, in 1997.
In 1993, he joined the Dipartimento di Ingegneria
dell’Informazione ed Ingegneria Elettrica of the
University of Salerno, Italy, where he was a Post-
doctoral Fellow (1998/99), an Assistant Professor
of Electrotechnics (1999/2003) and, since January
2004, he has been an Associate Professor. His main research interests are in
the analysis and simulation of switching converters, in circuit and systems for
renewable energy sources and in tolerance analysis and design of electronic
circuits. He is an Associate Editor of the IEEE TRANSACTIONS ON INDUSTRIAL
ELECTRONICS.