9124 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO.

11, NOVEMBER 2017

A 50-kW High-Frequency and High-Efficiency

SiC Voltage Source Inverter for
More Electric Aircraft
Shan Yin, Member, IEEE, King Jet Tseng, Senior Member, IEEE,
Rejeki Simanjorang, Senior Member, IEEE, Yong Liu, Student Member, IEEE, and Josep Pou, Fellow, IEEE

Abstract—High power density is required for power con-
verter in more electric aircraft due to the strict demands
of volume and weight, which makes silicon carbide (SiC)
extremely attractive for this application. In this paper, a pro-
totype of 50-kW SiC two-level three-phase voltage source
inverter is demonstrated with a gravimetric power density
of 26 kW/kg (without inclusion of filter). A gate assisted
circuit is introduced to reduce the switching loss. In addi-
tion, the ringings of voltage and current due to parasitic
parameters during the switching transition can also be mit-
igated. A mathematical model with consideration of various
parasitic parameters is developed, which illustrates the par-
asitic effects in high-speed switching SiC power module.
The converter is operated at a switching frequency up to
100 kHz and a narrow dead band of 250 ns. The measured
efficiency is 97.91%.
Index Terms—Efficiency, gate assisted circuit (GAC),
high-speed switching, inverter, parasitic effects, silicon car-
bide (SiC).
I. INTRODUCTION
N CONVENTIONAL aircraft, the power system architec-
I ture is a combination of pneumatic, mechanical, hydraulic,
and electrical hybrid subsystems. However, with the increasing
complexity of each subsystem, the interactions between them
tend to reduce the system efficiency and reliability. The trend
Manuscript received November 30, 2016; revised February 20, 2017
and March 8, 2017; accepted April 5, 2017. Date of publication April 24,
2017; date of current version October 9, 2017. This work was supported
by the National Research Foundation Singapore under the Corporate
Lab@University Scheme, conducted within the Rolls-Royce@NTU Cor-
porate Lab. (Corresponding author: Shan Yin.)
S. Yin was with the Rolls-Royce@NTU Corporate Lab, Nanyang Tech-
nological University, Singapore 639798. He is now with the Microsystem
and Terahertz Research Center, China Academy of Engineering Physics,
Chengdu 610200, China (e-mail: syin1@e.ntu.edu.sg).
K. J. Tseng was with the School of Electrical and Electronic Engineer-
ing, Nanyang Technological University, Singapore 639798. He is now
with the Singapore Institute of Technology, Singapore 138683 (e-mail:
KingJet.Tseng@SingaporeTech.edu.sg).
R. Simanjorang is with the Applied Technology Group, Rolls-Royce
Singapore Pte. Ltd., Singapore 797575 (e-mail: rejeki.simanjorang@
rolls-royce.com).
Y. Liu and J. Pou are with the School of Electrical and Electronic
Engineering, Nanyang Technological University, Singapore 639798
(e-mail: liuy0111@e.ntu.edu.sg; j.pou@ntu.edu.sg).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2017.2696490
0278-0046 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
in moving toward more electric aircraft (MEA) is to replace the
traditional nonelectrical power subsystems by the increasing
use of electric power [1]–[3]. The mechanically driven engine
accessories, oil pump, fuel pump, hydraulic pump, and genera-
tors are replaced by electrically driven machines and generators.
For example, in the Boeing 787 with nonbleed systems, some
functions including cabin environmental control system, wing
ice protection system, auxiliary power unit, and engine starting
have already been electrified.
Hence, the power converter has become one of the key tech-
nologies in MEA. In aircraft applications, a light power con-
verter weight has a direct impact on the operational cost and CO2
emission. Hence, high power density is desired for aerospace
power converters [4]–[8]. To increase the power density, the
power converter needs to operate at high switching frequency to
reduce the filter size. However, the switching frequency of sili-
con (Si) insulated gate bipolar transistors (IGBTs) is normally
restricted below 20 kHz. In addition, there is a trend to directly
mount the electric starter/generator (ESG) with the power con-
verter on the shaft of gas turbine engine [9], which will subject
the power converter to high ambient temperature above 200 °C.
However, the maximum junction temperature of Si-based power
device is normally below 150 °C, which is unacceptable for the
embedded ESG in aircraft.
Silicon carbide (SiC) is regarded as next-generation wide
bandgap material for power semiconductor devices for high
power density and harsh environment applications [10]–[13].
SiC power devices permit high switching frequency and high
junction temperature theoretically up to 600 °C [14]. Implemen-
tation of SiC power converter allows a simpler topology with the
same efficiency compared with Si power converter [15], which
also tends to reduce the complexity of controller design. Hence,
most of the early works on SiC high power density converter
(HPDC) focused on the basic converter topology of three-phase
two-level voltage source inverter (VSI).
An 8-kW inverter prototype was reported in [16] with a power
density of 25 kW/L. It consisted of the fundamental components
for VSI including power module, gate driver, dc-link capacitor,
heat sink, and cooling fans. In [17] and [18], a liquid-cooled
30-kW inverter prototype using a six-pack power module was
demonstrated with 8.35 kW/L or 8.5 kW/kg power density and
98.5% efficiency (at 10 kHz). In [19], a 10-kW inverter pro-
totype using additive manufacturing techniques was presented
YIN et al.: 50-KW HIGH-FREQUENCY AND HIGH-EFfiCIENCY SIC VOLTAGE SOURCE INVERTER FOR MORE ELECTRIC AIRCRAFT
Fig. 1. System diagram of ESG in MEA, where MSC and NSC stand
for machine-side converter and network-side converter, respectively.
with 7 kW/L power density and 99% efficiency (at 10 kHz). In
[20], a 35-kW inverter prototype was reported with 70 kW/L
or 50 kW/kg power density and >98% efficiency (at 20 kHz).
However, these previous works are still limited in low switching
frequency and do not fully utilize the high-frequency benefit of
SiC power devices, which may lead to an increase of filter size.
One of the major challenges in the application of SiC power
converters is the increasing electromagnetic interference (EMI),
which results from higher di/dt and dv/dt ratios [21]. During
the turn-off transition, the high di/dt leads to a voltage over-
shoots due to the stray inductance. While in the half-bridge
circuit, the high dv/dt during the turn-on transition of one tran-
sistor affects the complimentary transistor via the Miller capac-
itance, which may lead to a momentary arm shoot-through or
crosstalk [22], [23].
To mitigate the di/dt effect, since it is undesired to reduce
the switching speed by using a larger gate resistance, the most
straightforward strategy is to reduce the stray inductance in con-
verter layout design. Hence, the laminated structure is widely
accepted in dc bus with the overlapping positive and negative
planes [24], [25]. To mitigate the dv/dt effect, there are four
commonly used solutions from circuit design: negative power
supply, auxiliary gate–source capacitor, turn-off diode, and ac-
tive Miller clamp [26]. A gate assisted circuit (GAC) was further
proposed in [27] and [28], which provides a local low impedance
path for Cdv/dt current. However, these early works are still
limited to separately solve either the di/dt effect or the dv/dt
effect. Since these two effects are strongly dependent on each
other, individually solving one effect may lead to the deteriora-
tion of another effect.
In this paper, a 50-kW prototype of SiC HPDC for the
network-side converter (NSC) in the ESG is demonstrated using
the commercial SiC power module. As Fig. 1 shows, the NSC is
a part of the back-to-back converter, which is the interface be-
tween the starter/generator and ac grid of aircraft. It converts the
ac power with a variable frequency of 300–800 Hz to a constant
frequency of 400 Hz. Hence, this inverter needs to operate at
high frequency and high efficiency to alleviate the filter size and
heat sink size, respectively. In Section II, a mathematical model
for analysis of parasitic effects (di/dt and dv/dt) in high-speed
switching SiC power module is presented with consideration
of various stray inductances. In Section III, a high-speed gate
driver with an improved GAC is demonstrated to reduce the
switching loss. In addition, it mitigates both of the di/dt and
dv/dt effects at the same time, and thus reduces the ringings of
9125
Fig. 2. Schematic of DPT with parasitic parameters.
voltage and current. In Section IV, the switching characteriza-
tion of SiC power module is conducted based on double pulse
test (DPT) experiment. In Section V, the prototype of HPDC is
presented and an open-loop test is conducted. Finally, Section
VI summarizes the main conclusions of this paper.
II. PARASITIC EFFECTS IN HIGH-SPEED SWITCHING SIC
POWER MODULE
The commercial 1.2 kV/100 A SiC power module Wolf-
speed CAS120M12BM2 is used in this paper. It consists of six
parallel SiC metal–oxide–semiconductor field-effect transistors
(MOSFETs), and 12 antiparallel SiC Schottky diodes. The in-
creasing dv/dt and di/dt in the high-speed switching SiC power
module make the parasitic effects crucial in converter design.
The various stray inductances of DPT circuit, shown in Fig. 2,
can be lumped to the three major inductances as follows:
1) gate inductance LG , which consists of stray inductances
of driver chip, layout, and module;
2) drain inductance (or converter loop inductance) LD ,
which consists of stray inductances of dc-link capacitor,
layout, and module; and
3) common source inductance LS , which is the trace be-
tween external source terminal and source pad of die.
Due to the use of Kelvin source in module package, LS is
significantly reduced and cannot be controlled by circuit design.
Hence, the controllable circuit parameters only include RG , LG ,
and LD . As it is a common knowledge, the gate driver should
be as close as possible to the transistor to avoid the potential
LC resonance resulted from LG and gate capacitance. This has
been normally neglected in previous works that deal with Si
MOSFETs [29], [30]. However, with the increasing switching
speed, the gate driver loop may be easily subjected to the LC
resonance. Hence, the importance of LG becomes more sig-
nificant and can no longer be neglected for simplicity. In this
section, the di/dt effect at turn-off and dv/dt effect at turn-on
are investigated, since they have the most significant impact on
switching characteristics. For the classical half-bridge circuit,
the high side (HS) and low side (LS) transistors conduct alter-
natively with a dead time. Hence, to simplify the analysis, only
9126 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 11, NOVEMBER 2017

Fig. 3. Equivalent circuit for analysis of di/dt effect in voltage over-

shoot.

Fig. 4. Stray inductance extraction by Ansys Q3D.

the HS transistor is assumed to be active and the LS transistor

is always OFF.

A. Turn-Off di/dt Effect

The turn-off process of SiC MOSFET is controlled by both
gate driver and load current, especially at light load. Since the
low di/dt at light load only introduces rather insignificant volt-
age overshoot, it is not considered in this section. The equivalent
circuit for ac analysis is shown in Fig. 3. The relationship be-
tween channel current and gate voltage is given by
ich (t) = gm vG S (t) (1)
where gm is the transconductance of the SiC MOSFET. Hence, it Fig. 5. Effect of gate inductance on di/dt effect at different gate resis-
tances when L D = 22 nH.
can be concluded that the di/dt effect is proportional to the gate
voltage. Applying Kirchhoff’s Laws, the following equations
can be derived:
diS (t) diD (t)
vpulse (t) = vD S (t) + LS L + LD + iD (t) RD
dt dt
(2)
diG (t) diS (t)
vG S (t) = LG L − LS L + iG (t) RG L (3)
dt dt
vD S (t) = vD G (t) + vG S (t) (4)
dvD S (t) dvD G (t)
iD (t) = CD S + CG D + gm vG S (t) (5)
dt dt
dvG S (t) dvD G (t) Fig. 6. Effect of gate inductance on di/dt effect at different drain in-
iG (t) = −CG S + CG D (6) ductances when R G L = 10 Ω.
dt dt
iD (t) = iG (t) + iS (t) . (7)
The state-space equations are derived as gate driver loop. Hence, the mutual inductance between the
dX power loop and the gate driver loop is extracted by Ansys Q3D
= A · X + Bu (8) simulation, as shown in Fig. 4. LS L is equivalent to the mutual
dt
inductance and extracted to be 0.8 nH.
Y = C·X (9)
A ramp function with a typical slew rate of 15 V/ns (750 V/50
where X = [vD S (t), vG S (t), iD (t), iG (t)]T , Y = vD S (t), and ns) is set as the input vpulse (t). The effect of RG L , LG L , and
u = vpulse (t). LD on voltage overshoot is investigated by solving the state-
The parasitic capacitances are taken from the datasheet of the space equations numerically in MATLAB. As Fig. 5 shows,
SiC MOSFET module Wolfspeed CAS120M12BM2 at 750 V LG L has a more significant effect on voltage overshoot at small
with CG S = 6.26 nF, CG D = 37 pF, and CD S = 900 pF [31]. gm RG L . It is because the gate voltage ringing is less damped in
is 53.8 S when the drain current is 120 A, and the on-resistance this situation, which magnifies the drain current ringing and
RD is 13 mΩ, which are also obtained from the datasheet. deteriorates voltage overshoot. From Fig. 6, it can be found that
Although a separate gate return (G_RTN) path is adopted for LG L has a slightly more significant effect on voltage overshoot
this module, the strong electromagnetic field still affects the at large LD . It is because the increasing drain–source voltage
YIN et al.: 50-KW HIGH-FREQUENCY AND HIGH-EFfiCIENCY SIC VOLTAGE SOURCE INVERTER FOR MORE ELECTRIC AIRCRAFT 9127

Fig. 9. Effect of gate inductance on dv/dt effect at different gate resis-

tances when L D = 22 nH.

Fig. 7. Analysis of dv/dt effect in the half-bridge configuration.

Fig. 10. Effect of gate inductance (when L D = 22 nH) and drain in-
Fig. 8. Equivalent circuit for analysis of dv/dt effect in shoot-through.
ductance (when L G H = 40 nH) on resonant frequency of gate voltage
ringing.

ringing also enhances the gate voltage ringing, thus leading to

an increase of voltage overshoot.

B. Turn-On dv/dt Effect

As Fig. 7 shows, during the turn-on transition of LS transis-
tor in the half-bridge circuit, a voltage ramp occurs across the
drain–gate terminals of HS transistor. Then, a Cdv/dt current
flows via CG D and gate resistor RG H ,int , RG H ,ext , resulting a
voltage spike across gate–source terminals of the HS transistor. Fig. 11. Schematic of GAC.
A parasitic turn-on (or shoot-through) may occur if it exceeds the
threshold voltage. The equivalent circuit for analysis of dv/dt
result in a more serious voltage overshoot issue. To mitigate this
is shown in Fig. 8, which is quite similar to Fig. 3. Hence, the
di/dt effect, the gate inductance should be minimized as it also
dv/dt effect can also be described by similar equations (1)–(9)
has a significant effect at small gate resistance. To summarize,
except the following two changes: gm = 0 S (HS transistor is
both di/dt and dv/dt effects can be mitigated by reducing the
OFF) and Y = vG S (t). The peak of gate voltage at different
impedance of gate driver at turn-off.
RG H and LG H is shown in Fig. 9. It is also found that LG H has
a more significant effect on gate voltage spike at small RG H .
As Fig. 10 shows, the ringing of gate voltage is dominated by III. DESIGN OF HIGH-SPEED GATE DRIVER WITH GAC
LD instead of LG H . It shows the same resonant frequency as In this section, a high-speed gate driver is presented with
drain–source voltage, which is given by an improved GAC according to our previous work [32], which
1 is inserted between the gate and source terminals of power
f=  . (10) module, as shown in Fig. 11. The auxiliary p-channel MOSFET,
2π (LD + LS )CD S
Fairchild FDS4435BZ, is only active when the main transistor
Based on the discussions above, the most effective strategy is OFF. Compared with n-channel MOSFET used in [28], it does
to mitigate the dv/dt effect is to reduce the gate resistance, as not require complementary gate control signal and the circuit
it provides a low impedance path for Cdv/dt current. However, complexity of gate driver can be reduced. The auxiliary ceramic
a small gate resistance will also increase the turn-off speed and capacitor acts as a local current sink for both discharging current
9128
Fig. 12. Operation principle of GAC: (a) turn-off and (b) turn-on.
and Cdv/dt current. The additional diode is used to clamp
the voltage across capacitor. In hardware implementation,
the GAC should be located as close as possible to the power
module.
The operation principle of GAC is discussed in the following
section. During the turn-off transition of LS transistor, shown in
Fig. 12(a), the LS p-channel MOSFET is ON and GAC provides
a local low impedance (0 Ω) path for the discharging current.
Hence, it enhances the turn-off speed and reduces the switching
loss. Compared with the conventional gate driver with 0 Ω turn-
off resistance, this local discharging path provided by GAC
also permits a small gate inductance, thus reducing the turn-
off voltage overshoot. CA should hold enough negative charge
to make sure the potential is always below zero during this
period. According to the charge balance condition, it should be
accomplished that
CA VE E + Ciss VC C < 0
where Ciss = CG S + CG D . Considering VE E = −5 V and VC C
= 20 V, CA should be at least four times of Ciss .
During the turn-on transition of LS transistor, shown in
Fig. 12(b), the sudden voltage drop across the HS transistor
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 11, NOVEMBER 2017
Fig. 13. Impact of auxiliary capacitance on gate–source voltage spike.
will result in a Cdv/dt current flowing through its Miller ca-
pacitor and gate resistor. The HS p-channel MOSFET is ON
and GAC provides a local low impedance path for the Cdv/dt
current, which mitigates the voltage spike across gate–source
capacitor to eliminate the potential arm shoot-through issue.
Neglecting the stray inductance, the gate voltage spike can be
described as [28]
Crss
ΔVG S = VE E + VD C
Ciss + CA
  
kRG Crss CA2 Ciss + CA
+ 1 − exp − V D C
(Ciss + CA )2 kRG Ciss CA
(12)
where Crss = CG D , VD C = 750 V, k = 15 V/ns, and RG =
1.8 Ω. The relationship between the voltage spike and CA is
shown in Fig. 13. Due to the nonlinear property of Miller ca-
pacitance, three different voltage values at 750, 400, and 100 V
are investigated by simulation. It can be found that the voltage
spike can be significantly reduced when CA is large enough, and
the decreasing tendency will become insignificant when CA is
above 100 nF. Considering the effect of CA on di/dt effect, a
100-nF 50-V surface-mounted-device ceramic capacitor is se-
lected as the auxiliary capacitor, which has enough capability
for turn-off enhancement as well as temporary shoot-through
mitigation.
IV. SWITCHING CHARACTERIZATION OF SIC POWER MODULE
A DPT platform is set up for the switching characterization of
SiC power module, as shown in Fig. 14. The double pulse gate
signal is generated from Texas Instruments digital signal pro-
cessor (DSP) TMS320F28335. A single-layer winding, air core
inductor is made to ensure low equivalent parallel capacitance.
To measure the current, a scaled-down current transformers is
made, which comprises ten turns of isolated wire wound on
a ferrite toroid. It is directly installed on the source terminal
of power module to measure the current flowing through it.
(11)
A laminated three-phase dc bus with thick copper printed cir-
cuit board and multiple parallel film capacitors (900 V/41 μF)
is designed for low stray inductance. The baseplate of power
module is fixed to a hot plate with thermal adhesive for elevated
temperature test.
YIN et al.: 50-KW HIGH-FREQUENCY AND HIGH-EFfiCIENCY SIC VOLTAGE SOURCE INVERTER FOR MORE ELECTRIC AIRCRAFT 9129

Fig. 15. Comparison of switching waveforms between Si IGBT and SiC

MOSFET modules: (a) turn-off and (b) turn-on.

TABLE I
COMPARISON OF SWITCHING ENERGIES BETWEEN SI IGBT AND SIC
Fig. 14. DPT: (a) circuit diagram and (b) experimental setup. MOSFET MODULES

Energy Si IGBT SiC MOSFET Remark

First, the SiC MOSFET power module is compared with a
Si IGBT power module to demonstrate its high-frequency and
high-efficiency advantages [33]. The Si IGBT module used in
this paper is Semikron SKM150GB12T4G (1.2 kV, 150 A),
which is based on Infineon fourth generation trench field-stop
IGBTs. Both power modules are tested with a dc bus voltage of
750 V and a load current of 100 A. The gate resistance for Si
IGBT and SiC MOSFET modules are 1 and 4.7 Ω, respectively.
As Fig. 15 shows, SiC MOSFET module shows faster switching
speed and less current overshoot. However, the ringings of volt-
age and current are more serious than those of Si IGBT module.
As Table I shows, the total switching energy of SiC MOSFET
module is only 28% of Si IGBT module.
The influence of gate resistance on the switching characteris-
tics of SiC power module is evaluated as it is a tradeoff between
the switching loss and EMI. The effectiveness of the proposed
GAC is verified using three different gate resistances (4.7, 7.5,
and 10 Ω). As Fig. 16 shows, the turn-off characteristics are
independent of RG due to the low impedance discharging path
provided by GAC, and the switching speed can be significantly
improved with GAC. The dv/dt and di/dt ratios at turn-off are
measured to be 36 V/ns and 4.6 A/ns, respectively. The effect
of GAC is further evaluated by comparing with 0 Ω turn-off re-
sistance. As Fig. 17 shows, the GAC allows the same switching
speed and switching energy as 0 Ω situation. Moreover, it can
be found that both VD S and ID show slightly smaller ringings.
Hence, the GAC helps to reduce the ringings of voltage and
current in the power converter.
Eo ff 6.29 mJ 1.35 mJ Turn-off
Eon 7.65 mJ 2.73 mJ Turn-on
Er r 2.58 mJ 0.51 mJ Reverse recovery
Etot 16.52 mJ 4.59 mJ Total
Since the GAC has no influence on turn-on transition, only the
gate voltage waveforms at turn-off are compared, as shown in
Fig. 18. All of the ringings of VG S,L S have exceeded the absolute
maximum value of −10 V, which may stress the gate oxide. On
the other hand, the VG S,H S waveforms show slightly ringings,
which are within the range of absolute maximum values of
−10/25 V. It can be found that the ringings of both VG S,L S and
VG S,H S can be reduced with the proposed GAC. The reduced
gate voltage ringing means improved EMI performance and less
gate oxide stress, and thus improves the reliability of gate oxide.
To further evaluate the shoot-through elimination capability
of GAC, the VG S,H S waveforms during turn-on transition are
measured, as shown in Fig. 19. The GAC will limit the gate volt-
age spike (1.4 V) below the threshold voltage (2.5 V) regardless
of gate resistance, which confirms that shoot-through does not
occur.
The relationship between switching energy and load current
at different junction temperatures is shown in Fig. 20. With
the proposed GAC, Eoff almost keeps constant with load cur-
rent increasing. At low load current, it is same as that with-
out GAC, since the turn-off speed is controlled by the diode
in this situation. Hence, the GAC will become less effective
9130 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 11, NOVEMBER 2017
Fig. 16. Effect of GAC on turn-off waveforms at different gate resis-
tances.
Fig. 17. Comparison of turn-off waveforms with GAC and 0 Ω gate
resistance.
Fig. 18. Effect of GAC on gate voltage waveforms at different gate
resistances at turn-off.
at light load. At high load current, Eoff shows a reduction of
up to 70%. Although the GAC leads to a higher Eon at high
load current due to the extra input capacitance of GAC, it is
still much smaller compared with the reduction in Eoff . The
GAC allows a maximum reduction in total switching loss of
20%. Considering the temperature effect for both situations, Eon
shows a slightly decrease at high temperature, whereas Eoff is
independent of the temperature. Hence, the proposed GAC is
also stable for high-speed driving of SiC power module at high
temperature.
Fig. 19. Effect of GAC on HS gate voltage spike at different gate resis-
tances at turn-on.
Fig. 20. Switching energy at different junction temperatures and load
currents: (a) with GAC and (b) without GAC.
V. DEMONSTRATION OF SIC HPDC
A 50-kW prototype of SiC-based VSI is developed for MEA
application. It consists of three SiC power modules, three half-
bridge gate drivers, an interface board, a dc bus bar, and a liquid-
cooled cold plate. The cold plate is made of aluminum base plate
and copper pipe for lighter weight [34]. The gravimetric power
density is measured to be 26 kW/kg without inclusion of input
and output filter. The converter specifications are according to
the requirements in MEA, as shown in Table II.
The circuit diagram of the converter prototype is shown in
Fig. 21. An open-loop test is conducted with sinusoidal pulse-
width modulation generated by a TMS320F28335 DSP. The ac
output side of the inverter is connected to an LCL output filter
YIN et al.: 50-KW HIGH-FREQUENCY AND HIGH-EFfiCIENCY SIC VOLTAGE SOURCE INVERTER FOR MORE ELECTRIC AIRCRAFT 9131

TABLE II
SPECIFICATIONS OF SIC HIGH POWER DENSITY VSI

Parameter Value

Input voltage ±375 Vdc with neutral point

Output voltage 230 Vac (line-to-neutral)
3-phase 4-wire
Output frequency 400 Hz
Switching frequency 60–100 kHz
Efficiency > 95%
Dead time 250 ns

Fig. 23. Experimental waveforms of line-to-neutral voltage and line

current after filter.

Fig. 21. Converter test schematic with LCL filter and R load.

Fig. 24. HS and LS gate voltage waveforms with 250 ns dead time.

Fig. 22. Prototype of 50-kW HPDC and experimental setup for open-
loop test, prototype dimension l × w × h = 33 × 18 × 7 cm3.

Fig. 25. Comparison of harmonics (1st–40th) at two different dead

and then followed by an R load with Y-connection. The values
of converter-side inductance, ac capacitance, and grid-side in-
ductance are 55 μH, 5 μF, and 33 μH, respectively [35]. Due
to the weight constraint in aerospace applications, the inductor
is made of E-type amorphous core to reduce the filter weight,
although it has higher power loss than the ferrite core. The Litz
wire is used for the winding to further reduce the skin effect.
The dc input voltage, dc input current, converter-side/grid-side
line-to-neutral voltage, and converter-side/grid-side line current
are monitored by a Yokogawa WT3000 power analyzer. The
liquid-cooled heat sink is connected to a heat exchanger with
the water coolant at room temperature. The experimental setup
for the open-loop test of converter prototype is shown in Fig. 22.
The experimental waveforms of line-to-neutral voltage and
line current after filter for an input power of 50 kW is shown in
times.
Fig. 23. The rms values of line-to-neutral voltage and line current
are measured to be 227 V and 72 A, respectively. For the high
switching frequency up to 100 kHz, the dead time may constitute
a significant fraction of duty cycle and lead to an increase of total
harmonic distortion, which is mainly due to fifth- and seventh-
order harmonics. In this paper, a small dead time of 250 ns is
adopted, as shown in Fig. 24. This ensures no arm shoot-through
during the current commutation. Fig. 25 shows the comparison
of 1st–40th order harmonics at two different dead times of 550
and 250 ns at full load of 50 kW. It can be found that the fifth-
and seventh-order harmonics are reduced by 52% and 74%,
respectively.
The effect of GAC on converter efficiency and power loss
is evaluated by measuring one converter prototype with two
9132 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 11, NOVEMBER 2017
Fig. 26. (a) Converter efficiency and (b) power loss versus input power
at two different switching frequencies.
different configurations of gate driver circuit. As Fig. 11 shows,
for the conventional gate driver without GAC, RG provides
the current path for both turn-off and turn-on transitions. The
proposed gate driver with GAC provides a fast turn-off path and
thus reduces the switching loss. The converter efficiency and
power loss at different input power and switching frequency
are shown in Fig. 26. It is measured by placing both voltage
and current probes of power analyzer before filter. Study of the
power loss dissipated in the passive components is out of the
scope of this paper and is not included in the filter design.
At full load, the converter efficiency is measured to be 97.91%
with GAC and 97.8% without GAC at 100 kHz. The improve-
ment in efficiency is not so significant due to the high efficiency
that SiC power converters can achieve. Nevertheless, the im-
provement in terms of power loss is much more significant. The
converter loss is reduced by 5% due to the smaller switching
loss with GAC. At 60 kHz, the converter efficiency is measured
to be 98.68% with GAC and 98.53% without GAC, and the
converter loss is significantly reduced by 11.4%. At light load,
the difference between two cases is less significant. It is because
the GAC is less effective at low load current.
VI. CONCLUSION
A prototype of 50-kW SiC three-phase VSI with a gravimet-
ric power density of 26 kW/kg for aerospace application was
demonstrated in this paper. Based on the mathematical model of
parasitic effects, it was found that gate inductance starts to play
a crucial role in switching characteristics with the decrease of
gate resistance. Hence, with the local low impedance discharg-
ing path provided by GAC, the turn-off speed was maximized
(dv/dt 36 V/ns, di/dt 4.6 A/ns), the switching loss was re-
duced, and the turn-off voltage overshoot could be mitigated.
In addition, the GAC provided additional benefit in mitigating
shoot-through. By driving the SiC power module at high-speed
switching, the dead time was minimized to 250 ns without any
arm shoot-through issue. With the proposed GAC, the converter
showed an efficiency of 97.91% at 100 kHz, and the converter
loss was reduced by 5%.
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Electron., to be published.
Shan Yin (S’12–M’16) received the B.Eng. de-
gree in microelectronics from the University of
Electronic Science and Technology of China,
Chengdu, China, in 2010, and the Ph.D. degree
in electrical engineering from the Nanyang Tech-
nological University (NTU), Singapore, in 2016.
In 2013, he was a Research Student and then
a Research Fellow with the Rolls-Royce@NTU
Corporate Lab, NTU. Since September 2016,
he has been with the Microsystem and Tera-
hertz Research Center, China Academy of En-
gineering Physics, Chengdu, China. His research interests include wide
bandgap (SiC and GaN) power device applications, gate driver, and high
power density converter.
9133
King Jet Tseng (S’85–M’88–SM’98) was born
in Singapore. He received the B.Eng. (first
class) and M.Eng. degrees from the Na-
tional University of Singapore, Singapore,
and Ph.D. degree from Cambridge Univer-
sity, Cambridge, U.K., in 1988, 1990 and
1993, respectively, all in electrical engineer-
ing.
He has more than 25 years of academic, re-
search, industrial, and professional experience
in electrical power and energy systems. He has
undertaken numerous contract research projects for major corporations
such as Vestas, Rolls-Royce, and Bosch, and has been holding key
advisory appointments in both public and private sectors in Singapore.
He was awarded numerous research grants and published more than
250 technical papers, and actively reviews and edits papers for major
international journals and conferences. He was appointed the Head of
Power Engineering Division in Nanyang Technological University for the
maximum term of six years. He was the board member of the Singa-
pore Green Building Council, of the Advisory Board of BCA Center for
Sustainable Buildings, and the Energy Standards Committee of Spring
Singapore. He was a Program Coleader of Singapore–Berkeley Building
Efficiency and Sustainability for the Tropics at Singapore’s NRF-
CREATE, and the Founding Director of Electrical Power Systems In-
tegration Laboratory @ NTU, a Rolls-Royce research facility. He has
also founded a number of start-up companies.
Dr. Tseng is a Fellow of the Institution of Engineering and Technology,
the Institution of Engineers Singapore, and the Cambridge Philosophical
Society, as well as a Chartered Engineer registered in U.K. He has held
a number of major appointments in professional societies including the
Chair of IEEE Singapore Section in 2005. He was awarded the Swan
Premium by the IET, the IEEE Third Millennium Medal, the IEEE Region
Ten Outstanding Volunteer Award, and the Long Service Medal (Educa-
tion) from the Singapore Government. Currently, he is also the Professor
and Director of Electrical Power Engineering at Singapore Institute of
Technology, Singapore.
Rejeki Simanjorang (SM’16) was born in Tanah
Karo, Indonesia. He received the B.Sc., M.Eng.,
and Dr.Eng. degrees in electrical engineering
from the University of Sumatera Utara, Medan,
Indonesia, the Bandung Institute of Technol-
ogy, Bandung, Indonesia, and Osaka University,
Osaka, Japan, in 1998, 2002, and 2008,
respectively.
From 2008 to 2013, he was a Researcher
in the National Institute of Advanced Industrial
Science and Technology and R&D Partnership
for Future Power Electronic Technology, Japan. He is currently a Prin-
cipal Technologist in the Rolls-Royce Singapore Pte. Ltd., Singapore,
and leading some collaboration research projects between Rolls-Royce
Singapore and external partners. His research interests include applica-
tion of power converters, design of high power density converters, power
electronics packaging, and electrical health monitoring for power elec-
tronics system.
9134 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 11, NOVEMBER 2017
Yong Liu (S’16) received the B.Eng. degree
in electrical engineering from Wuhan Univer-
sity, Wuhan, China, in 2013, and the M.Sc. de-
gree in electrical engineering, in 2014, from the
School of Electrical and Electronic Engineering,
Nanyang Technological University, Singapore,
where he is currently working toward the Ph.D.
degree at the School of Electrical and Electronic
Engineering, Nanyang Technological University
in electrical engineering.
His research interests include magnetic inte-
gration, harmonic filter, parallel interleaved and electromagnetic interfer-
ence filter design for high power density converter, cooling system for
power converter, and electromagnetic model for wireless power transfer.
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Josep Pou (S’97–M’03–SM’13–F’17) received
the B.S., M.S., and Ph.D. degrees in electrical
engineering from the Technical University of Cat-
alonia (UPC), Catalonia, Spain, in 1989, 1996,
and 2002, respectively.
In 1990, he joined the faculty of UPC as an
Assistant Professor, where he became an As-
sociate Professor in 1993. From February 2013
to August 2016, he was a Professor with the
University of New South Wales (UNSW), Syd-
ney, NSW, Australia. He is currently an Associate
Professor in the Nanyang Technological University, Singapore, where he
is a Co-Director of the Electrical Power Systems Integration Lab, NTU,
and a Program Director of power electronics at the Energy Research In-
stitute, NTU. From February 2001 to January 2002, and February 2005 to
January 2006, he was a Researcher with the Center for Power Electron-
ics Systems, Virginia Tech, Blacksburg, VA, USA. From January 2012
to January 2013, he was a Visiting Professor with the Australian En-
ergy Research Institute, UNSW. Since 2006, he has been collaborating
with Tecnalia Research & Innovation as a Research Consultant. He has
authored more than 230 published technical papers and was involved
in several industrial projects and educational programs in the fields of
power electronics and systems. His research interests include modula-
tion and control of power converters, multilevel converters, renewable
energy, energy storage, power quality, HVdc transmission systems, and
more electrical aircraft and vessels.
Dr. Pou is an Associate Editor of the IEEE TRANSACTIONS ON INDUS-
TRIAL ELECTRONICS and the IEEE JOURNAL OF EMERGING AND SELECTED
TOPICS IN POWER ELECTRONICS.