College Format Document

LATTICE SYNCHRONIZATION TECHNIQUE FOR THREE WIRE
SYSTEMS TO BE SPECIFIC DOUBLE SOGI
I. INTRODUCTION
The power share of renewable energy-based generation systems is supposed to reach
20% by 2030, where wind and photovoltaic (PV) systems are assumed to be the most
outstanding examples of integration of such systems in the electrical network.
The increased penetration of these technologies in the electrical network has

reinforced the already existing concern among the transmission system operators (TSOs)
about their influence in the grid stability; as a consequence, the grid connection standards
are becoming more and more restrictive for distribution generation systems in all
countries .
In the actual grid code requirements (GCRs), special constraints for the operation of
such plants under grid voltage fault conditions have gained a great importance. These
requirements determine the fault boundaries among those through which a grid-
connected generation system shall remain connected to the network, giving rise to
specific voltage profiles that specify the depth and clearance time of the voltage sags
that they must withstand. Such requirements are known as low voltage ride through
(LVRT) and are described by a voltage versus time characteristic .
Although the LVRT requirements in the different standards are very different, as
shown in , the first issue that generation systems must afford when a voltage sag occurs is
the limitation of their transient response, in order to avoid its protective disconnection
from the network. This is the case, for instance, of fixed speed wind turbines based on
squirrel cage induction generators, where the voltage drop in the stator windings can
conduct the generator to an over speed tripping, as shown in [9]. Likewise, variable
speed wind power systems may lose controllability in the injection of active/reactive
power due to the disconnection of the rotor side converter under such conditions .
Likewise, PV systems would also be affected by the same lack of current controllability.
Solutions based on the development of auxiliary systems, such as STATCOMs

and dynamic voltage regulators (DVRs), have played a decisive role in enhancing the
fault ride through (FRT) capability of distributed generation systems, as demonstrated in
1
. Likewise, advanced control functionalities for the power converters have also been
proposed, . In any case, a fast detection of the fault contributes to improving the effects
of these solutions; therefore, the synchronization algorithms are crucial.
In certain countries, the TSOs also provide the active/reactive power pattern to be
injected into the network during a voltage sag; this is the case for the German E-on and
the Spanish Red Eléctrica Española (REE) . This trend has been followed by the rest of
the TSOs; moreover, it is believed that this operation requirement will be extended, and
specific demands for balanced and unbalanced sags will arise in the following versions
of the grid codes worldwide .
2
Regarding the operation of the distributed generation systems under balanced and
unbalanced fault conditions, relevant contributions, such as , can be found in the
literature. These solutions are based on advanced control systems that need to have
accurate information of the grid voltage variables in order to work properly, something
that has prompted the importance of grid synchronization algorithms. In power systems,
the synchronous reference frame PLL (SRF PLL) is the most extended technique for
synchronizing with three-phase systems . Nevertheless, despite the fact that the
performance of SRF PLL is satisfactory under balanced conditions, its response can be
inadequate under unbalanced, faulty, or distorted conditions .
In this paper, three improved and advanced grid synchronization systems are
studied and evaluated: the decoupled double synchronous reference frame PLL (DDSRF
PLL) , the dual second order generalized integrator PLL (DSOGI PLL), and the three-
phase enhanced PLL (3phEPLL) . Their performance, computational cost, and reliability
of the amplitude and phase detection of the positive sequence of the voltage, under
unbalanced and distorted situations, have been evaluated according to experimental grid
fault patterns extracted from , which have been reproduced in a real scaled electrical
network.
In the following sections, the discrete representation of each PLL will be detailed
(see Section IV), due to its great importance in the final implementation of the control,
after a brief description of the different structures (see Section III). Finally, their behavior
will be tested in an experimental setup (see Section VI), and their performance will be
discussed, particularly taking into account the accuracy of the positive-sequence detection
and their computational cost (see Section VII) when considering different faulty
scenarios, covering the response in front of sags, frequency changes, and harmonic
immunity.
3
CHAPTER-1
Phased Lock Loop
1. Introduction
1.1 Phase locked loop
High-performance digital systems use clocks to sequence operations and
synchronize between functional units and between ICs. Clock frequencies and data
rates have been increasing with each generation of processing technology and
processor architecture. Within these digital systems, well-timed clocks are generated
with phase-locked loops (PLLs) and then distributed on-chip with clock buffers. The
rapid increase of the systems' clock frequency poses challenges in generating and
distributing the clock with low uncertainty and low power. This research presents
innovative techniques at both system and circuit levels that minimize the clock timing
uncertainty with minimum power and area overhead.
With the exponential growth of no of internet nodes, the volume of data
transported by its backbone continues to rise rapidly. Among the available
transmission media, optical fibers have highest bandwidth with lower cost, serving
an attractive solution for internet backbone. However, the electronic interface
proves to be the bottleneck in designing high speed digital system. This fact,
combined with the ever-shrinking time to market, indicates that designs based on
flexible modules and macro cells have great advantages. In the optical communication
in a backbone infra structure, flexibility means, for example, programmable bitrates
requiring a PLL with robust operation over a wide range of frequency range. A wide
range PLL could be used by different protocols and applications so that we maximize
the reusability and reduce time to market.
1.2 PLL Fundamentals
Phase-locked loops (PLLs) generate well-timed on-chip clocks for various
applications such as clock-and-data recovery, microprocessor clock generation and
frequency synthesizer. The basic concept of phase locking has remained the same
since its invention in the 1930s. However, design and
implementation of PLLs continue to be challenging as design requirements of a PLL
such as clock timing uncertainty, power consumption and area become more stringent.
4
A large part of this research focuses on the design of a PLL for high-
performance digital system
1.3 PLL Definition

The basic block diagram of a PLL is shown in Figure. A PLL is a closed-loop
feedback system that sets fixed phase relationship between its output clock phase and
the phase of a reference clock. A PLL tracks the phase changes that are within the
bandwidth of the PLL. A PLL also multiplies a low-frequency reference clock, CKref,
to produce a high frequency clock, CKout.
BasicPLL Block Diagram

The basic operation of a PLL is as follows. The phase detector (comparator)
produces an error output signal based on the phase difference between the phase of
the feedback clock and the phase of the reference clock. Over time, small frequency
differences accumulate as an increasing phase error. The difference or error signal
is low-pass filtered and drives the oscillator. The filtered error signal acts
as a control signal (voltage or current) of the oscillator and adjusts the frequency of
oscillation to align φfeedback with φref. The frequency of oscillation is divided down
to the feedback clock by a frequency divider. The phase is locked when the feedback
clock has a constant phase error and the same frequency as the reference clock.
Because the feedback clock is a divided version of the oscillator's clock
frequency, the frequency of oscillation is N times the reference clock.
5
1.4 PLL Component

The block diagram of a charge-pump PLL is shown in Figure. A PLL
comprises of several components: (1) phase or phase-frequency detector, (2) charge-
pump current, (3) loop filter, (4) voltage-controlled oscillator, and (5) frequency
divider. The functioning of each block is briefly described below.
Individual Blocks in PLL Diagram

1.4.1 Voltage Controlled Oscillator
An oscillator is an autonomous system that generates a periodic output without
any input. A CMOS ring oscillator shown in Figure is an example of an oscillator. So
that the phase of a PLL is adjustable, the frequency of oscillation must be tunable. In
the example of an inverter ring oscillator, the frequency could easily be adjusted with
controlling the supply (voltage or current) of inverters. The slope of frequency versus
control signal curve at the oscillation frequency is called voltage-to-frequency (current-
to- frequency) conversion gain, KVCO; VCO=dfVCO/dVctrl evaluated at fVCO. Since
phase is the integral of frequency, the output phase of the oscillator is equal to f ΦVCO
=KVCO.Vctrl dt. In other words, the VCO in the frequency domain (s-domain), is
modeled as
ΦVCO/ Vctrl (s) = KVCO/S;
Ideally, for the linear analysis to apply over a large frequency range,
KVCO, needs to be relatively constant.
A five Stage Ring Oscillator
The PLL reference clock is generated from a crystal. The crystals typically
operate from tens to a few hundreds of MHz's On the other hand; VCOs for clocking
and parallel link applications operate at a few GHz or even ten GHz. For proper
functioning of the phase detector or phase-frequency detector, discussed in the next
section, a frequency divider divides down the VCO frequency to the frequency of the
reference clock.
1.4.3 Phase Detector
The phase detector (PD) compares the phase difference between two input
signals and produces an error signal that is proportional to the phase difference. In the
presence of a large frequency difference, a pure phase detector does not always
generate the correct dir ection of phase error. Phase error accumulates rapidly and
can oscillate between phase error of >180 oand
<180o from cycle to cycle. The average phase detector output
8
1.4.2 Frequency Divider

Contains little frequency information and no valuable phase information.
Since the phase detector is insensitive to frequency difference at the input, upon start-
up when the oscillator's frequency divided by N1 is far from the reference frequency,
the PLL may fail to lock. The problem is known as an inadequate acquisition
range of the PLL. To remedy the problem, a phase-frequency detector (PFD) is used
that can detect both phase and frequency differences. Figure 2.4 conceptually
demonstrates the operation of a PFD for two cases: (a) the two input signals have the
same frequency, and (b) one input has higher frequency than another input. In both
cases, the DC contents of
PFD's outputs, UP and DN, provide information about phase or frequency difference
Operation of a PFD: (a) fref=fCK, φref#φCk and (b) fref>
f1.4.4 Charge pump and loop filter

The charge-pump circuit comprises of two switches that are driven with UP and
DN outputs of PFD as shown in Figure 2.2. The charge-pump injects the charge into
or out of the loop filter capacitor (CCP). The combination of charge-pump and CCP
is an integrator that generates the average of UP (or DN) pulses. This average voltage
adjusts the frequency
9
he subsequent oscillator circuit. Since the VCO introduces another integrator,

the loop gain of a charge-pump PLL has two poles at origin; thus, the closed loop
system is unstable. To stabilize the system, a zero, ωz = 1/RCCP, is introduced in the
loop gain by adding a resistor, R, in series with CCP. The PFD, charge pump and filter
are often modeled with a linear continuous-time model. In reality, the PFD acts as a
pulse modulator system and drives the charge-pump for the duration of pulse width
which is equal to PFD input phase difference, Δφ. The actual phase response is not
linear because phase is cyclical. Furthermore, the phase information is discrete, sampled
at the clock reference frequency.
1.5 Noise and Power Considerations

The primary goal to design a PLL for high-performance digital systems is to
generate an output clock with minimum timing uncertainty. The timing uncertainty
arises from mismatches in devices and noise sources present in the system. Device
mismatches causes a static phase shift (or skew) in the PLL output clock from its
desired phase. Skew can be minimized with a careful layout and increasing the device
size. Skew is generally less critical than jitter because, due to its static nature, the
system can compensate for the static errors. Dynamic noise causes a random phase
shift (or jitter) in the PLL output clock. The noise sources in a PLL are device
electronic noise such as thermal noise or flicker noise and power-supply or substrate
noise.
1.6 Band Width of PLL

The bandwidth of a PLL is the measure of the PLL's ability to track the input
clock and jitter. The closed loop gain 3-dB frequency of the PLL determined the PLL
bandwidth.
The bandwidth is approximately the unity gain point for PLL open loop
response.
A high bandwidth PLL provides a fast lock time and tracks jitter on the reference clock
source, passing it through to the PLL output. A low bandwidth PLL filters out
reference clock jitter, but increase lock time
10
1.7 Phase Noise and Its Causes

Phase noise is the frequency domain representation of rapid, shot-term
random fluctuation in the phase of a wave. The term phase noise is used to describe
phase fluctuation due to random frequency fluctuation of a signal. Phase noise
can be caused by a number of conditions, but is mostly affected by an oscillator's
frequency stability.
The oscillator output is describe by
V (t) =V0sin (2*pi*f*t+ph)
Where f=oscillator frequency and ph=Phase angle
Its instantaneous frequency = f+ (1/2*pi)*(d pi/d t)
If the instantaneous frequency is same as f then the tern (d ph/d t) is zero so
phase noise is zero unless there is a phase noise.
Causes of Phase noise

a. The noise figure of active component such as transistors, integrated circuits,
voltage regulator zeners etc.
b. Thermal noise in passive component such as resistors.
c. Flicker noise in active
components.
d. Noise process in the
oscillator
e. Higher Q crystal will improve lower offset frequencies of phase noise generally less
than
100 Hz offset. As the crystal frequency increases the 'Q' of the crystal
decreases and the
phase noise at lower frequency offset will increases.
f. The crystal has a g-sensitivity that will degrade the phase noise under dynamic
vibration
conditions.
g. Long-term frequency stability can be affected by a long term drift caused by
the crystal
11
CHAPTER-2
2. Architecture of PLL
A wide range PLL requires a wider tuning range of VCO. In this paper, a fully
integrated CMOS VCO with an extended frequency range is described. In section-II,
following a brief overview of conventional architecture for ring type based VCO
design; the proposed architecture is described to solve the problems of conventional
methods. A negative feedback control algorithm automatically adjusting VCO
frequency range is used to extend the frequency range. Also circuits of this wide
tuning range VCO are described.
2.1 Phase frequency Detector
In an analogue mixer a number of different frequencies are generated within the

mixer namely the sum of the frequencies and the difference frequency (otherwise
known as the beat note) when both input frequencies are the same is the phase
difference is zero and the beat note is DC.
Phase detectors are part of a Phase Locked Loop (PLL) and can be either analogue
e.g. mixer or digital e.g. D-type flip-flop. When a mixer is used the output consists of
the sum and difference frequencies.
12
2.1.1 Edge Triggered D-Flip-flop
2.1.2 Differential Amplifier

A differential amplifier is a type of electronic amplifier that multiplies the
difference
between two inputs by some constant factor (the differential gain). Many electronic
devices use
differential amplifiers internally. Given two inputs Vand -
in in V , a practical
+
differential amplifier
gives an output Vout:
Where Ad is the differential-mode gain and Ac is the common-mode gai
13
The common-mode rejection ratio is usually defined as the ratio between

differential- mode gain and common-mode gain:
In the above equation, as Ac approaches zero, CMRR approaches infinity.

Thus, for a perfectly symmetrical differential amplifier with Ac = 0, the output voltage
is given by:
Note that a differential amplifier is a more general form of amplifier than one
with a single input; by grounding one input of a differential amplifier, a single-ended
amplifier results.
Some kinds of differential amplifier usually include several simpler

differential amplifiers. For example, an instrumentation amplifier, a fully differential
amplifier, a negative feedback amplifier, a instrument amplifier, or a isolation amplifier
often includes several op- amps; and those op-amps usually include a long-tailed pair
A differential amplifier is the input stage of operational amplifiers, or op-amps,
and emitter coupled logic gates
Differential amplifiers are found in many systems that utilize negative

feedback, where one input is used for the input signal, the other for the feedback signal.
A common application is for the control of motors or servos, as well as for signal
amplification applications. In discrete electronics, a common arrangement for
14
. implementing a differential amplifier is the long-tailed pair, which is also usually

found as the differential element in most op-amp integrated circuits.
Differential
Amplifier
Current source load Differential amplifier
15
2.1.3 Current Starved Inverter
16
2.1.4 Current starved VCO

VCOs are widely used in PLLs to provide a local clock signal that can be
locked to the frequency and phase of a reference signal. Current-starved VCO
topologies are commonly used because of their wide frequency range of operation,
allowing for tunable designs that can easily accommodate the high-speed
specifications in an RF application.
Description of VCO Circuit Topology
The current-starved VCO, schematically represented in Fig. 1, includes two

components: the input-bias stage and a ring oscillator (RO) structure designed using an
odd number (N>5) of current-starved inverters, where N is the number of RO stages.
The input voltage, Vinvco, sets the current through the input-bias stage and current
mirrors, which subsequently control the current through the current-starved inverters
and control the delay of each stage. The RO oscillates at a period of (Td*2N), where t d
is the delay time of an inverter stage.
Design:
In Inverter we take
Both the NMOS and PMOS are designed for

equal drive i.e.
17
IDCentre =N* *Vdd*Fcentre
Where N=total Number of inverters in series

(must be odd) Fcenter =Centre frequency
The W/L ratio for the N1 and N2 can be calculated from the following
formula
P1 and P2 and are same β as N1 and N2
So W/L ratio for these MOS can be calculated from the following formula
18
2.2 Limited Range Problem Of conventional VCO
The most common used architecture for VCO in CMOS technology is voltage
controlled ring type oscillator. It consists of several delay cells forming a closed
loop as shown in figure. The output clock frequency is determined by the delay
of each delay cell which in turn is controlled by control voltage. A wide frequency
range of oscillator means a wide tuning range of each delay cell. The delay cell is
usually a differential pair with a tail current and some active loading. The delay of
each cell is controlled by the tail current. There are some difficulties associated with
this architecture to achieve the wide tuning range. By using a single tail current, the
tuning range is limited by the control voltage range. The control voltage is usually
constraint by the power supply voltage, i.e. 0 ≤ Vcontrol ≤ Vdd .If we choose the small
tail current, the tail current is still not large enough even that the control voltage
reach the up limit so that the high end frequency range of VCO is small. On the other
hand, if we choose the large tail current, the tail current is still large even that the
control voltage reached the lower limit so that the lower end
frequency range of VCO is large.
Ring type oscillator
18
2.3 Negative feedback architecture

In order to solve the limited range of conventional VCO
architecture, the negative feedback controlled architecture is proposed. Figure shows a
block diagram of the proposed architecture. This architecture includes three blocks: a
negative feedback control voltage generator, a two-input voltage to current converter
and delay cells. The negative feedback generator converts the control voltage which
will be inputted to the voltage-to-current converter block. The two input voltage-to-
current converter converts the two control voltage inputs VC and NVC to current IC
which is supplied to the delay cell block. And finally the delay cell block
delays the input signal to the output signal whose delay is controlled by controlled
current IC.
Block Diagram of proposed architecture
The negative feedback control voltage generator takes the control voltage VC
(supplied by PLL) as an input and generates the negative feedback control voltage NVC.
This block does not need any additional pre-settings such as register bits or reference
voltages for comparators. The purpose of this block is that when the input control
voltage VC is low, the output
19
The relation between current and control voltage
Negativefeedbackcontrolvoltagegenerato
20
2.4 Two input voltage to current converter

The two input voltage-to-current converter accepts the two control voltages
VC and NVC as inputs and generates the control currents to each delay cell in the
VCO. The purpose of this block is to generate the wide range currents with the
limited range control voltage. The output is designed as the subtraction of two current
sources controlled by the two input voltages. The output current is designed as the
subtraction of he two current sources controlled by two input voltages: VC and
NVC. The relations between Iout,Il and I2 and the control voltage are shown in the
diagram. Il increase with increase in VC while I2 decreases. So when the control
voltage VC is small, the effective output current Iout is small although the current
controlled by VC is large. But when VC is high, the effective output current Iout is
equal to Il which is high because the current source I2 is 0 and doesn't reduce Iout.
So the current range is effectively
Twoinputvoltage-to-currentconverter
2l
2.5 Delay cell design

The delay cell is a differential pair with loading and bias controls. The
self biased techniques are used to reduce jitter and process variations. This
arrangement for extended frequency range VCO results a large gain of the VCO.
The above negative feedback scheme
combined with advanced delay cell generates a wide frequency range and low phase
noise VCO.
DelayCellcircuit
22
A High Swing Low Power CMOS Differential Voltage

Controlled Ring
Oscillator.
High Swing Low Power CMOS Differential

OSILATOR
Voltage-ControlledRingOscillato
23
Differential Amplifier Circuit with Positive Feedbac.
In the delay cells proposed in this work, we provide the necessary bias
condition for the circuit to oscillate by means of using the positive partial feedback
generated by Mlf and M2f, as depicted in above figure..
In the upper portion of the circuit, we have M3 and M4 or M5 and M6, that
implements a voltage controlled symmetrical load modifying the delay when the
control voltage Vc is changed, together with the oscillation frequency. The use of this
type of load allows diminishing the sensibility to variations in common mode and also
the phase-noise of the circuit [8]. In the
lower portion of the figure, a two-stage source follower buffer is implemented to drive
the output load composed by pad and instrument capacitances isolating the VCO from
these loads. In the proposed VCO, the operation frequency is determined by the number
of delay cells in the loop. The total capacitance and
resistance associated to the output nodes depends on the operating regions of the
transistors in the delay stages. The biasing scheme composed by transistors M8 to Ml3
provides a controlled bias current and a controlled voltage Ve ' in such a way that the
transistors M4 and M5 stay in the saturation region for the whole control voltage range.
Also this arrangement avoids the cells to loose gain maintaining a linear relation between
the control voltage Ve and the tail current provided to the cells by Mt. Transistor MlO
allow
24
CHAPTER-3
3.GRIDSYNCHRONIZATIONSPECIFICATIONSBASD
O N GCR
Even though several works are published within the field of grid
synchronization, almost all of them are centered on analyzing the individual
dynamic performance of each proposal, without first determining a time response
window within the dynamic behavior of the system under test, which would be
considered to be satisfactory.
In this paper, in order to evaluate the response of the grid synchronization
topologies under test, a common performance requirement for all the structures has been
established in this section, considering the needs that can be derived from the LVRT
requirements.
Despite the fact that the detection of the fault can be carried out with simpler
algorithms, as shown in , the importance of advanced grid synchronization systems lies in
the necessity of having accurate information about the magnitude and
phase of the grid voltage during the fault, in order to inject the reactive power
required by the TSO.In the German standard , it is stated that voltage control must take
place within 20 ms after the fault recognition, by providing a reactive current on the
low voltage side of the
25
Fig. 1. E-on voltage support requirement in the event of grid fault.
Fig. 2. REE voltage support requirement in the event of grid fault.

generator transformer to at least 2% of the rated current for each percent of the
voltage dip, as shown in Fig. 1. 100% reactive power delivery must be possible, if
necessary.
A similar condition is given in the Spanish grid code, where the wind power
plants are required to stop drawing inductive reactive power within 100 ms of a voltage
drop and be able to inject full reactive power after 150 ms, as shown in Fig. 2.
Considering these demands, this paper will consider that the estimation of the voltage
conditions will be carried out within 20–25 ms, as this target permits it to fulfill the
most restrictive requirements, in terms of dynamical response, available in the grid
26
codes. This condition will be extended to frequency estimation; although this parameter
is more related to secondary control algorithms than LVRT, the same time window
between 20 and 25 ms will be considered in this work for the detection of the
disturbance.
3.1 DESCRIPTION OF THE THREE SYNCHRO

NIZATION SYSTEMS
Many of the positive-sequence detection algorithms are based on SRF PLLs .

Despite having a good response under balanced conditions, their performance becomes
insufficient in unbalanced faulty grids (95% of cases), and their good operation is
highly conditioned to the frequency stability, which is incompatible with the idea of a
robust synchronization system. Many authors have discussed different advanced models,
which
Fig. 3.DDSRF-PLL block diagram
27
.
are able to overcome the problems of the classical PLL, using frequency and amplitude
adaptive structures which are able to deal with unbalanced, faulty, and harmonic-
polluted grids. In the framework of these topologies, three PLL structures will be
discussed and evaluated in this paper.
A. DDSRF PLL
The DDSRF PLL, published in [34] and [41], was developed for improving the
conventional SRF PLL. This synchronization system exploits two synchronous reference
frames rotating at the fundamental utility frequency, one counterclockwise and another
one clockwise, in order to achieve an accurate detection of the positive- and negative-
sequence components of the grid voltage vector when it is affected by unbalanced grid
faults. The diagram of the DDSRF PLL is shown in Fig. 3.
When the three-phase grid voltage is unbalanced, the fundamental positive-
sequence voltage vector appears as a dc voltage on the dq+1 axes of the positive-sequence
SRF and as ac voltages at twice the fundamental utility frequency on the dq−1 axes of the
negative-sequence SRF. In contrast, the negative sequence voltage vector will cause a dc
component on the negative-sequence SRF and an ac oscillation on the positive sequence
SRF. Since the amplitude of the oscillation on the positive-sequence SRF matches the dc
level on the negative sequence SRF and vice versa, a decoupling network is applied to
signals on the dq positive/negative SRF axes in order to cancel out such ac oscillations.
Low-pass filters (LPFs) in Fig. 3 are responsible for extracting the dc component from
the signal on the decoupled SRF axes. These dc components collect information about
the amplitude and phase angle of the positive- and negative-sequence components of the
grid voltage vector.
Finally, the PI controller of the DDSRF PLL works on the decoupled q-axis
signal of the positive-sequence SRF (v*q+1) and performs the same function as in an
SRF PLL, aligning the positive-sequence voltage with the d-axis. This signal is free of ac
components due to the effect of the decoupling networks; the bandwidth of the loop
controller can be consequently increased.
28
B. DSOGI PLL
The operating principle of the DSOGI PLL for estimating the positive- and
negative-sequence components of the grid voltage vectors is based on using the
instantaneous symmetrical component (ISC) method on the αβ stationary reference
frame,
Fig. 4. DSOGI-PLL block diagram.
as explained in . The diagram of the DSOGI PLL is shown in Fig. 4. As it can be

noticed, the ISC method is implemented by the positive-sequence calculation block.
To apply the ISC method, it is necessary to have a set of signals, vα –vβ , representing
the input voltage vector on the αβ stationary reference frame together with another set
of signals, qvα –qvβ , which are in quadrature and lagged with respect to vα –vβ . In
the DSOGI PLL, the signals to be supplied to the ISC method are obtained by using a
dual second order generalized integrator (DSOGI), which is an adaptive band- pass
filter based on the generalized integrator concept . At its output, the DSOGI
provides four signals, namely, V’α and v’β, which are filtered versions of vα and vβ,
respectively, and qv’α and qv’β, which are the in-quadrature versions of v’α and v’β.
29
A conventional SRF PLL is applied on the estimated positive-sequence voltage vector,

v+αβ, to make this synchronization system frequency adaptive. In particular, the v+αβ
voltage vector is translated to the rotating SRF, and the signal on the q-axis, v+q , is
applied at the input of the loop controller. As a consequence, the fundamental grid
frequency (ω’) and the phase angle of the positive-sequence voltage vector (θ+’ ) are
estimated by this loop. The estimated frequency for the fundamental grid component is
fed back to adapt the center frequency ω’ of the DSOGI. for improving the conventional
SRF PLL. This synchronization
C. 3phEPLL
The enhanced phase-locked loop (EPLL) is a synchronization system that has proven to
provide good results in single phase synchronization systems [43]. An EPLL is
essentially an adaptive band-pass filter, which is able to adjust the cutoff frequency as a
function of the input signal. Its structure was later adapted for the three-phase case [44],
in order to detect the positive-sequence vector of three-phase signals, obtaining the
3phEPLL that is represented in Fig. 5.
In this case, each phase voltage is processed independently by an EPLL. This block
filters the input signal and generates two sinusoidal outputs of the same amplitude and
frequency, v’n and jv’n, the second one being 90◦ with respect to v’n. The resulting signals
constitute the input for the computational unit. Owing to these in-quadrature signals, the
instantaneous positive-sequence voltage component, v+abc, can be estimated by means of
using the ISC method.
30
The performance of the different structures under test is really dependent on their final
digital implementation, particularly on
Fig. 5. 3phEPLL block diagram.
Fig. 6. Phase and magnitude estimation loop of the DDSRF PLL.

3.2 Discrete Implementation
the discretization approach made to their continuous equations . This implementation

is critical and should be studied in detail as a straightforward implementation can give
rise to additional delays in the loop that hinder the good performance of the PLL. Some
methods, such as the forward Euler, the backward Euler, and the Tustin (trapezoidal)
numerical integration, offer a good performance when used for discretizing other
synchronization systems, as shown in . However, Euler methods can be inadequate under
certain conditions, due to the need of introducing additional sample delays .
31
according to the specific needs of the presented topologies, this section will describe the
discrete representation of each PLL
individually. In order to facilitate the comprehension of the process, the different
building blocks that appear at Figs. 3– will be referenced. The values of the different
parameters used in each case are summarized in the Appendix.
A. DDSRF-PLL Discretization
The discrete model of this PLL can be easily obtained since the continuous
representation of several parts does not change in the discrete domain. This is the case
for the transformation blocks Tαβ, Tdq+1, and Tdq−1 , whose description can be found in
general scope literature .
1.Positive- and Negative-Sequence Decoupling Networks: The decoupling

network constitutes one of the most important contributions of this synchronization
method. The discrete equations of these blocks are shown in (1), being almost the same
as in the continuous domain . It is just necessary to consider one sample delay of
in order to avoid algebraic loops.
2.Phase and Magnitude Estimator Discretization: In the DDSRF PLL, the

decoupling network appears embedded in the classical SRF-PLL loop (see Fig. 6).
However, this does not affect the discretization of the phase and magnitude estimator
since v*d+1 and v*q+1 act as the input of this block
32
The discrete controller and the integrator can be built using a backward numerical
approximation. The frequency and phase can then be represented in the z-domain (2),
considering v*q+1 as the error to be minimized. In this equation, a feed forward of the
nominal frequency is given by means of ωff
33
Finally, sample-based representation gives rise to (3), which are the expressions to be
implemented
In these equations, a frequency feed forward has been introduced as an initial condition
to ω’.
3) LPF Block Discretization: The amplitudes of the dq positive- and negative-

sequence components are the outputs of the decoupling networks. However, four infinite
impulse response (IIR) LPFs extract the ripple from each sequence estimation in order to
reinforce the performance of the PLL in case of harmonic pollution. A first-order filter
with a cutoff frequency ωf , equal to half of the grid frequency, was originally proposed
in [41]; hence, the same transfer function has been implemented in this paper for
evaluation purposes in
34
B. DSOGI-PLL Discretization
1. DSOGI-QSG Block Discretization: As was previously mentioned in Section
II, the DSOGI-based quadrature signal generator (QSG) of Fig. 4 consists of two
independent and decoupled second-order generalized integrators (SOGIs). Therefore,
each SOGI-based quadrature signal generator can be discretized individually, thus
facilitating its mathematical description. In Fig. 7, the block diagram of the implemented
SOGI is shown.
Fig. 7. Quadrature signal generator based on a second order generalized integrator

(SOGI QSG).
This quadrature signal generator (QSG) is a linear system itself; therefore, a discrete
representation can be systematically obtained if the continuous state space is previously
deducted. The equations of the SOGI state space appear detailed in (5). where v
constitutes the input while v’ and qv’ are the two in-quadrature output signals
35
The discretization of this system has been performed using trapezoidal

integrators, as they offer a better detection of the phase, which is important when dealing
with sinusoidal signals . The symbolic values of each matrix of (7) are detailed in (6),
shown at the bottom of the page. In these matrices, Ts is the sampling time of the discrete
system, ω’[n] is the estimated frequency magnitude, which comes from the estimation
made at the SRF-PLL block at each computation step, and k is the
SOGI gain
The discrete state space of (6) is obtained from the continuous representation by means
of the mathematical procedure presented
36
Fig. 8. State variables of the SRF-PLL block.
where Ts is the sampling time.
37
The resulting discrete system is the best option as it reduces the need of using
additional delays for breaking algebraic loops that appear using other methods which do
not consider the SOGI QSG as a whole.
2. SRF PLL Discretization: The frequency and phase detection is obtained by
means of the SRF PLL shown in Fig. 8. The discretization of the controller and
the integrator is performed using the backward numerical approximation.
The frequency and phase can then be represented in the z-domain, as shown in (9), where
v+q constitutes the error to be minimized
It can be noticed that the previous equations in (9) are equal to (2), as, in both cases, an
SRF PLL is implemented. Likewise, the sample-based representation of (9) can be
written as shown in
C.3phEPLL Discretization
This three-phase grid synchronization system exploits the EPLL as a quadrature
signal generator. An independent EPLL is used for processing each one of the three-
phase voltages. The same EPLL structure is applied again to detect the magnitude and
phase of the positive-sequence voltage component.
38
1) QSG Block—EPLL Discretization: The block diagram of the EPLL

implemented in this paper is presented in Fig. 9.
Fig. 9. Quadrature signal generator based on an EPLL structure.

According to this diagram, the state space representation of the EPLL in the continuous
domain can be written as shown in
The discrete state space variable representation was described in using a forward Euler
approximation to reach satisfactory results; therefore, the same method has been
implemented here
39
Finally, after the state variables are calculated, the EPLL output can be obtained by (13),
generating the two quadrature signals
This type of discretization method needs a more accurate tuning, due to the fact
that the stable regions of the s-plane and z-plane are different [52]. However, its major
simplicity, compared to the Tustin or backward integration, benefits from the
computational speed of this block.
1) Computational Block Unit: The description for this block is the same in both discrete
and continuous domains. Neverthe- less, specific equations are used in this paper, as
shown in (14).
40
2) Phase and Magnitude Detection Block: This element is based on another EPLL,
which is responsible for estimating the phase and the magnitude of the positive-
sequence fundamental component. Its discretization is equal to that shown in (12)
Fig. 10. Experimental setup for testing three different synchronization algorithms.
41
TABLE I
PROPERTIES OF THE TESTING VOLTAGE SAGS
Positive, negative and homo-polar sequence vectors during the fault conditions for the
different sags
However, for the phase and magnitude detection block, the outputs are the positive
sequence magnitude and phase, which correspond directly with the states θ’ and A’,
respectively.
42
3.3 TESTING SIGNALS AND EXPERIMENTAL SETUP

Following the representations in the discrete domain already deducted, the different
PLL algorithms have been implemented in a control board based on a floating-point
Texas Instruments TMS320F28335 DSP at 150 MHz (6.67-ns cycle time). Their
capability to perform a fast and accurate synchronization has been tested in the
laboratory under different grid fault scenarios, where the three-phase voltage waveforms
experience transients due to the appearance of voltage sags, frequency variations, and
harmonic pollution. These unbalanced and distorted input voltages were generated by
means of an ac programmable source and an auxiliary transformer. The layout of the
experimental workbench used in this paper is presented in Fig. 10.
Six representative faulty and distorted scenarios have been selected for evaluating the
three synchronization systems under test.
• Voltage sags: In Table I, the characteristics of four selected voltage sags have been
summarized. It is worth to mention
Fig. 11. Generation of grid voltage sags in the experimental setup. (a)
Generation of a Type “A” voltage sag. (b) Generation of a Type “B” voltage
sag. (c) Generation of a Type “C” voltage sag. (d) Generation of a Type “D” voltage
sag.
43
that these sags are the most characteristic ones that affect wind power systems.
In Table I, the magnitude and the phase of the symmetrical components of the voltage
during the fault period are indicated in each case, assuming that the prefault voltage
is always equal to V + = 100, V − = 0, and V 0 = 0.

As can be seen in the table, three of the proposed sags give rise to unbalanced
voltages, as explained in [37] and [38], and, hence, to positive- and negative-
sequence components. The presence of the negative sequence during the fault allows a
more rigorous analysis of the synchronization capability of the different algorithms
under test. Moreover, unbalanced faults constitute 95% of the voltage sags that affect
distributed generation systems.
In order to obtain the aforementioned dips, different faults have been emulated with
the programmable ac source at the primary winding of the transformer, as indicated in
Fig. 11. De- pending on the fault topology as well as on the connection of the transformer,
the desired voltage waveforms at the measurement point, indicated in Table I, are finally
obtained, acquired, and later processed by the DSP.
• Harmonic-polluted voltage (8% THD): According to the EN50160 standard [53],
the THD of the voltage waveforms at the output of a generation facility cannot be
higher than 8%. Considering this requirement, Table II shows the harmonic
composition used for evaluating the performance of the grid synchronization
systems under test when the grid voltages become distorted.
• Grid voltage frequency jumps: By means of the programmable source, a 10-Hz jump
(from 50 to 60 Hz) in the frequency value of the positive sequence has been applied to
analyze the response of the frequency adaptive structures under test.
In the following section, the responses of the DDSRF PLL, DSOGI PLL, and 3PhEPLL
under these transient conditions will be compared.
44
TABLE II
HARMONIC COMPOSITION FOR THE TEST
3.4 EXPERIMENTAL PERFORMANCE OF THE

PLLS UNDER TEST
Behavior in Case of Voltage Sags
1) Type “A” Sag Test: This kind of voltage sag appears as a consequence of
three-phase faults that give rise to high short circuit currents and, hence, to a
balanced voltage drop in the network. As Fig. 12(e) and (i) shows, the DDSRF PLL
and the DSOGI PLL produce a good response, as both systems achieve a very fast
detection (20 ms) of the positive-sequence components (less than two cycles). The
response of the 3phEPLL, depicted in Fig. 12(m), also shows a good response, but
with a larger transient in the positive-sequence estimation.
2) Type “B” Sag Test: This kind of fault permits analyzing the behavior of the
PLLs under test in the presence of zero- sequence components at the input. The
Clarke transformation used in DSOGI PLL and DDSRF PLL to extract the αβ
components enhances the response of this synchronization system when the faulty
grid voltage presents zero-sequence components. Their responses, as shown in Fig.
12(f) and (j), are fast and accurate. On the other hand, the 3phEPLL does not cancel
out the zero-sequence component from the input voltage, something which may
affect the dynamics of the positive-sequence estimation loop. However, this effect
45
is further attenuated by the computational unit, as Fig. 12(n)

shows; the steady-state response is also reached with no great delay, as detailed
in Fig. 12(n), showing the good behavior of this PLL under these conditions.
3) Type “C” and “D” Sag Tests: These kinds of sags appear due to phase-to-
ground and phase-to-phase short circuits at the primary winding of the transformer,
respectively, as shown in Table I. In a distribution network, these distortions are
4) common than the previous ones, as they are the typical grid faults caused by
lightning storms. As depicted in Fig. 12(g)–(p), all three PLLs permit detecting the
positive sequence between 20 and 30 ms; however, the 3phEPLL has a slower
stabilization, as shown in Fig. 12(o) and (p). This effect is a bit more noticeable with
the “C” sag, where the combination of the phase jump and the magnitude change of
two phases occurs, as shown in Fig. 12(o).
B. Frequency Changes (50–60 Hz)
In this experiment, similar results are obtained with the DDSRF and the DSOGI PLL, as
can be seen in Fig. 13(a)–(d). The low overshooting in the amplitude estimation in both
cases [see Fig. 13(a) and (c)] assists the good phase and frequency detection, as shown in
Fig. 13(b) and (d). Likewise, the response of the 3phEPLL shows a similar settling time,
as shown in Fig. 13(e); however, the initial oscillation in the
46
47
Fig. 12. Amplitude and phase estimation of the three tested PLLs in case of four types of
sag. (a)–(d) Input signal (V). (e)–(h) Amplitude (V) and phase (rad) detection for the
DSRF PLL. (i)–(l) Amplitude (V) and phase (rad) detection for the DSOGI PL. (m)–(o)
Amplitude (V) and phase (rad) detection for the 3phEPLL. Scaling factors: Amplitude =
1 : 150; phase = 1 : 7.
48
Fig. 13. Amplitude, phase, and frequency estimation of the three tested PLLs in a
frequency jump. (a) and (b) Amplitude (V), phase (rad), and frequency detection for the
49
DDSRF PLL. (c) and (d) Amplitude (V), phase (rad), and frequency detection for the
DSOGI PLL. (e) and (f) Amplitude (V), phase (rad), and frequency detection for the
3phEPLL. Scaling factors: Amplitude = 1 : 150, phase = 1 : 7, and frequency 1 : 70.
amplitude estimation of the voltage contributes to slightly delay the stabilization of the
frequency magnitude, as displayed in Fig. 13(f).
C. Polluted Grids (THD = 8%)
The 3phEPLL behaves as a band-pass filter for the input signal, something that
permits filtering the input without adding extra filters. As can be seen in Fig. 14(d), the
3phEPLL offers the best filtering capability among the PLLs under test, with a clear and
undistorted estimation of the magnitude and phase of the input.
The response of the DDSRF PLL, depicted in Fig. 14(b), which has a first-order filter at
the output, is even better than the one provided by the DSOGI PLL, due to the latter’s
low-pass filtering behavior. Although the DSOGI PLL also behaves as well as a band-
pass filter, the tuning of its parameters, which permits a faster stabilization of the
estimated signal in the previous tests, plays against its immunity in front of harmonics, as
shown in Fig. 14(c), giving rise to small oscillations in the positive-sequence estimation.
50
Fig. 14. Amplitude and phase estimation of the three tested PLLs in a polluted grid (THD
= 8%). (a) Input signal (V). (b) Amplitude (V) and phase detection (rad) for the DDSRF
PLL. (c) Amplitude (V) and phase detection (rad) for the
DSOGI PLL. (c) Amplitude (V) and phase detection (rad) for the 3phEPLL. Scaling
factors: Amplitude = 1 : 150; phase = 1 : 7.
51
TABLE III
NUMBER OF OPERATIONS PERFORMED BY EACH PLL
A=Addition M=Multiplication T=Trigonometric S=Variable storage D=Division. Type

and number of operations in each PLL. The shadowed cells indicate the synchronization
system that is used the least number of times by each operator.
3.5 EVALUATION OF THE COMPUTATIONAL BURDEN TIME

The computational cost in the floating-point TMS320F28335 DSP, which is
considered as a microcontroller by the brand itself, has been evaluated for each case.
However, an initial qualitative analysis can be done if each algorithm is divided into its
fundamental operations. The different types of basic operations, as well as how many
times they were used in each algorithm, are summarized in Table III, where the
shadowed cells indicate which PLL is used the least often by each operator.
The results from Table III seem to indicate that the DDSRF PLL and the DSOGI PLL
could be the fastest algorithms. On the other hand, the number
of trigonometrical functions that the 3phEPLL has to perform plays against its
computational cost. This statement can be subsequently confirmed with the experimental
burden time measured for each PLL when processing one cycle, as shown in Table IV.
Regarding the results of Table IV, the DDSRF PLL performs the fastest loop. In spite of
the high number of additions
52
TABLE IV
COMPUTATIONAL COST EVALUATION
Global burden time of one cycle of instructions for each PLL programmed in a
TMS320F28335 DSP.
and multiplications to be calculated, the DSOGI PLL holds second position in
this burden-time comparative, although the differences with respect to the DDSRF are
not quite significant. Finally, it can be observed that the greatest burden time is obtained
with the 3phEPLL.
53
CHAPTER-4
SIMULATION BLOCK DIGRAMSAND RESULTS
BLOK DIAGRAM OF SINGLE SAG
54
FIG : MAGNITUDE WITH DSOGI PLL
FIG: MAGNITUDE WITH E3PHLL
55
FIG:MAGNITUDE WITH MODIFYDE E3PHLL
FIG:PHASE ANGLE WITH MODIFIDE E3PHLL
56
FIG: PHASE ANGLE WITH DSOGI
FIG :PHASE ANGLE WITHE3PHLL
57
FIG:FREQUENCY WITH MODIFYDE E3PHLL
FIG:FREQUENCY WITH DSOGI
58
FIG:FREQENCY WITH E3PHLL
FIG:IN PUT VOLTAGE
59
BLOCK DIGRAM OF TWO PHASE SAG
60
61
62
63
64
FIG:IN PUT VOLTAGE
65
BLOCK DIAGRAM OF THREE PHASE

SAG
66
67
68
69
70
FIG:IN PUT VOLTAGE
71
CHAPTER-5
5. CONCLUSION
In the process of synchronization of DG generated power with the utility, phase
tracking is very essential for proper grid synchronization. A PLL can be used to
obtain magnitude, frequency and phase information for estimation of
fundamental positive-sequence component of grid voltage. Accurate and fast
estimation of these quantities can be used for control and protection of the
system. Overall the grid synchronization system based on positive-sequence
estimation is able to handle non- ideal conditions well. The positive-sequence
phase angle is tracked within acceptable margins and therefore the PLL system as
given with the positive sequence estimation could indeed operate in a real life
application.
APPENDIX
The parameters used for tuning the different advanced synchronization systems
analyzed in this paper are summarized in Table V.
72
CHAPTER-6
BIBLIOGRAPHY
[1] F. Blaabjerg, R. Teodorescu, M. Liserre, and A. V. Timbus,

“Overview of control and grid synchronization for distributed power
generation systems,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp.
1398–1409,Oct. 2006.
Current isq -32768<isq<32767 SIN(angle) in the same format than in
Park return Q15.
[2] J. Svensson, “Synchronisation methods for grid- connected voltage

source converters,” Proc. Inst. Elect. Eng., vol. 148, no. 3, pp. 229–
235,May 2001.
[3] M. Karimi-Ghartemani and M. Iravani, “A method for

synchronization of power electronic converters in polluted and
variable-frequency environments,” IEEE Trans. Power Syst., vol. 19,
no. 3, pp. 1263–1270, Aug. 2004.
[4] F. M. Gardner, Phase Lock Techniques. New York: Wiley, 1979.
[5] Francisco D. Freijedo, Jesus Doval-Gandoy, Oscar Lopez, Carlos

Martinez-Penalver, Alejandro G. Yepes, Pablo Fernandez-Comesana,
Andres Nogueiras, JanoMalvar, Nogueiras, Jorge Marcos and Alfonso
Lago, “Grid-Synchronization Methods for Power Converters,” Proc. of
IEEE 35th Annual Conference on Industrial
[6] FANG Xiong, WANG Yue, LI Ming, WANG Ke and LEI Wanjun,
“A Novel PLL for Grid Synchronization of Power Electronic
Converters in Unbalanced and Variable-Frequency Environment,”
Proc. of IEEE International Symposium on Power Electronics for
Distributed Generation Systems: pp. 466-471, 2010.
[7] C. Lascu, L. Asiminoaei, I. Boldea, and F. Blaabjerg, “High

performance current controller for selective harmonic compensation in
active power filters,” IEEE Trans. Power Electron., vol. 22, no. 5, pp.
1826–1835,Sep.2007.
73
[8] M. Routimo, M. Salo, and H. Tuusa, “Comparison of voltage-source

and current-source shunt active power filters,” IEEE Trans. Power
Electron.,vol. 22, no. 2, pp. 636–643, Mar. 2007.
[9] J. M. Guerrero, L. Hang, and J. Uceda, “Control of distributed

uninterruptible power supply systems,” IEEE Trans. Ind. Electron.,
vol. 55, no. 8, pp. 2845– 2859, Aug. 2008.
[10] A. I. Maswood and F. Liu, “A unity-power- factor converter using

the synchronous-reference- frame-based hysteresis current control,”
IEEE Trans. Ind. Appl., vol. 43, no. 2, pp. 593–599, Mar./Apr. 2007.
[11] B.Wang, G. Venkataramanan, and A. Bendre, “Unity power factor

control for three-phase three- level rectifiers without current sensors,”
IEEE Trans. Ind. Appl., vol. 43, no. 5, pp. 1341–1348, Sep
74

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LATTICE SYNCHRONIZATION TECHNIQUE FOR THREE WIRE

SYSTEMS TO BE SPECIFIC DOUBLE SOGI

The increased penetration of these technologies in the electrical network has

Solutions based on the development of auxiliary systems, such as STATCOMs

1.3 PLL Definition

BasicPLL Block Diagram

1.4 PLL Component

Individual Blocks in PLL Diagram

A five Stage Ring Oscillator

1.4.2 Frequency Divider

Operation of a PFD: (a) fref=fCK, φref#φCk and (b) fref>

f1.4.4 Charge pump and loop filter

he subsequent oscillator circuit. Since the VCO introduces another integrator,

1.5 Noise and Power Considerations

1.6 Band Width of PLL

1.7 Phase Noise and Its Causes

Causes of Phase noise

In an analogue mixer a number of different frequencies are generated within the

2.1.1 Edge Triggered D-Flip-flop

2.1.2 Differential Amplifier

Where Ad is the differential-mode gain and Ac is the common-mode gai

The common-mode rejection ratio is usually defined as the ratio between

In the above equation, as Ac approaches zero, CMRR approaches infinity.

Some kinds of differential amplifier usually include several simpler

Differential amplifiers are found in many systems that utilize negative

. implementing a differential amplifier is the long-tailed pair, which is also usually

Current source load Differential amplifier

2.1.3 Current Starved Inverter

2.1.4 Current starved VCO

The current-starved VCO, schematically represented in Fig. 1, includes two

Both the NMOS and PMOS are designed for

IDCentre =N* *Vdd*Fcentre

Where N=total Number of inverters in series

P1 and P2 and are same β as N1 and N2

2.2 Limited Range Problem Of conventional VCO

Ring type oscillator

2.3 Negative feedback architecture

Block Diagram of proposed architecture

2.4 Two input voltage to current converter

2.5 Delay cell design

A High Swing Low Power CMOS Differential Voltage

High Swing Low Power CMOS Differential

Differential Amplifier Circuit with Positive Feedbac.

Fig. 1. E-on voltage support requirement in the event of grid fault.

Fig. 2. REE voltage support requirement in the event of grid fault.

3.1 DESCRIPTION OF THE THREE SYNCHRO

Many of the positive-sequence detection algorithms are based on SRF PLLs .

Fig. 3.DDSRF-PLL block diagram

Fig. 4. DSOGI-PLL block diagram.

as explained in . The diagram of the DSOGI PLL is shown in Fig. 4. As it can be

A conventional SRF PLL is applied on the estimated positive-sequence voltage vector,

Fig. 5. 3phEPLL block diagram.

Fig. 6. Phase and magnitude estimation loop of the DDSRF PLL.

the discretization approach made to their continuous equations . This implementation

1.Positive- and Negative-Sequence Decoupling Networks: The decoupling

2.Phase and Magnitude Estimator Discretization: In the DDSRF PLL, the

3) LPF Block Discretization: The amplitudes of the dq positive- and negative-

Fig. 7. Quadrature signal generator based on a second order generalized integrator

The discretization of this system has been performed using trapezoidal

Fig. 8. State variables of the SRF-PLL block.

where Ts is the sampling time.

1) QSG Block—EPLL Discretization: The block diagram of the EPLL

Fig. 9. Quadrature signal generator based on an EPLL structure.

3.3 TESTING SIGNALS AND EXPERIMENTAL SETUP

IDCentre =N* VddFcentre