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22 32-bit EISA Architecture - Evolution

The intmduction of the i3B6 and i486 32-bit micropmcessors with hrll 32-bit data bus and 32-
bit address bus also required an extension of the ISA bus. This bus was implemented for the
80286, with its l&bit address bus and 16 Mbyte address space ““ly. Not only is the small width
of the bus system outdated today, but so are the antiquated B-bit 8237A DMA chips, with their
limitation to 64 kbyte blocks, and the rather user-unfriendly adapter contiguration (“sing
@npea and DIP switches). Another serious contradiction between the very powerful 32-bit
3 processa and the &ired~ B-bit AT concept is the lack of supporting busmasters “n external
adapter cards.

I, Two completely different solutions for these pr”blems are established today: IBM’s micmchannel
;: for FSl2, and EISA, which has been developed by a group of leading manufachws of IBM-
compatible KS. IBM has gone dorm a completely different mad with its microchannel, not
:( only because of the new geometric layout of the’ bus slots, but also with the architedure
,! implemented. Moreover, IBM has denied the micrcchann_e~ to other manufacbuers by means
of patents and other protective rights. This is a consequence of the fact that these other clone
’ manufacturers had previously got a large part of the PC market. As IBM is rather miserly with
issuing licences, the microchannel is no longer the completely “pen architedure that users and
” man”Lwt”ren have been accustomed to with the PC/XT/AT. Together with the sigCficantly
’ larger timctionality of the micmchanne1, “ne may speak of a radical rmrganization or indeed I

view of the microchannel as a rwolutionaly step towards real 32-bit systhms.

e :
n ,. EEA, on the other hand, tries to take a m”te that might b-e called uevol”ti”nary~. The maxim .

of EJSA is the possibility of integrating ISA components into the EISA system without any . i

1. pmblems. This requires an identical geometry for the adapter cards and, therefore, unforhm-
s ately also the integration of obsolete concepts’ for the ElSA’s ISA part. With this concept, X-bit
? ISA components can be integrated in an EISA system with no problems, but you don’t then have
1s 9 my advantage. Under these conditions the EISA bus operates m”re or less identically t” the
:s 1 cmwentlonal ISA bus. only 16. and 32-bit EISA components really take advantage of the EISA
,e ‘. bus system, “sing, for example, burst cycles or 32-bit Dh& The EISA bus is capable of a data
&transfer rate of up to 33 hQytes/s. compared to 8.33 Mbytes/s with an ISA bus.
le In view of the t&Cal sbudure, EISA is m”re complicated than the miawhannel because it
A :’Mt only needs to cxry out EISA bus cycles, but for compatibility reasons also ISA cycles. This
h ; Applies, for example, to DMA. where the EISA..system must decide whether an B237A-
‘.:.-mpatible DMA cycle (with its known disadvantages) or a full 32-bit EISA DMA cycle has to I
,e $+ executed. The hardware must be able to carry-out both, and t%“s is, of course, rather I

iv .: @Jmplicated. In this aspect, the microchannel has an easier life; it frees itself from the outdated
al ‘. ~/XT/AT concepts, and starts from a new beginning. This restriction t” a new beginning
,A 6-s the microchannel less complicated. However, stronger competition in the field of EISA
‘1 ha &ly led to cheaper EISA chips, even though their technology is m”re complex. Additionally,
“_a the user you have the advantage that older ISA components may also be used initially. Later
i,y” can integrate more powerful EISA peripherals. In view of the speedy development, though,
&.?h” is going t” “se his old hard disk controller or S-bit graphin adapter $h 128 kbytes of
.$?“Uy when buying a computer of the latest generation?

550 Chapter 22

Therefore, the more straightforward concept is surely the micmchannel, which frees itself from
the old traditions; but because of IBM’s restrictive policy, it has been almost exclusively dedi-
cated to IBM products up to now. On a BIOS, operating system or application level you don’t
notice whether you are working with an EISA or micmchannel PC. Only system programmers
and bit freaks have to deal with their differences.

22.1 EISA Bus Structure

The name EISA, as an abbreviation for e.rfended ISA, already indicate the evolutionary con-
cept of this 32-bit extension for the AT bus. ISA components may be wed in an EISA - system
with no alterations. Purr EISA adapters inform the EISA system (by means of the EX32 and
Ex16 signals) that they are EISA components with the extended functions which are pmvided
for EISA. Internally, LlSA machines differ drastically from their ISA predecessors in many
aspects, discussed in the following sections. Figure 22.1 show a schematic block diagram of the
EISA archit&“re.

The clock generator supplie both the CPU and, after division of the frequency in the frequency
divider, the EISA bus with a clock signal. Thus the EISA bus isa synchronous bus system,
32.bit EISA Architecture - Evolution 551

because the CPU and EISA bus are supplied by the fame clock signal source, and are thus
Nnning synchronously. The maximum frequency of the EISA bus is 8.33 MHz. This clock rate
determines the X~~SS Of the CPU to all external units. On the other hand, the i386/i486/
Pendum may access the main memory at the full clock frequency (with possible wait state+ The
EISA bus buffer provides for a controlled data transfer between the local bus and the EISA bus.
The heart of an EISA bus is the EISA bus contmller. It distinguish- behyeen EISA and ISA bus
cycle% supplies all the required ISA and EISA bus signals, executes normal and burst cycles, and
Car&s Out the entire bus control operation in the EISA PC. Together with the data swapper, it
divide+ 32.bit quantities into t3- or I&bit portions for 8. and &bit peripherals, or recombines
such Portions into a 3%bit quantity. That is necessary, for example, if you insert a I&bit ISA
adapter into an EISA slot. The EISA maxim of compatibility then requirrs that the EISA logic
accesses the ISA adapter without any problem
EISA adapter cards with their own busmaster have a busmaster interface which enable a local
CPU (the busmaster) to control the EISA bus. Thus, EISA is illl important step towards a multi-
‘. P-so* wimnment. Moreover, the arbitration logic ?zd the altered assignment of DMA and
intermpt channels already supports multitasking operating systems on a hardware level. It
would be a pity to waste an i486 or Pentium on DOS alone. Presently, there is an EISA chip set
from Intel on the market that integrates the interrupt controller, DMA controller, bus arbitrator,
timer and the NM1 logic ion a single chip: the 82357 1%’ (integated system peripheal). The bus
controller is available as the 82358 EBC (EISA bus controller). The EIZA bus can carry Out
various bus cycles:
- standard bus cycle,
- burst cycle,
- bus cycle with BCLK stretching, and
., - enhanced master burst cycles EMB-66 &,d EMB133.
The standard bus cycle is a nomal i386 bus cycle, at least as far as the course of the participating
1 dbess, data and control signals are concerned. As the EISA bus is running with a bus clock
of at most 8.33 MHz, even with slow-clocked i386 Cl?Us&lot of CPU wait cycles are naary.
2 The standard bus cycle requires two BCLK cycles for hansfeting at most one quantity of 32 bits.
‘; The burst cycle is the s&e as the i486 burst cycle, but here the bus clock BCLK instead of the
; pmcffsor clock PCLK is decisive. A real novelty is the bus cycle with BCLK stretching. The
EEA bus controller is able to stretch one half cycle of BCLK to service slower devices at &t,
’ ad to restore synchronization with the CPU cltiagain. Figure 22.2 illustrates this: the CPU
’ frequency is 25 MHz, and the bus frequency BCLK is generated by dividing by 3, so it is there-
’ fo, 8.33MHz. A h il If cycle,of BCLK is stretclied under two &&stances:
’ synchronization of the rising BCLK edge with the falling edge of CMD if the busmaster on
tk motherboard addresses an EISA or ISA slave;
” ._ -
>$chronization%f the rising BCLK edge with the falling edge of CMD if an ISA master
ii addresses an EISA slave.
ti BY stretching BCLK, an EISA or ISA slave can be better integrated into an EISA system, as with
” the AT. The number of clock cycles for slower periphemls is reduced, and the system through-
2~ ‘Wt is enhanced.
552 Chapter 22

The advance of VLB and PC1 is also reflected by the EISA spxificationl The EISA interest group
has recently defined a new enhanced master bunt cycle which should mcrease the transfer rate
up to 66 Mbytes,s (E&B-66) or even 133 Mbytes/s -133). To achieve that, a data transfer
is no longer only triggered by the ascending BCLK edge. Additionally, both the ascending and
the descending ECLK edges can issue a data transfer. Thus, the transfer rate is doubled, while
the bus frequency remains unchanged’at a maximum of 8.33 MHz for compatibility reasons.
Together with a data bus width of 3’2 bits, this leads to a transfer rate of 66 Mbytes/s. To reach
the mentioned 133 Mbytes/s, additionally the 3%bit address part of the EISA bus is used for the
data transfer, as this part is unused during the data transfer phase in burst mode. Therefore, the
data bus width increases to 64 bits.

22.2 Bus Arbitration

A significant advance compared to the ISAbais is bus arbifrafia. This means that an external
microprwewn on an EISA adapter card can also completely control the bus, and may therefore
access the system’s main memory, the hard dhk and all other;ystem components on its own,
without the need of support by the CPU. This is necessary for a powerful multiprocessor
eperation if, for example, the 82596 LAN controller wants to access main memory and the hard
. disk, Such ext&ninal ElSA busmnsters can request control of the bus by the EISA MREQ (master
.&quest) signal from the host CPU on the motherboard. The host CPU is the standard busmaster
in this case.
The release of the bus control to an external busmaster on an adapter card was also posslb’e
with the AT, but in the AT this take place via a DMA channel, ati anpowerful arbitration for
several external busmasters is impossible in practice. The PC/XT and AT were only conceived
32.bat EISA Architecture - Evolution 553

of as single processor machines. Arbitration in the AT can only be a last resort, therefore. An
efficient and fair arbitration model is not implemented.
On the other hand, for releasing the EISA bus to various busmasters EISA uses an arbitration
model with thaw levels: DMA/refresh (highest level); CPU/master; other masters (lowest Iwel).
On each level several masters may be present. Within the level concerned the bus is switched .
in a rotating order. Refreshing the memory has the highest priority, because a lock of the refresh
by another master would lead to a data loss in DRAM, and therefore to a crash of the whole ’
system. If the refresh control requesb the bus via an arbitration, it always gets control after a
short reaction time period. All other busmasters have to wait until the current refresh cycle is ’
EISA busmasters don’t have to worry about refreshing the main memory on the motherboard.
This is carried cut by a dedicated refresh Itic. On the other hand, in the AT the pseudo-ISA
busmasters on an ISA adapter must also control the memory refresh if they are in mntml of the
With the EISA busmaster status register, EISA implem& the possibility of detemdning the last
active busmaster. This is important, for example, for an NM1 handler which, .dfter a time-out
error for the EISA bus, must evaluate which busmaster has operated ermneously~ Figure 22.3 :
shows the structure of this register. Note that a zero value indicates the slot with the last active
P busmaster.
,e I
The DMA system has also been improved significantly compared to the AT bus. Not only is the .
ial complete 3%bit address space available for curry QMA transfer (the AT bus allows only 64 or
mre 128 kbyte blocks), but three new DMA operatio~modes with improved data throughput have
‘“, also been implemented: DMA types A, B and C. T&e previous made is now called the cmptible .
or male. In this mode, the addresses are generated at the same clock cycles with an identical clock *
rd length, as on the ISA bus (that is, as was the case with the 8237Al.
ter &.?ww EISA DMA operating type A, on the other hand, shortens the memory phase of the
DMA transfer, but the I/O phase remains equal. Thus, one DMA cycle is carried out within six -
BCLK cycles, and the maximum data throughput reaches 5.54 Mbytes/s. Most ISA devices can ’
3k be operated on an EISA system with type A without causing a malfunction. With the DMA type
ior B, the I/O cycle also needs less time so that only four BCLK cycles are_necessary for one DMA
ed transfer. The data throughput is 8.33 Mbytes/s at the most. Type B is sup&ted by only a few
554 Chapter 22

ISA device. Finally, only EISA devices that support burst cycles are able to follow burst type
C. Here, one DMA transfer is execufed within a single BCLK cycle. With DMA burst type C.
DMA transfer rates of up to 33 Mbytes/s can be achieved if the full 3%bit width of the EISA
data bus is used. This is the maximum transfer rate for the EISA bus. EISA DMA modes A to
C support an 8, l6- and 3%bit data transfer. The transfer of data read or data write from/to
hard disks by means of DMA is again becoming interesting with EISA.
To address the 32.bit address space two page registers are available with EISA: the low- and
high-page registers. Their addresses are listed in Table 22.1. The low-page register is completely
compatible with the conventional DMA page register, known from the AT. The high-page
register supplies the high-order address byte A3-A24, and often serves to distinguish ISA and
ElSA DMA cycles: if the high-page register is not initialized in advance of a DMA transfer, an
ISA DMA cycle has to be executed which is compatibl; with the 8237A chip. Once the high-page
register has also been initialized, the DMA control is really operating in EISA mode and the
complete 32-bit address space is available. The EISA DMA chip increases or decreases the whole
32.bit address. Therefore (theoretically), a complete 4 Ghyte block can be transferred. In 8237A-
compatible mode, on the other hand, only the current.address register with a width of 16 bits
is altered, so that only a 64 or I28 kbyte block can be moved.

Cha”“el Low-page register High-page mglster

0 87h 487h
i 1 83h 483h
2 81h 481h
3 8Zh 482h
4 8fh 48fh
5 8bh 48bh
6 89h 48th
7 8ah 48ah

With EISA the service of the DMA channels is no longer carried out according to a scheme with
fixed priorities, but +tributed over three levels. Within each level the channels are allocated
according to a rotating scheme. This avoids the case where one peripheral with a high DMA
priority locks out other devices with lower prtorities by frequent DMA requests. This might be
possible, for example, if a task services a communications port where external requests we
arriving continuously, but another task with a=l6wer DMA priority accesses the hard disk. The
frequent requests lock out the task which attempts to read data from the hard disk. Thus the
more elaborate DMA hierarchy (as compared tothe An supports multitasking operating systems
where several tasks are competing for the DMA channels-more or 1-s a protection of minoriti~
in the PC. Also, the microchannel follows a similar stmtegy.
. &A implements seven DMA channels in total, which may be programmed to serve 8-, 16. Or
32-bit devices. The control of channels O-7 for in ISA-compatible or real ElSA transfer is canid
out with the two extended mode mgtsters. They are write-only, and are located at I/O addresses
40bh (channels O-3) and 4d6h (channels 4-n. respectively. Figure 22.4 shows the stmctum Of
these registers. -_ .+
32.bit EISA Architecture - Evolut@on 555

Through the STP bit you activate the ElSA extension for a DMA buffer structure bi the main
2 -0ty horn where data is sequentially read or stored. Usually this feature is not used, and
STP equals 0. The EOP bit determines the dire&on of the EOP signal for the seleaed channel.
In the PC/XT/AT, EOP was configured as output. EISA additionally dlows EOP from an
external device (for example, a communication interface). The TIM entry defines the transfer
mode, WLlrh the access width of the DMA channel, and the munting mode. A value of Oob
curresponds to the Bbit DMA channels of the PC/XT/AT, and a value of Olb to the l&bit AT
,,, drannels. Thus, for Width = Olb the output address is shifted by one bit to address I&bit words.
The address generated internally in the word count register ia incremented only by 1 upon each
transfer. Thmugh the shifted address, however, this means an incwmentation by 2. On the other
hand, for Width = lob, the word count register is incremented by 2 upon every transfer. Finally,
,! the DMA cuntmller increments the address by 4 when 32-bit l/O with byte cmmt is selected.
_ The two Channel bits determine for which of the eight chnels O-7 the other entries are valid.

/: 22.4 Interrupt Subsystem

As is the case with ISA, EISA also implements 15tiierrupt levels which are managed by the
: EISA interrupt controller. Table 22.2 lists the typical assignment of these IRQ channels.
’ For compatibility reasons, IR@ is occupied by cascading. The EISA interrupt controller behaves
in the same way as the two cascaded 8259A PlCs in the AT. Thus you have to output a double
’ EOI @‘master and slpve for the IRQMRQIS channels to terminate a hardware interrupt. Unlike
; the AT, the interrupt channels assigned to EISA adapters may also operate with level instead
5 of ed& triggering. ?he level of an IRQ line above a-certain threshold level issues an interrupt
y @quest in this case, and not the rise itself. It is therefore possible for several scwces to share
3, an IRQ. If one source is serviced the corresponding IRQ remains active and shows that a further
g device on the same IRQ line quests an interrupt. This means that in prb&le any number of
556 Chapter 22

devices may request an interrupt. Unlike the K/XT and the AT, a line is no longer reserved
for a single device. In the case of the three serial interfaces COMI, CQMZ, COM3, for example,
previously only COMI and COMZ could issue an interrupt via IRQ4 and IRQ3, while COM3
could only be operated with polling.
The PIC 8259A in the K/XT and AT can also operate with level triggering. Upon initialization.
however, you must decide whether all interrupts should be detected by level or edge triggering.
An individual choice is not possible there; EISA permits this by means of the control register
for level/edge triggering (Figure 22.5).

. &trim for IRQHRQZ, IRQg and IRQ13 are missing because they refer to devices integrated 0”
the motherboard (see Table 22.2). Note that qnly interrupts that service an ElSA device may
operate with level triggering. If you usi an ISA adapter, the interrupt assigned to it must be
programmed as edge triggered for compatibility reasons.
To complete the picture, I should mention that you can issue an N-MI-via software by writing
an arbitrary value to the R-bit port 462h. Do not confuse that with the NT U2b instruction which
32.bit EISA Architecture - Evolution 557

also leads to an interrupt 02h. Writing to the port 462h supplies the prcessor with an active
NM1 signal externally and, thus, simulates a hardwareissued non-ma&able interrupt.

22.5 EISA Timer and Failsafe Timer

The EISA timer comprises six channels in total, and is equivalent to and register-compatible
with two 8254 chips. The first three channels O-2 are reserved for the internal system clock, the
memory refresh, and tone generation for the speaker, as was the case with the AT. One of the
remaining three timers is used as a failsafe or watchdog timer. Generally, this is timer 3, that
is, counter 0 of the second 82% It issues an NM1 if a certain time period has elapsed. This
prevents an external busmaster from keeping control of die bus too long and blocking necessary
intermpts or memory refresh. If an external busmaster keeps control of the EISA bus too long,
in contradiction to the bus arbitration rules, this indicates a hardware malfunction or the crash
of the external busmaster. The failsafe timer then issues an NMI, and the arbitration logic
returns control to the CPU so that it may service the N$4I. YOU may accew the first timer via
the I/O addresses 4Oh to 43h, and the second timer through 48h to 4bh.

i 22.6 l/O Address Space

3 With EISA, the support and controller chips are also accessed via pats. Table 22.3 lists the new
I/O address areas for EISA. Unlike ISA, the individual EISA slots, and therefore also the in-
serted EISA adapters, can be addressed individually. Internal registers on the EISA adapters
therefore have different base addresses lOCC8000h. This is important so that EISA adapters can
5 be automatically configured without DIP switches. The high-order byte of the I/O address is
decoded by the I/O addrms logic of the motherboard, which uses it to drive the expansion slot

110 a d d r e s s Meaning
,, WOOh OOffh ISA motherboard
OlOOh .,. 03ffh ISA e&&n adapter
MOOh Odffh resewed for contmlle,~ on the E&A motherboard
0800h OBffh resewed for E&A motherboard
OcOOh Odfh rererw! for ElSA motherboard
1OWh tfffh expansmn Ilot 1 ..i .
: 2WOh 2f‘fh expanrlon Slot 2
3000h Ifffh expanrion slot 3
: 4000h 4fllh expansion‘slot 4
) 5000h Sfffh expanrion slot 5
” 6000h 6fffh expanrion slot 6
7OQOC. 7fffh expanrion slot 7
Y ‘: 800011 8,ffh expansion slot 8

concerned. The address decoder on the expansion adapters then only decode% the low-order
address bytes further. Thus, an ISA adapter which knows only a IO-bit I/O address can also be
inserted into an EISA slot without any problems.


With EISA adapter cards the IRQ used, as well as the DMA channels, are programmable. The
configuration information is stored in the extended CMOS RAM. EISA specifically extends the
CMOS RAM by 4 kbytes for this purpose. Special installation programs provide support when
configuring the EISA adapters, and automatically @te data into die extended EISA CMOS
RAM. Typical information is which I/O ports are used by the adapter. which IRQ and DMA
channels are assigned to the adapter, etc. This EISA system information can be retrieved by
means of several ftmctions of NT 15h. Theywe listed in the following.

- INT 15h, Fumtion dsh, Subfunction AL = 0~3, --Access to EISA System Information, Read
Slot Info

This function returns infomntion pertaining to the adapter in a certain slot.

Regkter call “abe Return value

AH d8h error cede”

AL OOtvWh” vendor by+
8H utility revision (high)
8L utility reviskm bv4
. check sum canf4guration file 84SB)
CL slot (o-63) check sum configuration file kS8)
DH number of device functions
DL function information
SIDI comprersed vendor ID -
C=? error if <> 0

, .
. - INT 154 Function 684 Subfunction AL = Olh - Access to EISA System Information, Read
Function Info

This function returns 320 information bytes in an info table pertaining to the indicated function
in a certain slot. The calling program must provide a sufficiently Jargg buffer for the info table.
560 Chapter 22

- INT 1E.h. Function dsh, Subfunction AL = 03h - Access to EISA System Information, Write
COtigU%tiOll <.
This function writes configuration value from a table of the calling program into the CMOS
RAM. Additionally, a new checksum is calculated and written to the appropiiate location,
although you must also specify a correct value. The function must be called successively for
every slot present in the system, even if no adapter is installed (the passed values must be Set
to 0).

call value Ftetllm “abe

d8h error code”
03h I
byte length of table
offset of table”
segment of table”
error if 0 0
32.bit EISA Architecture - Evolution 561

Errw code Meaning

OOh no error
80h invalid dot number
81h invalfd function number
82h extended CMOS RAM damaged
83h slot doesn’t contain any adapter

22.8 EISA Adapters and Automatic Configuration

Cm EISA adapten you will look in vain for DIP switches$vhich sometimes made configuring
ISA adapten appear like gambling. with an unpredictable result. EISA solves the configuration
pmblem much more efficiently: every EISA adapter comes with a floppy disk holding a coqigu-
mfkm file (CFG). The CFG stars the system elements of the EISA PC used, such as, for example,
the assigned IRQ and DMA channels. This information is used by a configuration utility which
is delivered together with each EISA PC to configure b&b the adapter and ‘PC correctly. Addi-
tionally, the utility is intelligent enough to detect access confliciz and to react appropriately.
Examples of this are address conflicts between two adapters whose address areas overlap, at
least partially. This may occur with interfaces whose register addresses are equal, or with ident-
ical ROM base addresses of the SCSI host qd VGA graphics adapters. Such address conflicts
are the main reason why an AT refuses to run after installing and configuring the brand-new
VGA adapter.
The CFG file was part of the EISA concept from the start. All the firms involved in EISA agreed
to a standard for the tile format, so incompatibilities do n&wise here. The name of every CFG
file must obey the folIawi:g rule: !hhhpppp.CFG; where hhh is an abbreviation for the manu-
facturer, and pppp is a product identification. The CFG files themselves are pure ASCII files,
and use a language with strictly defined commands that recall the CONFIGSYS of MS-DOS.
Examples of CFG commands are: NAME = 11.7, SLOT= ???, BUSMASTER = wlue?, COMMENTS
=fut. Manufacturen can determine all the impartexit parameters for their EISA adapters by
using the CFG commands, so that the configuration utility need qly read the CFG file to
eonfigure the EISA PC correctly with details of the “ewly installed a&pter. The user does not
need detailed knowledge of occupied addresses, DMA channels, etc. and the typical cow-at-a-
fivPbqre&gate feeling of untrained users can thus be avoided. The configuration data is stored
fn the qttended CMOS RAM, and the EISA PC boots without additional configuration next time.
+ lfthe &nfiguration data in the CMOS RAM gets lost, for example, through a battery power-
e break, then you need simply start the configuration utility and reamfigure the system again
k.using the CFG files for all installed adapters.
ihides the CFG files, EISA has another concept for supporting config&atkm, the so-called
dh Wfayjif~ KWL). They supplement the configuration language on the level of the configuration
$,Utility, and contain instructions in a format that looks like a mixture of C and Assembler. By
562 Chapter 22

means of the OVL files, a very exotic EISA adapter can be integrated into an EISA system
automatically. The OVL files are in about the sane relationship to the configuration utility as
a ROM extension is to the system ROM of the motherboard, and they extend the CFG language
by new commands. An OVL file is integrated into a CFG file by means of an INCLUDE com-
mand, for example, INCLUDE = asuper_ad.ovln.

22.9 EISA Slot

For extension of the ISA bus up to 32 bits, EISA additionally implements 90 new contacts.
Presently, only 16 of them are used for data lines, u for address lines, and I6 for control and
status lines. In addition to the 98 ISA contacts already present, these 90 new contacts would lead
to a huge EISA contact strip on the motherboard (probably bigger than the motherboard itself).
The microchannel solves this problem by miniaturizing the contacts and the distance between
them, thus making the microchannel plug-incompatible. But EISA was launched to enable an
integration of the previous ISA components withotiany problem. This, of course, means that
the geometry of the EISA slots is harmonized with the existing ISA adapters. The members of
f the EISA group negotiated these obstacles elegantly by implementing a second layer of contacts
in the EISA plug which is shifted against the previous ISA contacts so that only EISA adapters
can reach them. ISA adapter cards do not shcrkircuit the contacts because an ISA adapter
cannot penetrate deep enough into the EISA slot. Thus an EISA sl@ is quite compact for the
enormous number of contacts and, morecwer, completely compatible with the ISA adapter cards
wihicb have only one contact layer. Figure 22.6 schematically shows the structure of an EISA
slat and the assignment of the corresponding contacts.
The signals listed cm the outer sides of the figure are the new EISA signals which are supplied
or accepted by the lower-lying contacts. By means of the shifted arrangement of the EISA
contacts, 38 instead of 36 new contacts have been added to the previous ISA extension. Thus the
EISA slot comprises I88 contacts. The encoding barriers in the slots prevent an EISA adapter
card from being inserted wrongly, or an EISA card from penetrating too deep into the slot and
shorkircuiting the USA contacts.
Four of these contacb are available to each manufacturer for their own purposes. Using these.
a manufacturer can develop a spedally adapted adapter card for applications that need signals
that go beyond the EISA specification. Such adapters are, of course, no longer completely EISA
compatible. On the other hand, though, the ~manufacturer is not restricted too much in his
freedom to develop certain adapters.

.,22.10 El:A Signals

. _
-’ In the following sections the new EISA contacts are discussed, as well as the meaning of the
supplied or delivered signals. The ISA part’s assignment of an EISA slot can be found in Section
21.3. The ISA contacts CLK and ALE are indicated by BCLK and BALE here, as is usual for
EISA. Because EISA supports busmasters cm external adapters without any restriction, all Con-
nections are bidirectional. To show the data and signal flow more prekely, I have assumed for
32-bit EISA Architecture - Evolution
564 Chapter 22

the transfer dir&ions indicated that the CPU (or another device on the motherboard) represents
the current busmaster.


Terminal BZS
The address latch enable signal BALE is generated by the bus controller and indicates that valid
address signals are present on the l/O channel. The adapters can then de&e the address.


Terminal BZO
BCLK b the bus clock signal for the EISA bus, and is generated by dividing the CPU frequency so
that BCLK has a frequency of 8.33 MHz at most.,$CL.K determines the data transfer rate. In bunt
mode or EISA DMA mode C, the transfer rate reaches up to 33.3 Mbytes/s (8.33 MHz. 32 bits).
- - c.
Terminals E17, FI5, F17-FI8
These four byte enable signals indicate on which byte of the 32-bit data bus data is transferred
Therefore, they correspond to the AO and AI address bits. The signals come directly from the
CPU. m refers to the least-significant byte D&D7 of the data bus, m to the most-significant
byte D24-D31.

Terminal El
This command signal serves for clock harmonization within an EISA bus cycle by stretching a
bus clock cycle BCLK appropriately. ??% is generated by the EISA bus control for all EISA bus

Bridges E6, E16, E25: F6, F16, F7.5, G6, GI5, H6, H16
The coding bridges prevent an ISA adapter penetrating tw deep into an EISA slot and, thus,
short-circuiting or damaging the lower EISA,,Ftacts.
D16-D31 :.
Terminals G7-GIO, GI’P-GI4, G17-GIS, Hi-&, HlO-HI2, H14, HI6
T&se 16 bits form the high-order word of the 3%bit EISA data bus. The 16 low-order bits are
’ Kansferred via-the ISA bus section.
Terminal E7
An EISA slave activates the EXI6 signal if it can run with a lbbit data bus only (that is. is pn
EISA Ibbbit device). The EISA bus controller then accesses the device via D&D15 with a width
of 16 bits. The EISA bus controller also divides all 3%bit quantities from the CPU intO 16-bl’
32.bit EISA Architecture - Evolution 565

pmtions, and combines &bit portions from the EISA slave into a 32.bit quantity for the CPLJ,
Terminal E4
An EISA slave activates the EX32 signal if it can run with a 32-bit data bus (that is, is an EISA \’
32-bit device). The EISA bus controller then acces~g the device via EM-D31 with a width of
32 bits.

An active EISA ready signal EXRDY indicates that the addressed EISA device may complete the
current bus cycle. EXRDY serves to insert wait states into an EISA bus cycle.

L4!-LA14 LA24-LA31 **
Terminals EIS, EZO-E23, E26-E29, E31, F21, I%?-R4, RkF7.7, F31, Gl, G3-G4, HI-H3, H5
The large address signals LANA16’correspond to the AZ-Al6 signals of the ISA b&, but they
are valid earlier because, unlike the A2-A16 signals, they are not latched and thus delayed.
LA2&LA31 is the high-order address byte of the 31-bit ElSA data bus. Together with the non-
latched ISA address signals LA17-LA23, the LA2-LA16 and LA24-LA31 signals form the
address bus for fast EISA bus cycles. ISA bus cycles, on the other hand, use the latched (and
therefore slower) address signals AsA16. In EISA bus cycles, - the two
- low-order address bib
corresponding to A0 and Al are decoded from the four bits BEO-BE3.

Terminal Fll
This locked cycle signal is active (low) if a busmaster on the motherboard carries out a locked
bus cycle with an EISA slave. Using this, the busmaster &the exclusive access right to memory
as long as LOCK is actiye. Other chips such as, for example, DMA cannot use the memory
during this time period.

Terminal FlO
This signal serves to distinguish memory and I/O_EISA bus cycles+

Termi+ F4-F5, W-F8

fi~connections can be used by EISA OEMs for, their own purposes. I

:- ne system arbitrator respands with a master acknowledge signal MACK t,‘a MREQ from an
external busmaster to pass over control of the ElSA bus.
566 Chaoter 22

Terminal G19
An external device activates the master request signal MREQ to take over control of the EISA
bus as a busmaster. The system arbitrator detects MREQ and passes control if no other master
is active. Normally, the CPU on the motherboard is the active busmaster.

Terminal E9
An EISA master activates the master burst signal MSBURST to inform the EISA bus cantrolle~
that the master can carry out the next bus cycle as a bunt cycle. The bus transfer rate is thus
doubled. This is particularly advantageous for caclie line fills and D?vfA transfers.

Terminal E8
An USA slave activate the slave burst signal SLBISRST to inform the bus controller that it can
follow a burst cycle. Typical EISA slaves that activate SLBIJRST are fast 3%bit main memories

Terminal E2
This signal serves for dock signal coordination at the beginning of-an EISA bus cycle. m
indicates the beginning of a cycle on the local bus.

Terminal El0
The signal serves to distinguish write and read EISA bus cycles.

D32-D63 U/O; corresponding to BEO, BEl, LA%LA311

Terminals C-c& E17-EIS, E20-E23, E26-E29, Ul+lS, F21, F23-F.24, FZ6-F27, E31, Gl, Gs4,
Hl-n3. H5 t
In an enhanced master burst the 30 address terminals LANA31 and the two byte enable
temxinals m and m transfer the 37. high-order data bits of a 64-bit data quantity.
All other contacts are reset-~ ed (rep), are grbuided (GND), OT tramfw supply voltages for chips
(+S V, -5 V) and interfaces or drives (+I2 V, -12 V). I

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