A complete 8-bit Microcontroller in VHDL

In this VHDL project, VHDL code for a microcontroller is presented. The 8-bit
microcontroller is designed, implemented, and operational as a full design which
users can program the microcontroller using assembly language.
The instruction set and architecture of the 8-bit microcontroller are available at
Chapter 13 in the book "Introduction to Logic Circuits and Logic Design with VHDL"
by prof. Brock J. LaMeres. The microcontroller has an 8-bit processor, a 128-byte
program memory, a 96-byte RAM, 16x8-bit output ports, and 16x8-bit input ports.
Users can program the microcontroller by inserting opcodes and operands in the
program memory.

After completing the design, the microcontroller is implemented on FPGA DE0-nano

board as shown in the figure below.
VHDL Code for microcontroller

The VHDL code for the ALU of the microcontroller:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for 8-bit Microcontroller
-- Submodule VHDL code: ALU
entity ALU is
port (

A,B: in std_logic_vector(7 downto 0);

ALU_Sel:in std_logic_vector(2 downto 0);
NZVC: out std_logic_vector(3 downto 0);
Result: out std_logic_vector(7 downto 0)
);
end ALU;
architecture Behavioral of ALU is
signal ALU_Result:std_logic_vector(7 downto 0);
signal ALU_ADD: std_logic_vector(8 downto 0);
signal C,Z,V,N,add_ov,sub_ov: std_logic;
begin
process(ALU_Sel,A,B)
begin

ALU_ADD <= "000000000";

case(ALU_Sel) is
when "000" => -- ADD
ALU_ADD <= ('0' & A )+ ('0'& B);
ALU_Result <= A + B;
when "001" => -- SUB
ALU_Result <= B - A;
ALU_ADD <= ('0' & B) - ('0' & A);
when "010" => -- AND
ALU_Result <= A and B;
when "011" => -- OR
ALU_Result <= A or B;
when "100" => -- Increment
ALU_Result <= A + x"01";
when "101" => -- Decrement
ALU_Result <= A - x"01";
when others =>
ALU_Result <= A + B;
end case;
 end process;
Result <= ALU_Result;
N <= ALU_Result(7);
Z <= '1' when ALU_Result = x"00" else
'0';
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
---Overflow flag---------------------------------------
add_ov<= (A(7)and B(7) and (not ALU_Result(7))) or ((not A(7))and (not B(7))
and ALU_Result(7));
sub_ov<= (A(7)and (not B(7)) and (not ALU_Result(7))) or ((not A(7))and B(7)
and ALU_Result(7));
with ALU_Sel select
V <= add_ov when "000",
sub_ov when "001",
'0' when others;
-- Carry out flag
with ALU_Sel select
C <= ALU_ADD(8) when "000",
ALU_ADD(8) when "001",
'0' when others;
NZVC <= N & Z & V & C;
end Behavioral;
The VHDL code for RAM memory of the microcontroller:
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for 8-bit Microcontroller
-- Submodule VHDL code: MEMORY SYSTEM for 8-BIT COMPUTER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-----------------------------------------------------------------
------------ MEMORY SYSTEM for 8-BIT COMPUTER -------------------
-----------------------------------------------------------------
entity memory is
port (
address: in std_logic_vector(7 downto 0);
data_in: in std_logic_vector(7 downto 0);
write: in std_logic;
port_in_00: in std_logic_vector(7 downto 0);
port_in_01: in std_logic_vector(7 downto 0);
port_in_02: in std_logic_vector(7 downto 0);
port_in_03: in std_logic_vector(7 downto 0);
port_in_04: in std_logic_vector(7 downto 0);
port_in_05: in std_logic_vector(7 downto 0);
port_in_06: in std_logic_vector(7 downto 0);
port_in_07: in std_logic_vector(7 downto 0);
port_in_08: in std_logic_vector(7 downto 0);
port_in_09: in std_logic_vector(7 downto 0);
port_in_10: in std_logic_vector(7 downto 0);
port_in_11: in std_logic_vector(7 downto 0);
port_in_12: in std_logic_vector(7 downto 0);
port_in_13: in std_logic_vector(7 downto 0);
port_in_14: in std_logic_vector(7 downto 0);
port_in_15: in std_logic_vector(7 downto 0);
clock,reset: in std_logic;
data_out: out std_logic_vector(7 downto 0);
port_out_00: out std_logic_vector(7 downto 0);
port_out_01: out std_logic_vector(7 downto 0);
port_out_02: out std_logic_vector(7 downto 0);
port_out_03: out std_logic_vector(7 downto 0);
port_out_04: out std_logic_vector(7 downto 0);
 port_out_05: out std_logic_vector(7 downto 0);
port_out_06: out std_logic_vector(7 downto 0);
port_out_07: out std_logic_vector(7 downto 0);
port_out_08: out std_logic_vector(7 downto 0);
port_out_09: out std_logic_vector(7 downto 0);
port_out_10: out std_logic_vector(7 downto 0);
port_out_11: out std_logic_vector(7 downto 0);
port_out_12: out std_logic_vector(7 downto 0);
port_out_13: out std_logic_vector(7 downto 0);
port_out_14: out std_logic_vector(7 downto 0);
port_out_15: out std_logic_vector(7 downto 0)
);
end memory;
architecture Behavioral of memory is
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
component rom_128x8_sync
port (
address: in std_logic_vector(6 downto 0);
data_out: out std_logic_vector(7 downto 0);
clock: in std_logic
);
end component rom_128x8_sync;
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
component rw_96x8_sync
port(
address: in std_logic_vector(6 downto 0);
data_in: in std_logic_vector(7 downto 0);
write: in std_logic;
clock: in std_logic;
data_out: out std_logic_vector(7 downto 0)
);
end component rw_96x8_sync;
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
component Output_Ports
port (
address: in std_logic_vector(3 downto 0);
data_in: in std_logic_vector(7 downto 0);
write: in std_logic;
clock: in std_logic;
reset: in std_logic;
port_out_00: out std_logic_vector(7 downto 0);
port_out_01: out std_logic_vector(7 downto 0);
port_out_02: out std_logic_vector(7 downto 0);
port_out_03: out std_logic_vector(7 downto 0);
port_out_04: out std_logic_vector(7 downto 0);
port_out_05: out std_logic_vector(7 downto 0);
port_out_06: out std_logic_vector(7 downto 0);
port_out_07: out std_logic_vector(7 downto 0);
port_out_08: out std_logic_vector(7 downto 0);
port_out_09: out std_logic_vector(7 downto 0);
port_out_10: out std_logic_vector(7 downto 0);
port_out_11: out std_logic_vector(7 downto 0);
port_out_12: out std_logic_vector(7 downto 0);
port_out_13: out std_logic_vector(7 downto 0);
port_out_14: out std_logic_vector(7 downto 0);
port_out_15: out std_logic_vector(7 downto 0)
);
end component Output_Ports;
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
 signal rom_out,ram_out:std_logic_vector(7 downto 0);
signal output_port_addr: std_logic_vector(3 downto 0);
signal ram_address,rom_address: std_logic_vector(6 downto 0);
begin
ram_address <= address(6 downto 0) when (address(7)= '1') else
"0000000";
rom_address <= address(6 downto 0) when (address(7)='0') else
"0000000";
output_port_addr <= address(3 downto 0) when (address(7 downto 4)= x"E")
else
"0000";
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
rom_128x8_sync_u: rom_128x8_sync port map
(
address => rom_address,
clock => clock,
data_out => rom_out
);
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
rw_96x8_sync_u: rw_96x8_sync port map
(
address => ram_address,
data_in => data_in,
write => write,
clock => clock,
data_out => ram_out
);
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
Output_Ports_u: Output_Ports port map
(
address => output_port_addr,
data_in => data_in,
write => write,
clock => clock,
reset => reset,
port_out_00 => port_out_00,
port_out_01 => port_out_01,
port_out_02 => port_out_02,
port_out_03 => port_out_03,
port_out_04 => port_out_04,
port_out_05 => port_out_05,
port_out_06 => port_out_06,
port_out_07 => port_out_07,
port_out_08 => port_out_08,
port_out_09 => port_out_09,
port_out_10 => port_out_10,
port_out_11 => port_out_11,
port_out_12 => port_out_12,
port_out_13 => port_out_13,
port_out_14 => port_out_14,
port_out_15 => port_out_15
);
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
--- Multiplexer Output
data_out <= rom_out when address < x"80" else
ram_out when address < x"E0" else
port_in_00 when address = x"F0" else
port_in_01 when address = x"F1" else
port_in_02 when address = x"F2" else
 port_in_03 when address = x"F3" else
port_in_04 when address = x"F4" else
port_in_05 when address = x"F5" else
port_in_06 when address = x"F6" else
port_in_07 when address = x"F7" else
port_in_08 when address = x"F8" else
port_in_09 when address = x"F9" else
port_in_10 when address = x"FA" else
port_in_11 when address = x"FB" else
port_in_12 when address = x"FC" else
port_in_13 when address = x"FD" else
port_in_14 when address = x"FE" else
port_in_15 when address = x"FF" else
x"00";
end Behavioral;
The VHDL code for rom_128x8_sync.vhd: here
The VHDL code for rw_96x8_sync.vhd: here
The VHDL code for Output_Ports.vhd: here
The VHDL code for the data-path of the microcontroller:
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for 8-bit Microcontroller
-- Submodule VHDL code for the data path of the microcontroller
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
-------------------------
-- data_path
-------------------------
entity data_path is
port (
clock,reset: in std_logic;
IR_Load: in std_logic;
IR: out std_logic_vector(7 downto 0);
MAR_Load: in std_logic;
address: out std_logic_vector(7 downto 0);
PC_Load: in std_logic;
PC_Inc: in std_logic;
A_Load: in std_logic;
B_Load: in std_logic;
ALU_Sel: in std_logic_vector(2 downto 0);
CCR_Result: out std_logic_vector(3 downto 0);
CCR_Load: in std_logic;
Bus2_Sel: in std_logic_vector(1 downto 0);
Bus1_Sel: in std_logic_vector(1 downto 0);
from_memory: in std_logic_vector(7 downto 0);
to_memory: out std_logic_vector(7 downto 0)
);
end data_path;
architecture Behavioral of data_path is
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
component ALU
port (
A,B: in std_logic_vector(7 downto 0);
ALU_Sel:in std_logic_vector(2 downto 0);
NZVC: out std_logic_vector(3 downto 0);
Result: out std_logic_vector(7 downto 0)
);
end component ALU;
signal BUS2,BUS1,ALU_Result: std_logic_vector(7 downto 0);
signal IR_Reg,MAR,PC,A_Reg,B_Reg: std_logic_vector(7 downto 0);
signal CCR_in,CCR: std_logic_vector(3 downto 0);
begin
-- Instruction Register
process(clock,reset)
begin
if(reset='0') then
IR_Reg <= x"00";
elsif(rising_edge(clock)) then
if(IR_Load='1') then
IR_Reg <= BUS2;
end if;
end if;
end process;
IR <= IR_Reg;
-- MAR Register
process(clock,reset)
begin
if(reset='0') then
MAR <= x"00";
elsif(rising_edge(clock)) then
if(MAR_Load='1') then
MAR <= BUS2;
end if;
end if;
end process;
address <= MAR;
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
-- PC
process(clock,reset)
begin
if(reset='0') then
PC <= x"00";
elsif(rising_edge(clock)) then
if(PC_Load='1') then
PC <= BUS2;
elsif(PC_Inc='1') then
PC <= PC + x"01";
end if;
end if;
end process;
-- A register
process(clock,reset)
begin
if(reset='0') then
A_Reg <= x"00";
elsif(rising_edge(clock)) then
if(A_Load='1') then
A_Reg <= BUS2;
end if;
end if;
end process;
-- B register
process(clock,reset)
begin
if(reset='0') then
B_Reg <= x"00";
elsif(rising_edge(clock)) then
 if(B_Load='1') then
B_Reg <= BUS2;
end if;
end if;
end process;
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
--- ALU
ALU_unit: ALU port map
(
A => B_Reg,
B => BUS1,
ALU_Sel => ALU_Sel,
NZVC => CCR_in,
Result => ALU_Result
);
--- CCR Register
process(clock,reset)
begin
if(reset='0') then
CCR <= x"0";
elsif(rising_edge(clock)) then
if(CCR_Load='1') then
CCR <= CCR_in;
end if;
end if;
end process;
CCR_Result <= CCR;
---- MUX BUS2
BUS2 <= ALU_Result when Bus2_Sel = "00" else
BUS1 when Bus2_Sel = "01" else
from_memory when Bus2_Sel = "10" else
x"00";
--- MUX BUS1
BUS1 <= PC when Bus1_Sel = "00" else
A_Reg when Bus1_Sel = "01" else
B_Reg when Bus1_Sel = "10" else
x"00";
to_memory <= BUS1;
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
end Behavioral;
The VHDL code for the control unit of the microcontroller:
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for 8-bit Microcontroller
-- Submodule VHDL code for the control unit of the microcontroller
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- control unit
entity control_unit is
port (
clock,reset: in std_logic;
IR_Load: out std_logic;
IR: in std_logic_vector(7 downto 0);
MAR_Load: out std_logic;
PC_Load: out std_logic;
PC_Inc: out std_logic;
A_Load: out std_logic;
B_Load:out std_logic;
ALU_Sel:out std_logic_vector(2 downto 0);
CCR_Result: in std_logic_vector(3 downto 0);
 CCR_Load: out std_logic;
Bus2_Sel: out std_logic_vector(1 downto 0);
Bus1_Sel: out std_logic_vector(1 downto 0);
write: out std_logic
);
end control_unit;
architecture Behavioral of control_unit is
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
type FSM is
(S_FETCH_0,S_FETCH_1,S_FETCH_2,S_DECODE_3,S_LOAD_AND_STORE_4,S_LOAD_AND_STORE_5,S_L
OAD_AND_STORE_6,

S_LOAD_AND_STORE_7,S_DATA_MAN_4,

S_BRANCH_4,S_BRANCH_5,S_BRANCH_6

);
signal current_state,next_state: FSM;
signal LOAD_STORE_OP,DATA_MAN_OP,BRANCH_OP: std_logic;
begin
-- FSM State FFs
process(clock,reset)
begin
if(reset='0') then
current_state <= S_FETCH_0;
elsif(rising_edge(clock)) then
current_state <= next_state;
end if;
end process;
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
process(current_state,IR,CCR_Result,LOAD_STORE_OP,DATA_MAN_OP,BRANCH_OP)
begin
IR_Load <= '0';
MAR_Load <= '0';
PC_Load <= '0';
PC_Inc <= '0';
A_Load <= '0';
B_Load <= '0';
ALU_Sel <= "000";
CCR_Load <= '0';
Bus2_Sel <= "00";
Bus1_Sel <= "00";
write <= '0';
case(current_state) is
when S_FETCH_0 =>
Bus1_Sel <= "00"; -- PC
Bus2_Sel <= "01"; -- BUS1
MAR_Load <= '1';
next_state <= S_FETCH_1;
when S_FETCH_1 =>
PC_Inc <= '1';
next_state <= S_FETCH_2;
when S_FETCH_2 =>
Bus2_Sel <= "10";
IR_Load <= '1';
next_state <= S_DECODE_3;
when S_DECODE_3 =>
if(LOAD_STORE_OP='1') then
 next_state <= S_LOAD_AND_STORE_4;
elsif(DATA_MAN_OP='1') then
next_state <= S_DATA_MAN_4;
elsif(BRANCH_OP='1') then
next_state <= S_BRANCH_4;
end if;
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
---- LOAD AND STORE INSTRUCTIONS:
when S_LOAD_AND_STORE_4 =>
if(IR >= x"86" and IR <= x"89")then -- LOAD IMMEDIATE
Bus1_Sel <= "00";
Bus2_Sel <= "01";
MAR_Load <= '1';
elsif(IR = x"96" or IR = x"97")then -- LOAD IMMEDIATE
Bus1_Sel <= "00";
Bus2_Sel <= "01";
MAR_Load <= '1';
end if;
next_state <= S_LOAD_AND_STORE_5;
when S_LOAD_AND_STORE_5 =>
if(IR >= x"86" and IR <= x"89")then -- LOAD IMMEDIATE
PC_Inc <= '1';
elsif(IR = x"96" or IR = x"97")then
PC_Inc <= '1';
end if;
next_state <= S_LOAD_AND_STORE_6;
when S_LOAD_AND_STORE_6 =>
if(IR=x"86")then -- LOAD IMMEDIATE A
Bus2_Sel <= "10";
A_Load <= '1';
next_state <= S_FETCH_0;
elsif(IR=x"87" or IR=x"89") then -- LOAD A DIRECT
Bus2_Sel <= "10";
MAR_Load <= '1';
next_state <= S_LOAD_AND_STORE_7;
elsif(IR=x"88")then -- LOAD IMMEDIATE B
Bus2_Sel <= "10";
B_Load <= '1';
next_state <= S_FETCH_0;
elsif(IR = x"96" or IR = x"97")then
Bus2_Sel <= "10";
MAR_Load <= '1';
next_state <= S_LOAD_AND_STORE_7;

end if;
when S_LOAD_AND_STORE_7 =>
if(IR=x"87") then
Bus2_Sel <= "10";
A_Load <= '1';
next_state <= S_FETCH_0;
elsif(IR=x"89") then
Bus2_Sel <= "10";
B_Load <= '1';
next_state <= S_FETCH_0;
elsif(IR=x"96") then
write <= '1';
Bus1_Sel <= "01";
next_state <= S_FETCH_0;
elsif(IR=x"97") then
 write <= '1';
Bus1_Sel <= "10";
next_state <= S_FETCH_0;
end if;
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
---- DATA MANIPULATION INSTRUCTIONS:
when S_DATA_MAN_4 =>
CCR_Load <= '1';
if(IR=x"42") then
ALU_Sel <= "000";
Bus1_Sel <= "01";
Bus2_Sel <= "00";
A_Load <= '1';
elsif(IR=x"43") then
ALU_Sel <= "001";
Bus1_Sel <= "01";
Bus2_Sel <= "00";
A_Load <= '1';
elsif(IR=x"44") then
ALU_Sel <= "010";
Bus1_Sel <= "01";
Bus2_Sel <= "00";
A_Load <= '1';
elsif(IR=x"45") then
ALU_Sel <= "011";
Bus1_Sel <= "01";
Bus2_Sel <= "00";
A_Load <= '1';
elsif(IR=x"46") then
ALU_Sel <= "100";
Bus1_Sel <= "01";
Bus2_Sel <= "00";
A_Load <= '1';
elsif(IR=x"47") then
ALU_Sel <= "100";
Bus1_Sel <= "10";
Bus2_Sel <= "00";
B_Load <= '1';
elsif(IR=x"48") then
ALU_Sel <= "101";
Bus1_Sel <= "01";
Bus2_Sel <= "00";
A_Load <= '1';
elsif(IR=x"49") then
ALU_Sel <= "101";
Bus1_Sel <= "10";
Bus2_Sel <= "00";
B_Load <= '1';
end if;
next_state <= S_FETCH_0;
when S_BRANCH_4 =>
if(IR >= x"20" and IR <= x"28")then -- BRA
Bus1_Sel <= "00";
Bus2_Sel <= "01";
MAR_Load <= '1';
end if;
next_state <= S_BRANCH_5;
when S_BRANCH_5 =>
if(IR >= x"20" and IR <= x"28")then -- BRA
 PC_Inc <= '1';
end if;
next_state <= S_BRANCH_6;
when S_BRANCH_6 =>
if(IR=x"20")then -- BRA
Bus2_Sel <= "10";
PC_Load <= '1';
elsif(IR=x"21")then -- BMI
Bus2_Sel <= "10";
if(CCR_Result(3)='1') then
PC_Load <= '1';
end if;
elsif(IR=x"22")then -- BPL
Bus2_Sel <= "10";
if(CCR_Result(3)='0') then
PC_Load <= '1';
end if;
elsif(IR=x"23")then -- BEQ
Bus2_Sel <= "10";
if(CCR_Result(2)='1') then-- Z = '1'?
PC_Load <= '1';
end if;
elsif(IR=x"24")then -- BNE
Bus2_Sel <= "10";
if(CCR_Result(2)='0') then-- Z = '0'?
PC_Load <= '1';
end if;
elsif(IR=x"25")then -- BVS
Bus2_Sel <= "10";
if(CCR_Result(1)='1') then-- V = '1'?
PC_Load <= '1';
end if;
elsif(IR=x"26")then -- BVC
Bus2_Sel <= "10";
if(CCR_Result(1)='0') then-- V = '0'?
PC_Load <= '1';
end if;
elsif(IR=x"27")then -- BCS
Bus2_Sel <= "10";
if(CCR_Result(0)='1') then-- C = '1'?
PC_Load <= '1';
end if;
elsif(IR=x"28")then -- BCC
Bus2_Sel <= "10";
if(CCR_Result(0)='0') then-- C = '0'?
PC_Load <= '1';
end if;
end if;
next_state <= S_FETCH_0;
when others =>
next_state <= S_FETCH_0;
end case;
end process;
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
LOAD_STORE_OP <= '1' when IR = x"86" else
'1' when IR = x"87" else
'1' when IR = x"88" else
'1' when IR = x"89" else
'1' when IR = x"96" else
 '1' when IR = x"97" else
'0';
DATA_MAN_OP <= '1' when (IR >= x"42" and IR <=x"49") else
'0';
BRANCH_OP <= '1' when (IR >= x"20" and IR <= x"28") else
'0';
end Behavioral;
The VHDL code for the CPU of the microcontroller:
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for 8-bit Microcontroller
-- VHDL code for the CPU of the microcontroller
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- CPU in VHDL
entity cpu is
port(
clock, reset: in std_logic;
address: out std_logic_vector(7 downto 0);
from_memory: in std_logic_vector(7 downto 0);
write: out std_logic;
to_memory: out std_logic_vector(7 downto 0)
);
end cpu;
architecture Behavioral of cpu is
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
component control_unit
port (
clock,reset: in std_logic;
IR_Load: out std_logic;
IR: in std_logic_vector(7 downto 0);
MAR_Load: out std_logic;
PC_Load: out std_logic;
PC_Inc: out std_logic;
A_Load: out std_logic;
B_Load:out std_logic;
ALU_Sel:out std_logic_vector(2 downto 0);
CCR_Result: in std_logic_vector(3 downto 0);
CCR_Load: out std_logic;
Bus2_Sel: out std_logic_vector(1 downto 0);
Bus1_Sel: out std_logic_vector(1 downto 0);
write: out std_logic
);
end component control_unit;
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
component data_path
port (
clock,reset: in std_logic;
IR_Load: in std_logic;
IR: out std_logic_vector(7 downto 0);
MAR_Load: in std_logic;
address: out std_logic_vector(7 downto 0);
PC_Load: in std_logic;
PC_Inc: in std_logic;
A_Load: in std_logic;
B_Load: in std_logic;
ALU_Sel: in std_logic_vector(2 downto 0);
CCR_Result: out std_logic_vector(3 downto 0);
CCR_Load: in std_logic;
Bus2_Sel: in std_logic_vector(1 downto 0);
 Bus1_Sel: in std_logic_vector(1 downto 0);
from_memory: in std_logic_vector(7 downto 0);
to_memory: out std_logic_vector(7 downto 0)
);
end component data_path;
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
signal IR_Load: std_logic;
signal IR: std_logic_vector(7 downto 0);
signal MAR_Load: std_logic;
signal PC_Load: std_logic;
signal PC_Inc: std_logic;
signal A_Load: std_logic;
signal B_Load: std_logic;
signal ALU_Sel: std_logic_vector(2 downto 0);
signal CCR_Result: std_logic_vector(3 downto 0);
signal CCR_Load: std_logic;
signal Bus2_Sel: std_logic_vector(1 downto 0);
signal Bus1_Sel: std_logic_vector(1 downto 0);
begin
-----------------------
-- control_unit
control_unit_module: control_unit port map
(
clock => clock,
reset => reset,
IR_Load => IR_Load,
IR => IR,
MAR_Load => MAR_Load,
PC_Load => PC_Load,
PC_Inc => PC_Inc,
A_Load => A_Load,
B_Load => B_Load,
ALU_Sel => ALU_Sel,
CCR_Result => CCR_Result,
CCR_Load => CCR_Load,
Bus2_Sel => Bus2_Sel,
Bus1_Sel => Bus1_Sel,
write => write
);
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
-- data_path
data_path_u: data_path port map
(
clock => clock,
reset => reset,
IR_Load => IR_Load,
IR => IR,
MAR_Load => MAR_Load,
address => address,
PC_Load => PC_Load,
PC_Inc => PC_Inc,
A_Load => A_Load,
B_Load => B_Load,
ALU_Sel => ALU_Sel,
CCR_Result => CCR_Result,
CCR_Load => CCR_Load,
Bus2_Sel => Bus2_Sel,
Bus1_Sel => Bus1_Sel,
from_memory => from_memory,
 to_memory => to_memory
);
end Behavioral;
The Complete VHDL code for the microcontroller and VHDL Testbench for simulation:
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for 8-bit Microcontroller
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--- Top level VHDL code for the microcontroller
entity computer is
port(
clock,reset: in std_logic;
port_in_00: in std_logic_vector(7 downto 0);
port_in_01: in std_logic_vector(7 downto 0);
port_in_02: in std_logic_vector(7 downto 0);
port_in_03: in std_logic_vector(7 downto 0);
port_in_04: in std_logic_vector(7 downto 0);
port_in_05: in std_logic_vector(7 downto 0);
port_in_06: in std_logic_vector(7 downto 0);
port_in_07: in std_logic_vector(7 downto 0);
port_in_08: in std_logic_vector(7 downto 0);
port_in_09: in std_logic_vector(7 downto 0);
port_in_10: in std_logic_vector(7 downto 0);
port_in_11: in std_logic_vector(7 downto 0);
port_in_12: in std_logic_vector(7 downto 0);
port_in_13: in std_logic_vector(7 downto 0);
port_in_14: in std_logic_vector(7 downto 0);
port_in_15: in std_logic_vector(7 downto 0);
port_out_00: out std_logic_vector(7 downto 0);
port_out_01: out std_logic_vector(7 downto 0);
port_out_02: out std_logic_vector(7 downto 0);
port_out_03: out std_logic_vector(7 downto 0);
port_out_04: out std_logic_vector(7 downto 0);
port_out_05: out std_logic_vector(7 downto 0);
port_out_06: out std_logic_vector(7 downto 0);
port_out_07: out std_logic_vector(7 downto 0);
port_out_08: out std_logic_vector(7 downto 0);
port_out_09: out std_logic_vector(7 downto 0);
port_out_10: out std_logic_vector(7 downto 0);
port_out_11: out std_logic_vector(7 downto 0);
port_out_12: out std_logic_vector(7 downto 0);
port_out_13: out std_logic_vector(7 downto 0);
port_out_14: out std_logic_vector(7 downto 0);
port_out_15: out std_logic_vector(7 downto 0)
);
end computer;
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
architecture Behavioral of computer is
component cpu
port(
clock, reset: in std_logic;
address: out std_logic_vector(7 downto 0);
from_memory: in std_logic_vector(7 downto 0);
write: out std_logic;
to_memory: out std_logic_vector(7 downto 0)
);
end component cpu;
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
component memory
 port (
address: in std_logic_vector(7 downto 0);
data_in: in std_logic_vector(7 downto 0);
write: in std_logic;
port_in_00: in std_logic_vector(7 downto 0);
port_in_01: in std_logic_vector(7 downto 0);
port_in_02: in std_logic_vector(7 downto 0);
port_in_03: in std_logic_vector(7 downto 0);
port_in_04: in std_logic_vector(7 downto 0);
port_in_05: in std_logic_vector(7 downto 0);
port_in_06: in std_logic_vector(7 downto 0);
port_in_07: in std_logic_vector(7 downto 0);
port_in_08: in std_logic_vector(7 downto 0);
port_in_09: in std_logic_vector(7 downto 0);
port_in_10: in std_logic_vector(7 downto 0);
port_in_11: in std_logic_vector(7 downto 0);
port_in_12: in std_logic_vector(7 downto 0);
port_in_13: in std_logic_vector(7 downto 0);
port_in_14: in std_logic_vector(7 downto 0);
port_in_15: in std_logic_vector(7 downto 0);
clock,reset: in std_logic;
data_out: out std_logic_vector(7 downto 0);
port_out_00: out std_logic_vector(7 downto 0);
port_out_01: out std_logic_vector(7 downto 0);
port_out_02: out std_logic_vector(7 downto 0);
port_out_03: out std_logic_vector(7 downto 0);
port_out_04: out std_logic_vector(7 downto 0);
port_out_05: out std_logic_vector(7 downto 0);
port_out_06: out std_logic_vector(7 downto 0);
port_out_07: out std_logic_vector(7 downto 0);
port_out_08: out std_logic_vector(7 downto 0);
port_out_09: out std_logic_vector(7 downto 0);
port_out_10: out std_logic_vector(7 downto 0);
port_out_11: out std_logic_vector(7 downto 0);
port_out_12: out std_logic_vector(7 downto 0);
port_out_13: out std_logic_vector(7 downto 0);
port_out_14: out std_logic_vector(7 downto 0);
port_out_15: out std_logic_vector(7 downto 0)
);
end component memory;
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
signal address,data_in,data_out: std_logic_vector(7 downto 0);
signal write: std_logic;
begin
--- cpu
cpu_u: cpu port map
(
clock => clock,
reset => reset,
address => address,
write => write,
to_memory => data_in,
from_memory => data_out
);
-- memory
memory_unit: memory port map
(
clock => clock,
reset => reset,
 port_out_00 => port_out_00,
port_out_01 => port_out_01,
port_out_02 => port_out_02,
port_out_03 => port_out_03,
port_out_04 => port_out_04,
port_out_05 => port_out_05,
port_out_06 => port_out_06,
port_out_07 => port_out_07,
port_out_08 => port_out_08,
port_out_09 => port_out_09,
port_out_10 => port_out_10,
port_out_11 => port_out_11,
port_out_12 => port_out_12,
port_out_13 => port_out_13,
port_out_14 => port_out_14,
port_out_15 => port_out_15,
port_in_00 => port_in_00,
port_in_01 => port_in_01,
port_in_02 => port_in_02,
port_in_03 => port_in_03,
port_in_04 => port_in_04,
port_in_05 => port_in_05,
port_in_06 => port_in_06,
port_in_07 => port_in_07,
port_in_08 => port_in_08,
port_in_09 => port_in_09,
port_in_10 => port_in_10,
port_in_11 => port_in_11,
port_in_12 => port_in_12,
port_in_13 => port_in_13,
port_in_14 => port_in_14,
port_in_15 => port_in_15,
data_out => data_out,
address => address,
data_in => data_in,
write => write
);
end Behavioral;
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
-- VHDL Testbench for the microcontroller
library IEEE;
use IEEE.std_logic_1164.all;

entity computer_TB is
end entity;

architecture computer_TB_arch of computer_TB is

constant t_clk_per : time := 20 ns; -- Period of a 50MHZ Clock

-- Component Declaration

component computer
port ( clock : in std_logic;
reset : in std_logic;
port_in_00 : in std_logic_vector (7 downto 0);
port_in_01 : in std_logic_vector (7 downto 0);
port_in_02 : in std_logic_vector (7 downto 0);
port_in_03 : in std_logic_vector (7 downto 0);
 port_in_04 : in std_logic_vector (7 downto 0);
port_in_05 : in std_logic_vector (7 downto 0);
port_in_06 : in std_logic_vector (7 downto 0);
port_in_07 : in std_logic_vector (7 downto 0);
port_in_08 : in std_logic_vector (7 downto 0);
port_in_09 : in std_logic_vector (7 downto 0);
port_in_10 : in std_logic_vector (7 downto 0);
port_in_11 : in std_logic_vector (7 downto 0);
port_in_12 : in std_logic_vector (7 downto 0);
port_in_13 : in std_logic_vector (7 downto 0);
port_in_14 : in std_logic_vector (7 downto 0);
port_in_15 : in std_logic_vector (7 downto 0);

port_out_00 : out std_logic_vector (7 downto 0);

port_out_01 : out std_logic_vector (7 downto 0);
port_out_02 : out std_logic_vector (7 downto 0);
port_out_03 : out std_logic_vector (7 downto 0);
port_out_04 : out std_logic_vector (7 downto 0);
port_out_05 : out std_logic_vector (7 downto 0);
port_out_06 : out std_logic_vector (7 downto 0);
port_out_07 : out std_logic_vector (7 downto 0);
port_out_08 : out std_logic_vector (7 downto 0);
port_out_09 : out std_logic_vector (7 downto 0);
port_out_10 : out std_logic_vector (7 downto 0);
port_out_11 : out std_logic_vector (7 downto 0);
port_out_12 : out std_logic_vector (7 downto 0);
port_out_13 : out std_logic_vector (7 downto 0);
port_out_14 : out std_logic_vector (7 downto 0);
port_out_15 : out std_logic_vector (7 downto 0));
end component;
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
-- Signal Declaration

signal clock_TB : std_logic;

signal reset_TB : std_logic;
signal port_out_00_TB : std_logic_vector (7 downto 0);
signal port_out_01_TB : std_logic_vector (7 downto 0);
signal port_out_02_TB : std_logic_vector (7 downto 0);
signal port_out_03_TB : std_logic_vector (7 downto 0);
signal port_out_04_TB : std_logic_vector (7 downto 0);
signal port_out_05_TB : std_logic_vector (7 downto 0);
signal port_out_06_TB : std_logic_vector (7 downto 0);
signal port_out_07_TB : std_logic_vector (7 downto 0);
signal port_out_08_TB : std_logic_vector (7 downto 0);
signal port_out_09_TB : std_logic_vector (7 downto 0);
signal port_out_10_TB : std_logic_vector (7 downto 0);
signal port_out_11_TB : std_logic_vector (7 downto 0);
signal port_out_12_TB : std_logic_vector (7 downto 0);
signal port_out_13_TB : std_logic_vector (7 downto 0);
signal port_out_14_TB : std_logic_vector (7 downto 0);
signal port_out_15_TB : std_logic_vector (7 downto 0);
signal port_in_00_TB : std_logic_vector (7 downto 0);
signal port_in_01_TB : std_logic_vector (7 downto 0);
signal port_in_02_TB : std_logic_vector (7 downto 0);
signal port_in_03_TB : std_logic_vector (7 downto 0);
signal port_in_04_TB : std_logic_vector (7 downto 0);
signal port_in_05_TB : std_logic_vector (7 downto 0);
signal port_in_06_TB : std_logic_vector (7 downto 0);
signal port_in_07_TB : std_logic_vector (7 downto 0);
 signal port_in_08_TB : std_logic_vector (7 downto 0);
signal port_in_09_TB : std_logic_vector (7 downto 0);
signal port_in_10_TB : std_logic_vector (7 downto 0);
signal port_in_11_TB : std_logic_vector (7 downto 0);
signal port_in_12_TB : std_logic_vector (7 downto 0);
signal port_in_13_TB : std_logic_vector (7 downto 0);
signal port_in_14_TB : std_logic_vector (7 downto 0);
signal port_in_15_TB : std_logic_vector (7 downto 0);

begin
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
micrococontroller_unit : computer
port map (clock => clock_TB,
reset => reset_TB,
port_out_00 => port_out_00_TB,
port_out_01 => port_out_01_TB,
port_out_02 => port_out_02_TB,
port_out_03 => port_out_03_TB,
port_out_04 => port_out_04_TB,
port_out_05 => port_out_05_TB,
port_out_06 => port_out_06_TB,
port_out_07 => port_out_07_TB,
port_out_08 => port_out_08_TB,
port_out_09 => port_out_09_TB,
port_out_10 => port_out_10_TB,
port_out_11 => port_out_11_TB,
port_out_12 => port_out_12_TB,
port_out_13 => port_out_13_TB,
port_out_14 => port_out_14_TB,
port_out_15 => port_out_15_TB,
port_in_00 => port_in_00_TB,
port_in_01 => port_in_01_TB,
port_in_02 => port_in_02_TB,
port_in_03 => port_in_03_TB,
port_in_04 => port_in_04_TB,
port_in_05 => port_in_05_TB,
port_in_06 => port_in_06_TB,
port_in_07 => port_in_07_TB,
port_in_08 => port_in_08_TB,
port_in_09 => port_in_09_TB,
port_in_10 => port_in_10_TB,
port_in_11 => port_in_11_TB,
port_in_12 => port_in_12_TB,
port_in_13 => port_in_13_TB,
port_in_14 => port_in_14_TB,
port_in_15 => port_in_15_TB);
CLOCK_STIM : process
begin
clock_TB <= '0'; wait for 0.5*t_clk_per;
clock_TB <= '1'; wait for 0.5*t_clk_per;
end process;
-----------------------------------------------
RESET_STIM : process
begin
reset_TB <= '0'; wait for 0.25*t_clk_per;
reset_TB <= '1'; wait;
end process;
-----------------------------------------------
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
 PORT_STIM : process
begin
port_in_00_TB <= x"00";
port_in_01_TB <= x"11";
port_in_02_TB <= x"22";
port_in_03_TB <= x"33";
port_in_04_TB <= x"44";
port_in_05_TB <= x"55";
port_in_06_TB <= x"66";
port_in_07_TB <= x"77";
port_in_08_TB <= x"88";
port_in_09_TB <= x"99";
port_in_10_TB <= x"AA";
port_in_11_TB <= x"BB";
port_in_12_TB <= x"CC";
port_in_13_TB <= x"DD";
port_in_14_TB <= x"EE";
port_in_15_TB <= x"FF";
wait;
end process;

end architecture;
The VHDL implementation of the microcontroller is fully verified by simulation and
demonstrated on FPGA DE0-nano with I/O Shield.