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َو رْ ُز‬
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My Lord! Advance me in Knowledge and true
understanding

MICROPROCESSOR BASED SYSTEM

Lecture4
Dr. Shahrul Naim Sidek
snaim@iiu.edu.my
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 QUIZ 2:

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Memory System Design
(Chapter 8)

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Accessing Memory
3 Bus Architecture Realization
• Asynchronous data transfers
• Involves master-slave transfer. Master = µP, Slave = memory/ I-O
• Master initiates the data transfer, Slave response to it
• Example of an asynchronous read/write cycle from memory

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Asynchronous Data transfer
System Timing: A. µP generates valid add & assert
3 Bus Architecture Realization address strobe (AS) at B
B. AS cause memory to place data on
Add
A
data bus
Bus Add Valid
C. Data on data bus becomes valid
AS D. Memory informs µP about valid data
(from µP) B
E on data bus by DTACK signal
E. µP reads data on data bus and
Data
C negates it AS telling memory that it
High
bus Data Valid finishes reading data
Z
F. Memory negates data DTACK to
complete read cycle
D F
DTACK
This are fully interlocked hand shake
(From memory)
sequence.
- memory access can be extended until
an acknowledge signal is received.
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 System Timing: Bus Control to Access Memory
M68000 Asynchronous Bus Control
Address Strobe (AS*)
• three-state signal indicates the info on the address bus is valid address.
Read/Write (R/W*)
• three-state signal defines data bus transfer as read or write cycle. The
R/W signal relates to the data strobe signals as describes below
Upper and Lower Data Strobes (USD*, LDS*)
• three-state signal and R/W* control the flow of data on the data bus. Next
table lists the combination of these signals and the corresponding data on
the bus.
• When R/W* is high, the processor reads from the data bus, alternatively
when the R/W* is low, the processor drives the data bus. In 8-bit mode,
UDS* is always forced high and the LDS* signals is used.
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 System Timing: Bus Control to Access Memory
M68000 Asynchronous Bus Control
Data Transfer Acknowledge (DTACK*)
• input signal indicates data transfer is completed.
• when processor recognizes DTACK* during read/write cycle, data is
latched/written, and the bus cycle is terminated.

UDS LSD R/W D8-D15 (even byte) D0-D7 (odd byte)

High High - No valid data No valid data
Low Low High Valid data bits 8-15 Valid data bits 0-7
High Low High No valid data Valid data bits 0-7
Low High High Valid data bits 8-15 No valid data
Low Low Low Valid data bits 8-15 Valid data bits 0-7
High Low Low Valid data bits 0-7 Valid data bits 0-7
Low High Low Valid data bits 8-15 Valid data bits 8-15
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
SECTION 8.4

System Timing: Read Data from Memory

M68000 Read Cycle – Flow Chart

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Read Data from Memory

• M68000 read word from memory

• M68000 acts as bus master
– initiates read
• Memory acts as bus slave
– responds to master requests
• Memory-mapped I/O
– “memory” can really be peripheral device
• Interlocked handshaking between master and slave
– master uses R/W*, AS*, UDS*, LDS* to tell memory that
address is present
– slave uses DTACK* to tell CPU that data is ready
• A M68000 memory access takes a minimum of eight clock
states numbered from clock states S0 to S7
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 System Timing: Timing Diagram

• Typically do not care about data/address signal values

• Do care about control signal values
• Not to scale - relationships more important

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Read Timing Diagram

A memory access begins in clock

state S0 and ends in state S7

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Read Timing Diagram

The most important parameter

of the clock is the duration of a cycle,
tCYC.

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Read Timing Diagram

At the start of a memory access

the CPU sends the address of the location
it wishes to read to the memory

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Address Timing

• We are interested in the way the M68000 generates new

address for use in the current memory access

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Read Timing Diagram

In state S1 a new
Initially, in state address becomes
S0 the address valid for the remainder
bus contains the of the memory access
old address

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Read Timing Diagram

The time at which the contents

of the address bus change can be
related to the edges of the clock.
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 System Timing: Address Timing
• The sequence of events that govern the timing of the
address bus
• The “old” address is removed in state S0
• The address bus is floated for a short time, and the CPU
puts out a new address in state S1

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Read Timing Diagram

The old address is removed

in clock state S0 and the
address bus floated

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Read Timing Diagram

tCLAV

The designer is interested in the point at

which the address first becomes valid. This
point is tCLAV seconds after the falling edge
of S0.
tCLAV – duration of clock low to address valid

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Read Timing Diagram

The memory needs to know when

the address from the CPU is valid.
An address strobe, AS*, is asserted
to indicate that the address is valid.

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Memory Add. & Add. Strobe

• We are interested in the relationship between the time at

which the address is valid and the time at which the address
strobe, AS*, is asserted
• When AS* is low it indicates that the address is valid
• We now look at the timing of the clock, the address, and the
address strobe

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Read Timing Diagram

AS* goes active low after

the address has become valid AS* goes inactive
high before the address
changes
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 System Timing: Read Timing Diagram

AS* goes low in clock

state S2

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Timing Diagram
• The M68000 has two data strobes LDS* and UDS*. These select the
lower byte or the upper byte of a word during a memory access
• To keep things simple, we will use a single data strobe, DS*
• The timing of DS* in a read cycle is the same as the address strobe,
AS*.

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Read Timing Diagram

The data strobe, is asserted

at the same time as AS*
Rev 1.0
in a read cycle
Microprocessor Based System (MCT 2219) SBAH Jul’07
 System Timing: Data Bus
• During a read cycle the memory provides the CPU
with data
• Note : valid data does not appear on the data bus
until near the end of the read cycle

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Read Timing Diagram
Data from the memory
appears near the end of
the read cycle

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Analyzing Timing Diagram
• We are going to redraw the timing diagram to remove
clutter
• We aren’t interested in the signal paths themselves,
only in the relationship between the signals

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Read Timing Diagram

We are interested in the relationship

between the clock, AS*/DS* and
the data in a read cycle
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 System Timing: Read Timing Diagram

The earliest time at which the memory can

begin to access data is measured from the point
Rev 1.0
at which the address isBased
Microprocessor first valid
System (MCT 2219) SBAH Jul’07
 System Timing: Read Timing Diagram

Address
becomes valid Data
The time between address valid becomes valid
and data valid is the memory’s
access time, tacc
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 System Timing: Calculating Access Time
• We need to calculate the memory’s access time
• By knowing the access time, we can use the
appropriate memory component
• Equally, if we select a given memory component, we
can calculate whether its access time is adequate for
a particular system

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Read Timing Diagram

Data from the memory is latched into

the 68000 by the falling edge of the
clock in state S6.
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 System Timing: Read Timing Diagram

Data must be valid

tDICL seconds before
the falling edge of S6
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 System Timing: Read Timing Diagram

We know that the time between the

address valid and data valid is tacc
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 System Timing: Read Timing Diagram

The address becomes

valid tCLAV seconds after
the falling edge of S0
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 System Timing: Read Timing Diagram

From the falling •the address becomes valid

edge of S0 to the •the data is accessed
falling edge of S6: •the data is captured
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 System Timing: Read Timing Diagram

The falling edge of S0 to the falling

edge of S6 is three clock cycles
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 System Timing: Read Timing Diagram

3 tcyc = tCLAV + tacc + tDICL

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Example of Read Timing
Requirement

• 68000 clock 8 MHz tCYC = 125 ns

• 68000 CPU tCLAV = 70 ns
• 68000 CPU tDICL = 15 ns
• What is the minimum tacc?
• 3 tCYC = tCLAV + tacc + tDICL
• 375 = 70 + tacc + 15
• tacc = 290 ns

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Write Cycle
M68000 Write Cycle – Flow Chart

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Write Cycle
M68000 Write Cycle – Flow Chart

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 System Timing: Write Cycle
• Similar to read cycle
• Difference
– CPU puts data on data bus early in bus cycle
– UDS*/LDS* not asserted until data on bus (together with DTACK*)
– R/W* is set low
• most memory needs address stable before this
– memory/peripheral reads data
• can use UDS*/LDS* to latch data into memory
• Timing requirements
– typically write cycle specs can be easily met
– memories write faster than they read
• big driver to little cell vs. little cell to big load

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Memory System Design: Organization
• Logical Organization of RAM/ EPROM / EEPROM / ROM

Row &
Address Bus Column
Memory
Decoder
Arrays

Data Bus
Data Controller

CS
OE Control
WE Logic
Rev 1.0 Microprocessor Based System (MCT RAM
2219)& EEPROM Only) SBAH Jul’07
 Memory System Design: Organization
• Static Ram (SRAM) Pin Out

Pin Function Pin Function

Name Name
CS* Chip Select Input I/O0-I/O8 Data input/output
OE* Output Enable Input Vcc Power
WE* Write Enable Input Vss Ground
A0-A14 Address input NC Not Connected

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Memory System Design: Add & Data Bus
• Data bus 8 bit eg. D0-D7 or 16bit (D0-D15)
• Add bus 24bit – Add. 16MB of external memory
• A0 – processor control UDS/LDS (A0 low : UDS, A0 High : LDS)
• A1 – A23 for data transfer
• Data strobe control of data bus
UDS LSD R/W D8-D15 (even byte) D0-D7 (odd byte)
High High - No valid data No valid data
R Low Low High Valid data bits 8-15 Valid data bits 0-7
High Low High No valid data Valid data bits 0-7
Low High High Valid data bits 8-15 No valid data
W* Low Low Low Valid data bits 8-15 Valid data bits 0-7
High Low Low Valid data bits 0-7 Valid data bits 0-7
Low High Low Valid data bits 8-15 Valid data bits 8-15

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Memory System Design: Bus Buffering
• Ensures that we do not exceed the digital output fan out.
• Memory Bus Data bus buffering
Ctrl D0 DB0
Memory LS245
CPU Data
CPU
Add
D7 DB7

• Add bus buffering D8

LS245 DB8

A1 74LS244

CPU
D15
DB15

A8
R/W Dir

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07