Elements of physical design

Unit-3
 Basic concepts of physical design
• Physical design is the actual
process of creating circuits on
silicon.
• Schematic diagrams are
carefully translated in to sets of
geometric patterns (polygons)
• Electric characteristic of a logic
gate depends on the aspect
ratio of the transistors.
• The process of physical design is
performed using a computer
tool called a layout editor.
• Library, cells, instances
 CAD toolsets
• Physical design is based on the CAD tools that simplify the process and aid in the
verification process.
 CAD toolsets
Translates polygon patterns in
Extraction routine
to electrical networks

Checks the layout and

Layout V/S schematic schematic

Layout database and checks

Design rule check every occurrence of the
design rule list on the layout

Automatically finding viable

Place and route wiring routes between 2
points

Electrical rule checker Highlights the connecting paths

 Layout of basic structures
• P substrate (n-well technology)
1. Start with p-type substrate
2. N-well
3. Active
4. Polysilicon
5. P select
6. N select
7. Active contacts
8. Polysilicon contact
9. Metal1
10. Via
11. Metal2
12. Over glass
 p-type substrate
• Oxide layers are grown or deposited between the conducting layers above
the substrate
• The actual values of W and S depend on the layer.
• Manhattan geometries deals with turns are multiple of 90°. Right angle
layout but doesn't give the best packing density. Many layout editors allow
you to select the angles in an arbitrary manner.

s
 N-wells
• An n-well is required at every location where a p-FET is to be
made.

• Wnw= minimum width of a n-well mask feature.

• Snw-nw= minimum edge to edge spacing of adjacent n wells.
 Active area
• Silicon devices are built on active areas of the
substrate.
• Active area is flat and provides access to the top
of the silicon wafer.

• Wa = Minimum width of an active feature.

• Sa-a= minimum edge to edge spacing of active
mask polygon.
• FOX = NOT (Active)
 Doped silicon regions
• To create n+ and p+ regions. These are known as ndiff and pdiff respectively.
• Thermal technique called diffusion is used instead of implantation.
• n+ regions are by ion implanting arsenic or phosphorous ions in to the
substrate in areas selected by the n-select mask. This process is done after the
isolation process.
• n+=(n select)ᴒ(active)
• Wa = Minimum width of an active area.
• Sa-a= minimum active to n select spacing.

• P+ region are by ion implanting Boron

• p+=(p select)ᴒ(active)ᴒ(nwell)
• Wa = Minimum active area width.
• Sa-a= minimum active to p select spacing.
 MOSFETs
• MOSFET structure exist every time a poly gate line completely crosses an n+ or p+ region.
Poly line is deposited before the ion implantation and adds to block do pants from entering
the silicon.

• L= Wp = minimum poly width

• Sp-p = minimum poly to poly spacing
• dpo=minimum extension of poly beyond active.

• The minimum poly line width is the same as the drawn channel length for a FET.
• Gate overhang distance: dpo is required to insure the formation of the self aligned FET if a
small registration error occurs in the lithography.
• n-FET =(n-select) ᴒ(active)ᴒ(poly) this is where channel is formed.
 P-MOSFETs
• Cross-section view and layout view of P-MOSETS

• pFET= (pSelect) ᴒ (Active) ᴒ (Poly) ᴒ (nWell)

• p+=(pSelect) ᴒ (Active) ᴒ (nWell) ᴒ (NOT [Poly] )
 Drawn and effective dimensions of a
MOSFET
• Critical dimensions are the channel length L and
width W.
• The physical length is small than L due to lateral doping during the implant
annealing step.
• Leff: electrical or effective channel length
• Lo: overlap distance on both sides
• Leff= L –2Lo
• Leff= L –ΔL
• The channel width is also small than the drawn value due to reduction of active
area by the field oxide growth.
• Weff= W –ΔW
 Active contacts
• An active contact is a cut in the Ox1 that allows the first layer of metal1 to contact an
active n+ or p+ region.

• Sa-ac= minimum spacing between Active and Active Contact

• dac, v= vertical size of the contact
• dac, h= horizontal size of the contact

• A square contact is obtained if, however, it is not uncommon to have aspect rations
other than 1:1
• dac, v= dac, h= dac
 Metal1
• Metal1 is applied to the wafer after the OX1. Metal1 is used as interconnect for signals
and power supply distribution.
• Wm1= minimum width of a Metal1 line
• Sm1-ac= minimum spacing from Metal1 to Active Contact.

• First layer metal line with an active contact to an n+ region. The contact cut through the
oxide has been filled with a plug.
• Wm1= minimum width of a Metal1 line
• Sm1-ac= minimum spacing from Metal1 to Active Contact
• Every contact is characterised by a resistance
• Rc=contact resistance Ω

• Since the contacts are all in parallel, the effective resistance of the Metal1-Active
connection with N contacts is reduced to
• Metal1 allows access to the active regions of MOSFETs using the Active Contact
oxide cut.
• Sp-ac= minimum spacing from Poly to Active Contact
• Sa-p= minimum spacing from Active to Poly

• A Poly Contact mask is used to allow electrical connections between Metal1 and the
Polysilicon gate
• A pair of series-connected FETs sharing the central n+ region
• Sp-p= minimum Poly-to-Poly spacing
 Parallel-connected FETs
• Sg-g= dac+ 2Sp-ac
• the size of the contact itself, plus two units of poly-active spacing
 Vias and Higher Level Metals
• CMOS processes add several additional layers of
metal that can be used for signal and power
distribution

dv= dimension of a Via (may be different for vertical direction)

wm2= minimum width of Metal2 feature
sm2-m2= minimum spacing between adjacent Metal2 features
sv-m1= minimum spacing between Via and Metal1 edges
Sv-m2= minimum spacing between Via and Metal2 edges
 Latch up prevention
• Latch up is a condition that can occur in a circuit
fabricated in a bulk CMOS technology.
• When a chip in a state of latch-up it draws a
larger current from the power supply but
doesn’t function in response to input stimuli.
• The state of latch-up operation is restored by
removing and reconnecting the power supply.
• Worst-case situation, the chip may enter latch-
up when power is applied and never be
functional . If the current flow is too large, heat
dissipation will destroy the die.
 Latch-up current flow path
• The path has very low resistance and allows
larger currents to flow.
• It is a 4 layer pnpn structure between power
supply and ground.
 Latch up prevention
• It starts with the physical design level with various rules used to avoid the
formation of the current flow path.
• Since the current flows through the n-well and the p-well substrate , place
VDD and ground at different points.
• Include an n-well contact every time a PFET is connected to the power
supply VDD, and4
• Include a p-substrate contact every time an n-FET is connected to ground
rail.
• Twin tub technologies are popular in advanced processing lines.
Design rules for nmos and pmos
Design rules for transistors and gate
over hang distance
lambda based design rules
 Cell-based Concept
• The basic building blocks in physical design are
called CELLS.
• A cell may be simple as FET or complex as ALU.
 Creation of new cell using basic units
• The expression f can be created with the
cascade of two NOT gates and one NAND2 gate.
 VDD & VSS power supply lines

• Power supply lines placement

Dm1-m1 = Edge-to-Edge distance between VDD and VSS

Pm1-m1 = Distance between the middle of the VDD and VSS lines
The two are related by, where WDD is the width of the power supply lines
Pm1-m1 =Dm1-m1 + WDD
 Two approaches to place FETs:
Horizontal and Vertical direction
MOSFET orientation
• The value of X2 is greater than X1 for a given circuit.
• Interconnect routing are also an important consideration for the
VDD and VSS spacing. The wiring is often more complicated
than designing the transistor arrays.
• Approach to this problem is to place rows of logic cells in
parallel and allocate space in between the rows of wiring.
• Since Metal2 lines can cross over Metal1, vertical lines can be
used to connect logic cells to METAL 1 interconnect as shown
 Weinberger image
• The inverted logic cells are defined to be flipped in relation to the rows of logic cells above or
below.
• This is because they have VDD at the top and VSS at the bottom.
• The n-FETs are placed on both the sides of VSS line. Since no spacing is automatically reserved for
wiring. .
• Drawback: must use Metal2 or higher metal layer to achieve this approach
 Port placement
• The input and output ports of a cell must be
placed at conventional points to facilitate the
interconnect wiring.
• FET gates are at the polysilicon level a poly
contact to connect the output of a cell to the input
of another cell.
 FET sizing and Unit transistor
• FET are specified by the aspect ratio (W/L)
• Combine with the processing parameters to
give the electrical characteristic of the
transistor Given the gate area by AG = LW