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VLSI DESIGN ISSUES

Design Process
 It is a Sequence of steps to design a chip with constraints like size, area,
power and delay

 As the complexity increases, the design flow and verification is tedious

 Hence CAD tools are used

Tasks in chip design:

i. Design: It starts with the description of the system

a. Behavioral Domain: Specifies the hardware functionality

b. Structural Domain: Refers to a set of sub-modules connected together

c. Physical Domain: Specifies the layout used to build the system

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Design Process
ii. Verification: Verification is done to verify the functionality of a chip. It is
done at two levels higher level(register transfer level) and lower
level(transistor level)

iii. Implementation: After verification, the design is realized onto the

hardware

iv. Software Development: The verified design, with necessary hardware

components is converted into a stream of bits to program onto the target
device

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Design for Testability
 Testing is a process of verification

 When a known input is applied to a unit, a known

output is evaluated

 Test vectors are generated for the design test

Defects : They are problems that occur in silicon. It

indicates a physical failure of the chip

i. Processing defects: VDD or Vss shorts, gate-

oxide short/open, process or mask errors

ii. Material defects: Surface impurities, crystal

breakdown etc.

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Design for Testability
Fault: It is the defect in circuit behavior
Reasons for a Fault:
i. Imperfect connections

ii. Poor insulation, grounding or shorting

Types of Faults:
i. Undetected
ii. Detected

iii. Blocked

iv. Tied

v. Redundant

vi. Untestable

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Design for Testability
 Fault model :A fault model is used to detect the fault a circuit

Different Fault models:

i. Single stuck-at faults

ii. Transistor open and short faults

iii. Memory faults

iv. Functional faults

v. Delay faults

vi. Analog faults

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Fault coverage
 Fault coverage is a measure to detect the percentage of
faults by the applied test vectors. Testing involves the
detection of all the faults in a DUT. Performance of testing
process is measured by the percentage of fault coverage.

 For example, if a fault coverage is 100%, then the test process

and test vectors detect all the possible faults in DUT. In other
words, fault coverage gives the measure of goodness of the
test programs. The major issue of design for test is to improve
the percentage of fault coverage.
Single Stuck-at Fault Model

 It is a fault model used to detect faults in digital

circuits.

 S-a-1

 S-a-0

 It depends on number of wires

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Technology Options
 After synthesis and verification, the next step is fabrication onto silicon chip

Two options for fabrication of chip:

i. Full-custom design

ii. Semi-custom design

Note:Logic synthesis is the process of converting a high-level description

of design into an optimized gate-level representation.
Logic synthesis uses a standard cell library which have simple cells, such
as basic logic gates like and, or, and nor, or macro cells, such as adder,
muxes, memory, and flip-flops.

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Full-custom design
Advantages:

i. High performance can be achieved

ii. Minimum area can be achieved

iii. Maximum speed can be achieved

Disadvantages:

i. Requires great number of staff and labor

ii. High cost and long time to market

iii. High cost to design

iv. Long time for verification

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Semi-Custom design

 Part of the design is fixed with standard logic and used in other designs

Classification of Semi-Custom Design

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Semi-Custom design
Advantages of cell-based design:

i. It minimizes the design effort time due to reusable property

ii. Pre-designed cells reduce the complexity of the circuit

Disadvantages of cell-based design:

i. Fixed logic elements in library

ii. It reduces the possibility of 100% designer’s choice based on objects

iii. Fan-out and fan-in are not known in advance

iv. The complete process of fabrication is required which leads to delay in

introducing into the market

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Categories of cell-based design

1. Standard Cell-Based Design:

 Logic cells are placed in rows with same height, but different widths
 The cells placed in rows, are connected with routing channels
 Cells may be different size(due to variation in fan-in)
2. Complied Cell-Based Design
 Designer has a choice of customizing and optimizing the cells
 Software tools are used to generate the cells
3. Macro Cell-Based Design
 Macro cells are pre-designed complex designs
 Eg: Multipliers, data paths, memories, DSPs etc

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 Array-Based Designs
Advantages:

i. It is alternative of Cell-based designs

ii. Dedicated process is avoided(reduces non-recurring engineering

cost)

Categories of Array-Based Designs:

i. Pre-diffused

ii. Pre-wired

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Array-Based Designs
i. Pre-diffused:

a. Array of primitive cells or transistors are manufactured by vendors

b. Fabrication steps for primitive cells are standardized

c. Desired connections are added with few metallization steps

d. Eg: Mask Programmable Gate Arrays

ii. Pre-wired:

a. All primitive cells are provided but manufacturing process is separated

from implementation phase (which is performed at user’s side)

b. Eg: FPGA

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 STYLE
Design
constraint Full
Standard Cell Gate Array FPGA
Custom

Compact to
Area Compact Moderate Large
Moderate

Performance High High to Moderate Moderate Low

Fabricate All Layers All Layers Routing None

Power Calculations
 Total power = static power + dynamic power

i. Static power/ leakage power: It is consumed when the logic circuit is in

quiescent or idle state. Sources are Leakage currents due to sub-threshold
and reverse biased pn-junction at diffusion regions and substrate.

ii. Dynamic power: It is consumed due to signal transitions(from 0→1 or

1→0) in the circuit

Types of signal transitions:

i. Functional transitions ( transitions necessary to perform logic functions)

ii. Spurious transitions/ glitch(unnecessary transitions due to unbalanced

path delays)

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Power Calculations

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Package Selection

Multiple stacked die

system in package (SiP)

System on chip (SOC)

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Clock Mechanisms

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Clock skew:
Mixed Signal Design
Mixed Signal Design

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