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An all-MOS charge-redistribution A/D conversion technique

Conference Paper · March 1974

DOI: 10.1109/ISSCC.1974.1155344 · Source: IEEE Xplore

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3 authors, including:

Paul R Gray David Hodges

University of California, Berkeley University of California, Berkeley
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SESSION XVI: A/D and D/A Techniques

FAM 16.4: An All-MOS Charge-RedistributionA/D Conversion Technique*

Ricardo E. Suarez, Paul R. Gray and David A. Hodges

University of California

Berkeley, Cai.

THE HIGH COST of the analog-digital conversion function has of dividing the existing charge on C1 by two and adding a charge
impeded the application of digital processing of analog signals in of
cost-sensitive areas such as automotive and consumer electronic bn VREF
control
systems.The
simultaneous requirement in
classical
approaches for high-performance analog circuitry, such as 2
operational amplifiers, and digital circuitry forcounting, se- so that for an n-bit D/A conversion
quencing,anddatastoragehastended to result in hybrid
approaches - one or more bipolar analog chips and an RlOS chip
bn2 ~ v R E F
to economically perform the digital functions’.
Trout =
c
In thispaper anall-MOS charge-redistributionconversion n-0 2N
technique realizable witha single low-cost “ I S chip willbe
described. In contrast to earlier charge redistribution converters,* which is the desired output.
no operational amplifiers and only two grounded capacitors are With theaddition of a voltage comparatorandsequencing
required.Thetechnique is based on the serial D/A converter logic the serial D/Aconvertercan beused to constructa
shown inFigure 1. The conversionbeginswith both capacitors successive-approximation A/D converter as shown inFigure 2.
discharged and is accomplished serially by considering the least In contrast to the D/A conversion, the Most Significant Bit (MSB)
significant bit b o first. If thisbit is one;
a S2 is closed must be determined first for A/D. The control logic takes on a
momentarilycharging C 2 to VREF; if it is azero, C2 is left particularly simple form since the DAC input string at any given
discharged. Switch S1 is then closed momentarily giving a point in the conversion is just the previously encoded word LSB
voltage Vout of first. For example, consider a point during the A/D conversion in
which the k most significant bits have been decided. To decide
the ( k + l ) t h bit, a(kt1) bitD/A conversion is carried out assuming
Vout = [bo VREF
T I the bit under consideration is a I . If the bit should indeed have
beenazero, the D/A output voltage will exceed the analog
Leaving the charge on C1, the precharging of C2 is repeated, this voltage being encoded, and this will be indicated by the compara-
timcconsideringthenextleastsignificant bit b1.After re- tor. The correct valueof the bit is stored,andthenext serial
distribution, the output voltage is D/A is started. Since the D/A conversion for the kth bit requires
k rcdistributions, the total number of redistributions required for
an M-bit A/D conversion is M(M+l).
bo VREF b l VREF
Vout = ___ + ~
The principal factors limiting the linearity of this technique
4 2 are theerrorchargescoupled onto C 1 and C2by theswitch
parasitics, the capacitormatching
and
the
capacitor
non-
This repetitive procedure has the effect as the nth redistribution linearity.Thecffect of comparatoroffsetisminimized by an
offset cancellation circuit.
Theerror charge transferred tothecapacitors C 1 and C2
throughtheswitchcapacitancesduringswitchtransitionsin
effect places a lower limit on the capacitor size that can be used
*This work was supported in part by the National Science
Foundation Grant GK-40912. while achieving a specified accuracy. This in turn places a limit
‘Schoeff. J. A.. “A Monolithic Analog Subsvstem for High- on the speed with which the redistribution can take place, and
AccuracyAIDConversion”. I S S C C D I G E S T OF T E C H N I C A L hence the overall converter speed. While this design tradeoff can
P A P E R S , p. 18-19; Feb., 1973. be cased by the use of charge cancellation techniques as described
‘Schmidt, H.. “Analog Digital Conversions”, Van Nostrand- later, it is a fundamental factor limiting speed.
Reinholt; 1970.
The properties of the integrated capacitors C1 and C2 have a
’Poujors, R., et ai., “Low Level MOS Transistor Amplifed
Using StorageTechniques”, ISSCC D I G E S T OF T E C H N I C A L strong effecto n the performance of the converter. Because of the
P A P E R S , p. 152-153; Feb., 1973. freedom to choose an optimum shape factor, mask-edge-induced
mismatches between MOS capacitor pairs is significantly smaller logic are required; in a complete NMOS realization this amount
than those for diffused resistorsof practical value and comparable of logicrequires less dieareathantheanalogportion of the
physical size. Experimental results from 25 pF round MOS dots circuit. A schematic of themonolithicanalogportion of the
on N+ substratesindicatethat50thpercentilemismatch of prototype circuit is shown in Figure 3. Charge-cancelling devices
.06 per cent is achievable with this size capacitor; mismatches Q5 and 46 serve t o cancel partially the error charge transferred
fromthis
source are inversely dependent on device size. onto the capacitorsby the switch transistorsQ1, Q3, and Q4;the
Capacitance linearity is dependent on the surface concentration waveform applied to the gates is the complement of that applied
in the MOS structure; it was found experimentally that surface to the gates of the switch transistors. The voltage comparator
concentrationsontheorder of 1020cm-3wererequired to utilizesanoffsetcancellationscheme3 which simultaneously
achieve thelinearityrequiredforan8-bitconverter.Inthe provides a level shifting function. Prior to the conversion, the
prototype circuit, a P+ channel stop diffusion is used to form two inputs of the comparator are shorted together by 433, and
thebackplate of thepolycrystalline-silicon-Si02 - silicon switches 4 3 0 and 431 are closed. Capacitors C3 and C4 then
capacitor. charge to the common mode voltage plus a difference voltage
The feasibility of this conversion technique was investigated equal to the first stage input offset voltage multiplied by the
by the design andfabrication of aprototype8-bitconverter first stage gain. Upon turnoff of 430, 431, and Q32, the input
shownschematicallyinFigure 2. Thecritical analog circuitry referred offset then becomes the second stage offset divided by
shown within the dotted lines was fabricated as an N-channel the first stage gain. The stability problem inherent in feedback
silicon-gate MOS integratedcircuit, while theremaining logic correction schemes using multistage MOS amplifiers is avoided.
was performed with TTL. Fortybits of registerandassorted A die photois shown in Figure4.

PARALLEL
DATA OUT

0 TEMPORARY STORAGE
SHIFTREGISTER

SHIFT
'REFERENCE I SERIAL
DAC
sz CONTROL ( vII) 1 DAc STORAGE
RIGHT
*
I S3 CONTROL ( V I O )
REGISTER

! IS1 CONTROL ( V I * )
I
PARALLEL
XFER
DATA
SHIFT
LEFT

STATUS I
CI = c 2 LOGIC START
S E P U E N C E 8 CONTROL

FIGURE 1-Serial charge-redistribution

digital-to-analog
converter. FIGURE 2-Complete analog-digital converter.

-0
I>
-
+-No 0
= s FqgJ 9 I*

vss ( - 5 V )
FIGURE 3 4 i r c u i t schematic of monolithic DAC and voltage comparator.

[See page 248 for Figure 4.1

 FIGURE 4-Photomicrograph of experimental die containing
the circuitry of Figure 3.

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