CARLETON UNIVERSITY

Department of Electronics
ELEC-3500 Digital Electronics September 12, 2006

Lab 1 : MOSFET Switches

1. Design and Specification of MOSFET Devices

Digital circuits are implemented by arranging switches (typically Billions of them) together into logical net-
works. Today, metal-oxide field effect transistors (MOSFETs) are the most common way to implement these
switches due to their ease of manufacture and high density. To implement logic networks, we typically use 2
types of switches. One that conducts with a “1” input, and one that conducts with a “0” input. These can be
made with NMOS and PMOS transistors respectively.

Active High Active Low

“1” “0”
Turns on when a “1” Turns on when a “0”
is applied to the control. is applied to the control.

0V
2.5V
NMOS PMOS

But... for the switch to work, there must be a strong voltage difference from the gate to one of the terminals.

STRONG 2.5V STRONG 0V

??? ???
0V 2.5V
Vgs=2.5V >> Vth: switch conducts well |Vgs|=2.5V >> Vth: switch conducts well

2.5V STRONG 0V STRONG

??? 0V ??? 2.5V
Vgs=2.5V >> Vth: switch conducts well |Vgs|=2.5V >> Vth: switch conducts well

weak 2.5V weak 0V

1V >1V 1.5V <1.5V

Vgs=1.5V > Vth: switch conducts poorly |Vgs|=1.5V > Vth: switch conducts poorly

2.5V 0V

2.2V >2.2V 0.3V <0.3V

X X
Vgs=0.3V < Vth: switch does not conduct |Vgs|=0.3V < Vth: switch does not conduct

ELEC 3500 DIGITAL ELECTRONICS page 1 of 4

Carleton University ELEC 3500, Lab 1 : MOSFET Switches Transistors as Switches, Transistor Pulling Down

In this lab, you will modify some MOS- Pull Down +2.5V Pull Up
FET based circuits, and simulate their use as +2.5V
switches.

1.1 Transistors as Switches VOUT

VOUT
Digital gates are made from switches. FIGURE
2.1 shows four types of switch connections. We +2.5V
will look at how to use MOS transistors in each Transmission (Pass) Gate
type of connection.

a) PMOS and NMOS as pull down switches. VOUT

VOUT
b) PMOS and NMOS as pull up switches.

Complimentary Symmetry FIGURE 2.1

1.2 NMOS transistors. NMOS transistor at ground
VOUT(MIN)
+2.5V=VDD 2.5 V
1.2.1 Transistor Pulling Down
R
To use transistors in digital cir-
cuits one must know how to con- output
nect them to get the full 0V to ID 0.1 1.25
2.5V output swing
G pF
Here, with the NMOS gate at VOUT
2.5V =VDS
2.5V, and the source at 0V, Vgs is S
large and so the transistor is VGS
FIGURE 2.2 0 R
strongly conducting. 103 104 105 106

Q1. Simulate the circuit in Figure 2.2 to find the lowest output voltage Vout (min) with different values of
R. (Try R=10 kOhm, R=25 kOhm, 50kOhm, 200kOhm, 1000 kOhm)
a) Plot the observations of Vout min versus R.
b) What is the delay from Vin rising to 1.25V to Vout falling to 1.25V with R = 200 kOhm
b) Considering how fast the output would take to charge and discharge (which is normally very im-
portant in digital circuits), what is the disadvantage of making R very high (eg. 1000 kOhm)?

The 0.1pF capacitor is stray circuit capacitance. Many MOS circuits have only stray capacitance (no re-
sistors) in them, particularly if they feed only other MOS circuits.
Q2. a) With R= 1 kOhm, using simulations plot Id versus VGS.
b) Is there a sharply-defined threshold voltage, above which the transistor starts conducting?
c) From your plot, make an estimate for this value. How confident are you (eg. +- 1%, +-10%, +-
50%)?

Q3. With R =200 kOhm, L = 1 um, sweep W (the width of the transistor) from 1um to 10um (at least 4
points), and for each value measure the delay from Vin rising to 1.25V --> Vout falling to 1.25. Plot
the simulation sweep, and plot the measurement results for your report.

Department of Electronics September 12, 2006 page 2, of 4

Carleton University ELEC 3500, Lab 1 : MOSFET Switches NMOS transistors., Transistor at Top End (VDDEnd) Of

FIGURE 2.3
VG-S ≥ VTHRESH ≈0.5V
+2.5 V NMOS
VDD NMOS
+2.5 V

OUTPUT RANGE
DRAIN

OUTPUT RANGE
VD ≈ 0 G
VG =2.5V S
G
DRAIN VS ≤ 2V
S ≈ 0.5V Min
VG-S = 2.5V R

R
NMOS pulls-down to Ground NMOS only pulls-up to VDD - VTHRESH

Q4. Keep R = 200 kOhm, W = 1 um, sweep L (the length of the transistor) from 1um to 10um (at least 4
points), and for each value measure the delay from Vin rising to 1.25V --> Vout falling to 1.25. Plot
the simulation sweep, and plot the measurement results for your report.

1.2.2 Transistor at Top End (VDDEnd) Of Circuit.

Now consider the NMOS transistor connected at the top of instead of the bottom (FIGURE 2.4). With
the gate at 2.5V, the transistor is turned on, so one would expect VOUT to be close to 2.5V. But is it real-
ly that close?
The Threshold Voltage
The MOS transistors used in gates have a minimum VGS to turn on called VTH (threshold voltage). Typ-
ically VTH is 0.4 to 0.8V. Even at VGS = VTH conduction is poor. One needs a voltage many times higher
to give a low channel resistance. FIGURE 2.3 shows how even with VG=2.5V, VGS can be much small-
er. Further the pull-up connection can never have an output above VDD-VTH.
The MORAL:
To STRONGLY turn on an NMOS transistor, we want a full strength control voltage (i.e. 2.5V) from the
gate to one of its other terminals (source or drain). In a ‘normal’ digital circuit (Figure 2.2), the NMOS
source is always grounded (at 0V) and so when it is turned ON, the full 2.5V is always across the transis-
tor and it has a lot of ‘ummph!’. If the transistor is connected as in Figure 2.3b, then Vgd = 0 (absolutely
no ‘ummph’ on that side) and as the output charges, Vgs will vary between 2.5V (lots of ‘ummph!’) to
Vth (no ummph).
Q5. Run simulations of the circuit in Figure 2.4 for different values of R, and
a) find the maxiumum value of the output voltage(s), plotting them on a curve of Vout(MAX) vs R.
b) From this plot, what do you estimate the threshold voltage of the NMOS to be?
You should find the output
NMOS, transistor at top VOUT(MAX)
(Source) can never rise 2.5 V
closer than VTHRESHOLD . +2.5 V

Q6. Comment: Would you G VDS

think digital circuits 2.5V
S output 1.25
would perform better VGS
when NMOS transistors 0.1
were connected to pull R pF
VOUT
the output up or down?
FIGURE 2.4 0 R
102 103 104 105 106 107

Department of Electronics September 12, 2006 page 3, of 4

Carleton University ELEC 3500, Lab 1 : MOSFET Switches PMOS transistors, Pulling Down with a PMOS

1.3 PMOS transistors PMOS; transistor pulls down. VOUT(MIN)

2.5 V
Just like NMOS transistors that wanted a full +2.5 V
control swing to turn ON with a lot of ‘ummph!’, R
PMOS transistors are the same way. They turn on
when the gate is at a LOWER voltage compared to output 1.25
either of the source or drain terminals. The stronger VGS 0.1
this (-ve) voltage swing is, the lower the ‘ON’ re-
sistance and the better the switch. 2.5V V pF
G OUT
0V =|VDS|
Another thing to keep in mind is that due to 0
D
the chemistry of things, PMOS transistors are 2-3x FIGURE 2.5 102 103 104 105 106 107
slower than NMOS ones.

1.3.1 Pulling Down with a PMOS

Q7. Simulate the circuit of Figure 2.5 to find VOUT for a range of R.
a) Plot the graph Vout min versus R.
b) How close can VOUT get to 0V?
c) Estimate the threshold voltage of the PMOS transistor from this.

1.3.2 PMOS Transistor Pulling Up

Q8. Simulate the circuit of Figure 2.6 to plot VOUT max vs R, particularly find the maximum VOUT.
Q9. Comment: Would you think digital circuits would perform better when PMOS transistors were con-
nected to pull the output up or down?
Q10. a) For R=200 kOhm, calculate the de- PMOS; transistor pulls up VOUT(MAX)
lay from Vin falling to 1.25V --> vout 2.5 V
rising to 1.25V. Include this plot in +2.5 V
your report. VGS
S
b) How does this compare to the delay G |VDS|
0V
of the NMOS? (Refer to Q3) 1.25
D output
VOUT 0.1
R
pF

0
FIGURE 2.6 102 103 104 105 106 107

Deliverables:
• Print and Fill out a cover sheet.
• Show your completed work to a TA at the end of your section and Get signed.
• Answer all the questions and submit it with supporting printouts (Only answer the ques-
tions. This report does not need introduction, conclusion etc)
• Attach your signed coversheet as the first page of your report.

Department of Electronics September 12, 2006 page 4, of 4