Chapter 3: Methodology

This chapter is organized as methodology discussed that enables the

integrated design for a 16-bit Sigma-delta Analog to Digital Converter that will
implement in 45nm CMOS process for low power applications. The diagram below
shows the working outline of activities of the present study for the accomplishment of
the project.

Figure 3.1 Research Methodology

In designing of Sigma Delta ADC, the first thing to do is to learn how the whole
system works by gathering information/concepts and formulas in designing of blocks.
Next, Make a design plan in every blocks. The target parameters is identified and topology
for every blocks is picked based upon the specifications. Then, the next action is the
designing and testing of the design in cadence. If the result of the test doesn’t meet the
target specification then, redesign and test the system until the target specification is met.
 The group makes a research about the related literature of the sigma delta ADC.
All related theories and topologies collected are studied. The results of every topologies
are checked and are analyzed in a way that we can find the each merit of the
approaches. Thus, we can choose the best topology which is capable to satisfy the
needed specification of the design.

3.1 Overview of Operations

Sigma-Delta Analog to Digital Converter architecture is ideal for converting

analog signals to digital output with large frequency and high resolution results. The
Sigma Delta ADC is fundamentally composes by an internal modulator (Sigma – Delta
Modulator) and a digital Filter.

Figure 3.1.1 The 2 major blocks in Sigma Delta ADC, Sigma Delta Modulator and Digital
Decimator and filter

Delta Sigma Converter collects sample form the input by oversampling and this
outputs a stream of 1 bit data. This are made possible by making use of a fast sampler.
Sigma delta modulator gets its name ‘delta’ from the fact that it measures the difference
between the input signal and the feedback signal by the DAC. The “delta” is used to
present the small change incrementally or small deviation known as “delta modulation”.
Delta modulation depends on quantization change in the signal in every sample that has
been took. “Sigma” or the integration part is taken at the input side of ADC and output
side of DAC. Thus, this type of modulation is called as sigma delta modulation.

Figure 3.1.2 In a frequency-domain representation, the noise characteristic is key to the

modulator’s frequency operation

SD modulator is the building block of sigma delta ADC that the analog input
signal pass through. It is the analog part of SD ADC, the number of bits/ resolution of
the ADC is determined by the modulator’s order. Modulator’s order is affected of the
sampling ratio. So that to tune the order of the modulator, sampling ratio is being set.
SD Modulator is composed of an integrator and a comparator which is placed in the
forward path and the n bit DAC which is placed in the feedback path.

The integrator measures the analog voltage output from the modulator and gives
a signal to the n bit ADC. Next, the output of the integrator is converted into digital zero
or one by the n bit ADC through the use of the system clock. The output of the ADC will
be feedback through a n Bit DAC.
 Then, the feedback signal that came from the output of DAC goes to the
summing amplifier, then the input signal is subtracted to the feedback signal of DAC.
Next, the low pass filter integrator filtered out the error signal. The comparator there is
used as the quantifier at oversampling clock frequency. The input signal is compared
with the last sampled signal to tell if the signal is larger than the reference or not. If it is
higher than the previous sample then the output is increased else decreased. The
thickness of pulses shows the value of the input in average. It represents that most of
the pulses are 1s for the positive peak and the negatives pulses are 0s for the negative
peak of the signal. It makes the digital representation of the input analog signal.

The sigma-delta modulator can have high resolution by the technique of noise
shaping where the noise is pushed to a higher frequency which is out of the frequency
band of interest, where it is filtered out soon by the digital decimator and filter

3.2 Circuit Design

3.2.1. Design Considerations

The following are the considerations the researcher used as guide in

designing the Sigma Delta ADC

a. Power

The Proposed Sigma- Delta ADC should consume only

less than 1 mW of power. Some considerations to
achieve this is the speed of the Sigma-Delta ADC, and its
resolution.
 b. Speed

The Proposed Sigma- Delta ADC should be able to

process signals up to 500 kHz. Sigma Delta ADC works
by the principle of oversampling so if the input signal let
say is 500 kHz then the sampling frequency would be lot
larger.

c. Resolution

Sigma Delta ADC are known for its high resolution among
other ADC because of oversampling and noise shaping
technique.

3.2.2. System Level Specification

3.2.2.1. Specifications

The Sigma Delta ADC aims the following specifications shows in table
3.2.2.2.1

Table 3.2.2.2.1 Specifications

PARAMETERS VALUE
Resolution 16 Bits
Power Consumption less than 1 mW
Input Bandwidth at least 500 kHz
Differential Non-linearity (DNL) 1 LSB
Integral Non-linearity (INL) 1 LSB
Voltage Supply 1V
3.2.3. Block Level Requirement

After considering the system level requirement set by the proponents, the
requirements for each block was determined based on the different architectures
discussed in the chapter 2 of this paper.

This part of the study focused in setting the appropriate specifications that
is needed in designing each block of the SD ADC. All information gathered were
weighed and analyzed according to the parameters that affect the energy
efficiency and power consumption of each block. This should be reflected in
characterizing the transistor level of each block. This was essential in stimulating
the circuit design regarding its DC and AC properties. The process of designing
the Sigma delta ADC needs a systematic and well planned procedure and
involves the right use of time and effort in order to come up with the design that
complies with the given specifications. Techniques and risk consideration for
every block was identified properly.

3.2.3.1 Modulator requirement

Since modulator responsible for converting analog signal

into digital. The general consideration for designing are power
dissipation, integral nonlinearity, sampling rate, Differential
nonlinearity, order of modulator and resolution. Since the resolution
is affected by the order modulator, over sampling ratio then
balancing of the three parameter can make the system be low
powered

3.2.3.1.1 Integrator

The subtractor has only one topology. So that, what we can

innovate is Operational Amplifier used which has many topology
such as Miller OTA, telescopic, Folded Cascode, Multi stage
 architectures. The topology would be chosen defends upon the
target specifications and power requirement.

3.2.3.1.2 Subtractor

The subtractor performance relies on the Operational

amplifier of subtractor. So that, what we can innovate is Operational
Amplifier used which has many topology such as Miller OTA,
telescopic, Folded Cascode, Multi stage architectures. The
topology would be chosen defends upon the target specifications
and power requirement.

3.2.3.1.3 n-bit ADC

The n bit ADC is the core of the modulator. The conversion

of analog to digital is happening on this block so this block should
be designed properly so as to meet the specifications of the
modulator. One requirement is its resolution the higher the
resolution the higher SNR for a given modulator order. It should be
design also to be power efficient so that the main objective of this
study can be achieved.

3.2.3.1.4 n-bit DAC

The n-bit DAC serves as a feedback for the sigma delta ADC.
One of the requirements that it should meet is linearity, for a 1 bit
DAC the analog output voltage is just merely the +vref or –vref while
in n bit DAC there are more possible outputs. That’s why linearity
becomes a problem to a n bit DAC.

3.2.3.2 Decimator

3.2.3.2.1 Digital filter and Decimator

 The digital filter will filter the streams of bits of 1’s and 0’s
from the modulator. Here the downsampling will also be done to
reduce the frequency of the data output and to increase the word
length to target resolution.

3.2.4. Block Level Consideration

The sigma delta analog to digital converter architecture has several factors to
consider. Such factors are order of ADC modulator limits, the digital filter function,
decimator filter function, the compatibility of the parts of ADC to pull together and the
specifications relation.

3.2.3.1 MODULATOR

Figure 3.2.3.1.1 Block diagram of 1 bit SD modulator

The modulator consists of a Difference Amplifier, integrator, and n-bit

Quantizer (ADC) and a 1bit DAC. Figure 3.5 shows the basic structure of a modulator.
The total power of the sub blocks of the modulator should be equal or less than 0.5 mW.
3.2.3.1.1. Subtractor (Delta)

a. Input offset voltage- The input voltage is connected directly to the

Subtractor so the input offset of these should be minimal as
possible.

b. Linearity- The Subtractor is intended to function as linear

difference of the inputs and non-linearities would surely degrades
its function

c. Speed- the subtractor should be fast enough so that the

frequency due to oversampling will be possible.

3.2.3.1.2. Integrator (Sigma)

a. Input offset voltage-should be minimal as possible.

b. Gain Bandwidth Product –the gain bandwidth product should be

large as to accommodate the high signal frequency.

3.2.3.1.3. N bit ADC

a. Power Consumption- Since the proposed sigma delta ADC

should have a power consumption of less than 1 mw power
consumption of the Comparator should be relatively low since
there are many other blocks to be powered.

b. INL-It is the maximum deviation from a straight line. It is a

measure of non-linearity so low INL is desirable.

c. DNL-it is the deviation from the ideal value of 1 step which is

equal to 1 LSB. It is expressed in terms of the number of bits
with no missing codes.
 d. Full Scale Range-it is the range of input signal that an ADC can
process. High full scale range is desirable since more values of
input signal can be process without further signal enhancement.

e. Conversion time-the sigma delta adc works on oversampling

therefore each part should be able to cope with high speed
therefore conversion time should be made small as possible.

f. Input Impedance-is is the impedance seen at the input terminal. It

should be high so that the loading effect on the integrator would
be minimal.

g. Resolution- ADC is the core of the sigma delta ADC. Higher

resolution of the ADC or the quantizer can increase the overall
performance per given power and modulator order, also higher
resolution decreases the idle tone behavior of a 1 bit ADC.

3.2.3.1.4. N- Bit- DAC

a. Switching speed - The most stringent requirement for the 1-Bit

DAC is the switching capabilities. It should be able to respond
to the sampling frequency which is OSR*nyquist rate.

b. Input Impedance- The input to N-Bit ADC is from the the N bit
ADC which is clocked at high frequency so it should have high
input impedance.

c. Resolution - the resolution of the DAC would be determined by

the number of bits of the ADC . Number of bits of the DAC is
equal to the resolution of the ADC
 d. Power-since the main objective is to design an ultra low power
sigma delta ADC its imperative that each sublocks would have
least power consumption.

e. Linearity- INL and DNL will measure the nonlinearity of the

DAC. As the resolution of DAC increases the linearity also
worsens so proper designing is needed so as to keep the DAC
linearity within the limits.

3.2.3.2. DECIMATOR

The process of converting the sampling rate to a lower rate is called Decimation.
Decimation means reducing by a factor 10. But in communication it is the reduction in
the sampling rate of the signal. It is a digital low pass filter which performs the samples
rate reduction operation.

3.2.4.2. Digital Decimator and filter

3.2.4.1.1. Decimation Ratio- it is the ratio of how slow the output of

the decimator data compared to its input.

3.2.4.1.2. Power-as technology evolves power consumption is

getting smaller so as to provide longer battery life, but
decreasing the power has some consequences specially
in performance and in area. To have a decent
performance on a low power area is sacrificed so proper
design is needed so as to weight out things properly.
 3.2.4.1.3. Ripple Pass Band- it is the amount of ripple on the pass band.
The least ripple pass band is preferable

3.2.4.1.4. Attenuation- it is the amount of how well the filter attenuates

the signal out of the frequency band of interest. In layman’s
term it is how well the unwanted signal is being filtered out.

3.3 Detailed Design

This section will discuss the detailed procedure to design the Sigma Delta
ADC.

From all the data and information gathered from literature review relating to
the design process, the researcher can now have the detailed representation on how
the Sigma Delta ADC would be performed. since it is not a 1 block project integration
is needed for each part so as to see how they perform when they are already
integrated to each other to see whether they meet the expectation or need some fine
adjustment or at worst requires a redesign. This design process will take time which
includes designing, implementation, testing, and reconfirmation of the results. This
design is a mixture of analog and digital design so various software will be used to aid
for the design process these include Cadence, Verilog HDL, Matlab and Simulink.

The step-by-step design procedure that results in the proper Sigma Dela
ADC design are the following.

First know the target specification and requirement of Sigma Delta ADC.
From these specifications and requirement, choose among different available
architecture /topology of sigma Delta ADC that would best fit on it. The primary
objective is ultralow power, therefore the chosen topology should have the least power
consumption. Next determine the sub blocks of the chosen Sigma Delta ADC
topology, these includes the modulator and digital decimator filter.
 For the modulator part model the signal that will be used here, consider the
frequency and amplitude of the signal and noises that might be present. Then
determine the specifications, requirements and considerations of the modulator to be
used in the design process. From here choose the appropriate topology for the
modulator. Also it is not a 1 block design so determine the sub-blocks of the modulator
and define their corresponding specifications, requirements and considerations. After
these start designing the sub-blocks by computing for the necessary parameters.
Consider power dissipation, signal bandwidth, resolution, accuracy, SNR, DR and
Figure of Merit.

For the digital decimator filter model the input signal that this block will receive from
the modulator, which are streams of bits of 1 and 0, model this input that it will have
the frequency of oversampled ratio multiplied to the nyquist frequency of the input
signal. Consider any noise and inaccuracy that might have occur during the
modulation process. Define the specifications, requirements and considerations of
the digital decimator filter, and from these choose the best topology among the
available topology, if needed design your own topology. After a topology is chosen
start designing the digital decimator filter by computing for the necessary parameters
such as downsampling ratio, pass band ripple, stopband attenuation and power
dissipation. Finally integrate the 2 major blocks the modulator and the digital
decimation filter. Then check for the performance using multiple test analyses and
redesign if necessary.

3.4. Circuit Design Specification

The circuit specification of the design will be the ultralow power, high data rate
and high resolution. Different techniques and the best design topology will be
needed in order to achieve this that’s is why each part has methods to be
considered in order to successfully have the design. Methods were taken into
account for the progress of the design. Cadence 45 nm technology and Matlab
Simulink /VHDL will be used to implement the design.
The desired output design will be attained by the use of the Analog Design
Octagon. Every parameter is interrelated to each other. Therefore, if one of the
considerations is change or adjust, the other parameters will be affected in
 accordance to the amount of variations in the circuit. In this design octagon, the
availability of the specifications was the fundamental requisite for the schematic
upon changing one of the parameters in the circuit. Since power dissipation varies
according with the other parameters, then balancing the parameters in accordance
with the target specifications will make the desired output design successfully
achieved.

Figure 3.4.1 Analog Design Octagon

The division of power in the circuit were also considered in the design.
Since the overall power that the design needs to achieve is less than 1 mW, then
the SD modulator and decimator will share the 1mW allowance. The modulator is
the analog part which has more sub-blocks compared to the decimator so that it
will consumed more power. Also, since power is directly proportional to current
which affect the behavior of each electronic component, its value was considered
ensuring that each component works as desired.

3.5 Design Procedure for Delta-Sigma ADC

It is necessary to have a systematic procedure in coming up with the

desired architecture. This part of the study mainly emphasizes the actual design
processes of the project, based on the data and information obtained from the
literature and studies. This process compromises different sub-stages for the
whole circuit design procedure from its step-by-step circuit implementation
including electronic stages. Along this stage is the definition of specifications and
constraints, the selection of proper circuit topology, the computation of
parameters, circuit design implementation, testing and verification.
 The sub-blocks of the sigma delta modulator and decimator are divided to
three as the division of work and will be done by the three designers in the group.
The three designers mentioned will do the three different individual tasks of
designing of blocks and sub-blocks of SD ADC. Task 1 is the design making of
comparator and integrator. Task 2 is the design making of n-bit DAC and n-bit
ADC. Task 3 is the design making of decimator. Each tasks will be separately
study and build by the given designer of that tasks. However, it doesn’t mean that
the designers will not help each other in case of conflict and complication on
working of the design. The designers will still help and do teamwork things
because they are a team. The division of work is for the individual growth of each
designer.
As mentioned before, the designers will do the priority tasks that had given
to them. Those tasks will be checked weekly as progress of the project until the
whole project is finished.
Figure 3.5.1 General Flow Chart for designing the sub-blocks of the Sigma Delta ADC
3.5.1 Defining Specification and Constraints

The Table 3.5.1.1 shows the target specification for Sigma Delta ADC.

Table 3.5.1.1 Target Specifications of Sigma Delta ADC

PARAMETERS VALUE
Resolution 16 Bits
Power Consumption less than 1 mW
Input Bandwidth at least 500 kHz
Differential Non-linearity (DNL) 1 LSB
Integral Non-linearity (INL) 1 LSB
Voltage Supply 1V

The following is the known constraints that will surely encounter by the proponents in
designing of Sigma Delta ADC.

1. Designing of an ultra-low power Sigma-Delta ADC with power consumption of

less than 1 mW.

2. Overcoming the resolution to bandwidth trade-off problem of common Sigma-

Delta ADC that will affect the speed performance of the system

Since the project is not yet finished, then the proponents will probably encounter
more constraints in the near future in the designing of the Sigma Delta ADC.
3.5.2 Selecting Circuit Topology

Every topologies for the Sigma Delta modulator and its subblocks are
examined and analyzed in order to select the initial topology necessary for the design.

Table 3.5.2.1 Selected Topologies

Blocks and *Subblocks Initial Chosen Topology/ Architecture

Sigma Delta Modulator Continuous Time

*Integrator Active RC integrator with Two Stage

Operational Amplifier

*Subtractor Subtractor with Two Stage Operational

Amplifier

*n-bit ADC SAR ADC

*n-bit DAC Resistor String DAC

Decimator and filter Non Recursive Comb Filter

 Sigma Delta modulator
a. Architecture Sigma Delta modulator
Continuous Time Sigma Delta ADC

Table 3.5.2.2 Main differences between CT and DT Sigma Delta ADC

Since the proponents will design a low power SD ADC then, Continuous Time
type of SD ADC is the appropriate to use. Besides that it is low power, Continuous Time
has sampling frequency which is not very sensitive to the amplifier gain bandwidth and
has inherent Anti-aliasing filter.

Figure 3.5.2.1 Continuous Time Sigma Delta ADC

(https://brage.bibsys.no/xmlui/bitstream/handle/11250/2370216/438128_FULLTEXT01.pdf?seq
uence=2)
 b. Loop Filter

Figure 3.5.2.2 CIFB topology

Figure 3.5.2.3 CIFF topology

In CIFF topology,it is only the error signal that is fed to the loop filter.This
signal consists primarily of quantization noise. To suppress the stage’s noise the
first integrator can have large gain. Unlike CIFF topology the CIFB topology fed
the input signal with quantization noise back to every node of the filter that’s why
each integrator has larger swing which leads to higher power consumption.
(Xialong Yuan, 2010).
The Noise Transfer Functions are the same for both topology, however, their
STF are different. The STF of the CIFF topology features first-order filtering
beyond the unity gain frequency fu of the loop while the CIFB topology has L-
order filtering.

Subblocks of Modulator

a. Integrator

For the architecture of integrator, we selected Active RC

Integrator topology. This topology is typically used for continuous time
sigma delta modulator.

Figure 3.5.2.4 Active RC Integrator

Since, the proponents are aiming for ultralow power and high
speed design of Sigma delta ADC, then Two Stage topology is the best
option to use for the operational amplifier inside the integrator as shown
in the table 3.3.
Table 3.3 Performance comparison of various OTAs

Two Stage has the lowest power consumption compared with the other
topologies (Ali Fasli Yoknami, 2010).

b. Subtractor

Figure 3.5.2.5 Subtractor Circuit

Since, the proponents are aiming for ultralow power and high
speed design of Sigma delta ADC, then Two Stage topology is the best
option to use for the operational amplifier inside the subtractor as
shown in the table 3.3.
c. n-bit ADC
Figure 3.11 n-bit SAR ADC

Figure 3.5.2.6 :Simplified N Bit SAR ADC

Table 3.5.2.4 Comparison Table among different ADC Architecture

Based on Table 3.5.2.4 the proponents are initially thinking of SAR ADC as the
quantizer for the Sigma Delta Modulator since it has low power consumption with high
resolution and high sampling rate

d. n-bit DAC

Figure 3.5.2.7 n-bit DAC

A resistor string DAC, is one of the simplest and popular architectures. It features
monoticity, good Differential Non Linearity (DNL) performance low power consumption
and high conversion rate.

The initial chosen topology for the n-bit DAC is the resistor string DAC topology.
This topology has the most significant advantages among the rest of DAC topologies.
Such advantages are its monoticity, its good Differential Non Linearity (DNL) and
Integral Non Linearity (INL) performances (See in the Figure 3.5.2.8) across the input
code range, its high conversion speed and specially its low power consumption. (Bula
Carlos D.)
 Figure 3.5.2.8 DNL and INL plot comparison [DAC Topologies for GSM
Sigma Delta Modulators (Bula Carlos D.)]

Decimator

Table 3.5.2.5 Comparison Among Several Decimator Configurations

(Anil Bhardwahj, 2015)

 Based on the table above Non Recursive Comb Filter has the least power
consumption so the proponents are initially planning to use them.

Figure 3.5.2.9 1st order CIC Filter

CIC filter power consumption can be minimized by reducing the data word width
and data clock rates. CIC filter power consumption can be reduce by using serveral
techniques such as polynomial factoring and nonrecursive structures easing the word
width growth problem.

In the nonrecursive structure the data word width increases by M bits each
stage,but the sampling rate is reduced by factor of 2. This nonrecursive structure has
been shown to consume less power compare to recursive implementation ()
3.5.3 Computation of Parameters

Sigma Delta Modulator

Table 3.5.3.1 Parameter Formulas

Term Formula

𝑆𝑄𝑁𝑅−1.76
Effective Number of Bits ENOB = 6.02
(ENOB)

Oversampling Ratio (OSR) 𝑓𝑠

𝑂𝑆𝑅 =
2𝑓𝐵

Signal quantitized Noise 𝜋 2𝐿

( )
Ratio (SQNR) 𝑆𝑄𝑁𝑅𝑚𝑎𝑥 (𝑖𝑛 𝑑𝐵) = (20𝐿 + 10) log10 2𝐿 + 1
+6.02𝑁 + 1.76

Dynamic Range (DR) 3 2𝐿+1

DR = 2 ( 𝜋2𝐿 )(2𝑁 − 1)2 𝑂𝑆𝑅 2𝐿+1

Figure of Merit (FOM) 𝑆𝑁𝐷𝑅−1.76

𝐹𝑂𝑀 = 𝑝𝑜𝑤𝑒𝑟/[2 ∗ 𝐵𝑊 ∗ 2 6.02 ]

INL = | [(VD - VZERO)/VLSB-IDEAL] - D |

Integral Non-Linearity (INL) , where 0 < D < 2N-1.

VD - analog value represented by the digital output

code D,
N - ADC's resolution,
VZERO - minimum analog input corresponding to an
all-zero output code,
 VLSB-IDEAL - ideal spacing for two adjacent output
codes.

Differential Non- DNL = |[(VD+1- VD)/VLSB-IDEAL - 1] |

Linearity(DNL)
, where 0 < D < 2N - 2.
VD - physical value corresponding to the digital
output code D,
N - ADC resolution,
VLSB-IDEAL - ideal spacing for two adjacent digital
codes.

a. Operational Amplifier
Design Formulas for Two Stage Operational Amplifier

(Er. Rajni, 2011)

3.5.4 Circuit Schematic Implementation

As the sizing for the transistor and values for the other electronic components are
computed, the proponents will build the circuit schematic in Cadence.

3.5.5 Testing and Verification

After the circuit schematic is successfully built, the circuit will undergo to the
testing process. The proponents will use the features of Cadence and/or Matlab to test
and verify if the target specification of Sigma Delta ADC is met or not.

3.5.6 Decision

After the checking for the performance using multiple test analyses, the
proponents will redesign the sigma delta whenever the target specifications of ADC are
not attained.

Opening Cadence Virtuoso

1. Open Virtual Box.

 Figure 3.5.2 Start-up Screen of the Cadence Virtuoso

2. On the left pane, choose the created virtual machine and click “Start”.

Figure 3.5.3 Start Icon

3. The virtual machine will start and will ask you to choose which disk to boot. Choose
the first one by hitting Enter on the keyboard.
4. A login screen will appear. Just click the name or hit Enter then enter the following
password without quotes: “.smarzo” and click Sign In or hit Enter.
5. The desktop will appear if the login is successful.
 Figure 3.5.4 Cadence Virtuoso Desktop
6. Right click in Desktop
7. Choose Open Terminal
8. Enter the following commands:
- “ cd workspace”
- “source bashrc”
- “virtuoso”
9. Ignore the error and wait for the GUI to load.

Adding shared folder between windows and rhel7

1. On the menu bar of the Virtual Box, click Devices  Shared Folder  Shared Folder
Settings.
2. Settings window will appear. Right click on the Folders List and choose “Add Shared
Folder”. For the Folder Path, choose “Other” then choose the folder desired. (For
example, I created a folder “VMshared” on Desktop of Windows) Check “Auto-mount” and
“Make Permanent” the click Ok.
3. The Folder List will be updated. Click OK and reboot the machine by typing “reboot” on
the Terminal.
3.6 Test and Integration

After accomplishing sub-stages circuit design, it is subjected to testing.

Numerous simulations are made to ensure that the design is running as planned. The
proposed design will be simulated after the designing is done. Since this design is
composed of many subblocks integration will also be done for the design to function
properly. In this part every subblocks will be tested on different parameters that will
ensure their functionality. The software to be used in the simulation would be cadence
virtuoso using 45 nm gpdk and Verilog HDL.
The testing will be done so as to evaluate first the functionality of the subblocks
of modulator-differentiator, integrator, ADC,DAC and the digital decimator and digital
filter. All the results and tests are going to be observed. Errors on simulations will be
checked and will undergo troubleshooting. The effect of one parameter over the other
will be also analyzed.
Testing in Cadence

First, open the file name of the Sigma Delta Analog to Digital Converter, click
file Open. From the library, choose the desired cell view of the developed schematic
of the Sigma Delta ADC. Set the default configurations for View and Open with Field as
schematic and schematic L, respectively. Then, click OK button. The Schematic Editing
Window for the Sigma Delta ADC circuit will be displayed.

Then, simulate the schematic of the circuit. Click Launch ADE L. An ADE L
window will pop out that will serve as a platform for editing design variables, analyses
and outputs to be plotted in the simulation. Edit Analyses for generating the graph of the
different tests. Select the type of Accuracy Results then click Apply and OK.
 Figure 3.6.1 Analyses Window

A. DC Analysis
1. In your Schematic Editor Window, go to Launch  ADE L. Click Yes when asked
about ADE XL instead. The Analog Design Environment (ADE) shown below
will pop-up.
2. In the ADE window, add Model Libraries. Go to Set-up  Model Libraries then
add the necessary model and check its corresponding box.
3. Fill in the Section (opt) in the Model Library Setup. Choose tt for typical process.
Then click apply to add the model les. Then click the OK button.
4. Specify your analysis to be performed in the ADE window. Click Analayses 
Choose. The window for analyses options will appear.
5. In the Analysis Window, choose the corresponding analysis for your circuit. For
this exercise,
a. Toggle dc for DC analysis.
b. Toggle Save DC Operating Point also to view operating region.
c. Toggle Component Parameter to sweep a device instance
parameter (Vgs on this exercise).
d. Click Select Component and select from the schematic the ideal
voltage source.
e. Select Component Parameter window will pop-up, then click the item
with DC voltage and click OK. In the Sweep Range menu, toggle
 Start-Stop and provide the sweep range (Start: 0 Stop: 1, this is
actually the X-axis (VGS) of your graph).
f. Toggle Enabled and click Apply afterwards.
*Note: The Circuit is just a sample to set as guide for the simulation process.
6. Back in the ADE window, dene the outputs where the analysis will be obtained.
Go to Outputs  To be Plotted  On Schematic. Then the schematic
window of your circuit will appear.
7. Select the drain node of the N-channel device to plot values of the drain current.
The selected parts will display in the ADE window.
*Note: Selecting nodes will plot current while selecting wire will display
voltages.
8. After completing the ADE set-up, in the right side of the window click the icon
for Simulate and Run (green circle with a white arrow on the center).

B. AC Analysis
1. After configuring each component, click the Launch option on your schematic
window and select ADE L.
2. Right-click on then analyses panel and select Edit. Choose ac. Set Analyses
with starting frequency = 1Hz and ending frequency = 1 G (optional). Press
OK. Refer to the image for analyses set-up.
3. To be able to show the frequency response of the output, open the calculator
(in the ADE L toolbar Tools  Calculator).
4. You can show the magnitude plot in dB with the following steps:
a. Click vf and click the output node CO in the schematic.
b. Click vf and click the input node V1 in the schematic.
c. Click / option under key pad.
d. Click mag and db20 in the Modifiers list
e. Go back to ADE L toolbar and right click on the output panel and
select edit. The Setting Outputs window will appear.
f. Click Get Expression name the expression as magnitude and press
OK.
5. To simulate the phase plot refer to instructions discussed for the simulation of
magnitude plot, however, instead of setting the modifier to mag and dB20,
select phase. On your setting outputs window, get expression and name
this ‘phase’
6. After setting the Output and Analyses configurations on ADE L toolbar, run your
simulation by pressing the green button (run) at the right side of your ADE
L window, a window for your waveform will appear.

C. Transient Analysis
1. After configuring each component, click the Launch option on your schematic
window and select Ade L.
2. Right-click on the analyses panel and select Edit. Choose tran. Set Stop Time
to 10u and tick conservative and click OK.
3. After setting the Output and Analyses configurations on ADE L toolbar, run your
simulation by pressing the green button (run) at the right side of your ADE
L window, a window for your waveform will appear.

7. Choose voltage for Output. For the Positive Output Node click select and choose
and part on the design where output is expected to be seen. For the
Negative Output Node choose the wire connecting to the ground.
8. If phase noise is needed choose time average for Noise Type and click PM.
9. Click OK.
10. Click the green button to run simulation.
11. Choose Results  Direct Plot  Main Form. Then click Phase Noise and Plot.