Using the D&C approach, you need to design a combinational circuit that counts the number of 1’s in an n-bit number (bit-string) A. The resulting circuit needs to be as fast as possible via designing a fast D&C structure (which mainly, though not exclusively, will be due to having a minimum number of levels), but not by using a faster and thus more expensive design of leaf or stitch-up functions than their least expensive design. Assume that n = 2k, for some k. As part of your design derivation, you need to clearly show the following aspects of your D&C approach. (a) The breakup of the root problem into two or more subproblems, including a clear description of what those subproblems are. 25 (b) The stitch-up function at each level i of the D&C tree (level 1 is the top level). This can be described/designed in a generic way for level i in terms of its functionality and input/output size (number of bits); need not give different stitch-ups for each different level i. If the stitch-up function is a well-known or at least well-defined mathematical or logical function that you can describe mathematically and/or logically, then you need not derive the truth table (TT) or exact logic expressions and gate-level implementation of this function. Otherwise, you can just give the TT or logic expressions of the function. Note also, that in the former case, the stitch-up function can either be one well-defined function or a composition of two or more well-defined functions. Also, for this problem, the stitch up function should be designed with the minimum hardware cost; so do not use a fast stitch-up function to speed up your design if it has more hardware cost than a slow design. 75 (c) The leaf function, which is the function that is needed at the bottom of the D&C tree. Again, the leaf function should be described in a similar way as specified for the stitch-up function. Note that the level of the D&C tree at which the leaf function’s realization is appropriate is dependent on the design problem, and can typically range from a problem of size 1 to 4 bits. In this case, you need to judiciously determine this level so that it makes sense for the current problem. The leaf function also should be designed with the minimum hardware cost. 25 Finally, note that in some designs the stitch-up and leaf functions are different and in others, they are the same. It is for you to determine what the case is for this problem (this is also partly dependent on your D&C approach). (d) The schematic of the final design for n = 8 in terms of the interconnections between the leaf and 3 stitch-up function blocks, in which the smallest basic blocks of input size _ 4 (see the next item for the definition) that the stitch-up and leaf blocks may be composed of, are also shown. The structure of the circuit should be complete and clearly understandable. Show the critical path of your design in the schematic. 50 (e) Determine the delay of this circuit as a function of n, assuming that the delay of the smallest well-defined basic function(s)/block(s) with a small constant number of inputs (i.e., whose number of inputs is not a function of n and is a small number, say, _ 4) that you use in your stitch-up functions and leaf functions is 1 unit. Note that if there are other basic functional blocks with a small constant number of inputs, but which are larger than the smallest block, take their delay to be an appropriate multiple of unity (delay of smallest-size block) and briefly justify this multiple. 75 (f) Analyze the hardware cost of your design as a function of n, assuming unit cost for the smallestsize well-defined basic function block (each with a small constant number of, say, _ 4, inputs). Note that if there are other basic functional blocks with a small constant number of inputs, but which are larger than the smallest block, take their cost to be an appropriate multiple of unity (cost of smallest-size block) and briefly justify this multiple. 50 Maximum points can only be obtained for fast and hardware-cost-efficient designs. Note again that the speed of the design is to be obtained by a good D&C structure and not by using a faster stitch-up or leaf function design (in case. multiple designs are possible for the determined stitch-up and leaf functions) Total 300 Summation Closed Form Hint: Xk i=0 (i _ ai) = a _ Xk i=0 (i _ ai1) = a _ Xk i=0 d(ai) da =a_ d Pki =0 ai da =a_ d(1 ak+1)=(1 a) da ( if a < 1) = a _ [(k + 1)ak=(1 a) + (1 ak+1)=(1 a)2] A similar approach applies if a > 1. 4 3. Divide-&-Conquer (D&C) Based Design 2 Use the divide-and-conquer (D&C) approach to design a combinational multi-bit left-shifting circuit with inputs that are an n-bit number X (the shiftee) and a log2 n bit # m (the shift amount), and which outputs a (2n 1)-bit number Z that is X shifted m times. E.g., if X = 11000111, and m = 110 = 6, then X needs to be shifted by 6 bits and Z = 011000111000000. Such a shifter is called an (n; log2 n), shifter—an (n; k) shifter shifts n bits of some inputX by the shift value encoded in k bits. As part of your design derivation, you need to clearly show the following aspects of your D&C approach. (a) The breakup of the root problem (i.e., the first level breakup) for an n-bit X into two or more subproblems, including a clear description of what those subproblems are. 50 (b) Stitch-up Issues: – If there is a stitch-up function for this problem derive the design. If the stitch-up function is a well-known or at least well-defined mathematical or logical function that you can describe mathematically and/or logically, then you need not derive the truth table (TT) or exact logic expressions and gate-level implementation of this function. Otherwise, you can just give the TT or logic expressions of the function. Note also, that in the former case, the stitch-up function can either be one well-defined function or a composition of two or more welldefined functions. – If there is subproblem dependency for your breakup, specify what it is, and if so, discuss if it makes sense to use the Wait or the DAC strategy to resolve the dependency, and do accordingly in your design. 25 (c) The leaf function, which is the function that is needed at the bottom of the D&C tree. Again, the leaf function should be described in a similar way as specified for the stitch-up function. Note that the level of the D&C tree at which the leaf function’s realization is appropriate is dependent on the design problem, and can typically range from a problem of size 1 to 4 bits. In this case, you need to judiciously determine this level so that it makes sense for the current problem. 50 (d) The schematic of the final design for an (8, 3) shifter, clearly identifying whichever of the following are there in your design: the leaf function, the stitch-up functions, the subproblem dependencies. The schematic should also show the smallest basic blocks of input size _ 4 (see 5 the next item for the definition) that the stitch-up and leaf blocks may be composed of. The structure of the circuit should be complete and clearly understandable. Show the critical path of your design in the schematic. 75 (e) Determine the delay of this circuit as a function of n, assuming that the delay of some welldefined basic function(s)/block(s) with a small constant number of inputs (i.e., whose number of inputs is not a function of n) that you use is 1 unit. Identify all your basic blocks. 50 (f) Analyze the hardware cost of your designs in terms of the number of the aforementioned welldefined basic function blocks (each with a constant number of, say, _ 4, inputs), i.e., assuming the cost of each such basic block is 1 unit. 50 Total 300 Hint: Perform the D&C of the design by breaking up the bits representing the shift amount m.