Subject: VLSI Design and Technology(BE- 2015 Course) 404181

Teaching Methodology & Details

Book list:

Text Books:

T1: Charles Roth, and Lizy John “Digital System Design using VHDL,” 2nd Ed., Cengage Learning.

T2: Wayne Wolf, “Modern VLSI Design (IP-Based Design),” Pearson Publication.

T3: Steve Kilts “Advanced FPGA Design Architecture, Implementation and Optimization,” Wiley.
Reference Books:
R1: Neil H. E. Weste, David Money Harris, “CMOS VLSI Design: A Circuit & System Perspective,” 4 th Ed. Pearson Publication.
R2: R. Jacob Baker, “CMOS Circuit Design, Layout, and Simulation‖,” 3rd Ed, Wiley-IEEE Press
R3: John F. Wakerly, “Digital Design Principles and Practices,” 4th Ed., Prentice Hall
R4: M. Morris Mano, “Digital Design‖,” 3rd Ed., Pearson
R5:Cem Unsalan, Bora Tar, “Digital System Design with FPGA: Implementation Using Verilog and VHDL,” McGraw-Hill
R6: Jayaram Bhasker, “A VHDL Primer,” 3rd Ed., PHI.
R7 : Brown-Vranesic,”Fundamentals of Digital Logic with VHDL Design”Second Edition”
R8 : RABAEY : Digital Integrated Circuits

Unit Content Page nos. of Text/Reference book

I : HDL Design flow T1: 52-53 OR R3: 241-243
Language Constructs, Modeling styles R6: 4-13
Design
Data objects, Data types, Operators R6: 14-27
Sequential statements R6: 28-34
Concurrent statements R6: 44-59
Packages and Libraries R6: 78-79
Functions, Procedures, Attributes, T1: 389-400
Operator overloading, Resolution
functions
Mealy and Moore machine sequence T1: 17-28
detector and other state machine examples
Compilation, Simulation, and Synthesis T1: 77-81, 84-87
Hierarchical and flat designs R6: 123-125
Partitioning for synthesis T3: 188-190
Resource sharing T3: 208-210
Pipelining T3: 211-213
Efficient coding styles Efficient coding styles.pdf
Sequential synchronous machine Any 2nd year DIGITAL ELECTRONICS
II: design TEXTBOOK
Moore and Mealy machines
Digital
HDL code for Machines R7:Topic 8.4 ( 502-513 )
Design and (Run the programs in XILINX ISE & show )
Issues FIFO Should be covered in PRACTICALS
Metastability and solutions T1:1.10 ( 30-35 )
Noise margin ,Fan-out R8 : ( 26 -30 )
Skew ,Timing considerations R8 :10.3.1(46-48),T2:5.4.3(311-314 in PDF search )
Hazards R4 : Topic (9.7) ( 452-457 ),T1( 12-14)
R7 : Topic (9.6) ( 656- 663 in PDF search )
Clock distribution T2:7.3.3 ( 457-460 in PDF search )
Clock jitter R8 :10.3.1(50-51)
 Supply and ground bounce Hand-Written Notes Posted on Group
Power distribution techniques T2:7.3.2 ( 452-454 in PDF search )
Power optimization T2:5.7 ( 341-342 in PDF search )
Interconnect Routing techniques T2:7.2.2 ( 443-451 in PDF search )
Wire parasitic T2:2.4.1 ( 88-94 in PDF search )
Signal integrity issues T2 : 5.3.2 ( 294-299 in PDF search )1-Phase,2-Phase
Clock , Signal Skew
I/O architecture T2:7.5.2 ( 469-473 in PDF search )
III : PLD Design flow T1: 52-53
Architecture CPLD Architecture, Features, T1: 156-160 OR R3: 840-849 (XC9500 family)
Specifications, Applications
s and
FPGA Architecture, Features, T1: 165-185 AND/OR R3: 850-858 (XC400 family)
applications Specifications, Applications. Note: For architecture refer R3
Implementing functions in FPGA T1: 310-316
FPGA synthesis and implementation. T1: 339-348
IV : N-MOS, P-MOS and CMOS, MOSFET R1: 61-93,
DIGITAL parasitic, Technology scaling, Channel 141-142,
length modulation, Hot electron effect,
CMOS Velocity saturation, CMOS Inverter, 181-204,
Circuits Device sizing, CMOS combinational logic 327-332,
design, Power dissipations, Power delay
product, Body Effect, Rise and fall times,
Latch Up effect, transmission gates.
V: Design Flow T1: 52-53
Application Cell design specifications R2: 97-98 AND R1: 632-634
Spice simulation, AC and DC analysis, R2: 8-29
Specific
Transfer Characteristics, Transient
Integrated responses, Noise analysis
Circuit Lambda based design rules, Gate layouts R1: 24-26; 27-29
Fabrication methods of circuit elements: R2: 110-113
Resistors: Interdigitated and Common-
Centroid layout
Fabrication methods of circuit elements: R2: 114
Capacitors
Fabrication methods of circuit elements: R2: 120-121
MOSFETs
Design verification: Electrical rule check, R1: 53
Design rule check Layout Vs. Schematic
Post-layout Simulation and Parasitic R1: 643
extraction
Antenna effect R1: 133-134
Electromigration effect R2: 68
Drain Punchthrough R1: 252
Crosstalk R2: 71-72
Static Timing Analysis R1: 640
VI: Types of fault, Need of Design for T1: 339-361
Testability (DFT), DFT Guideline,
Testability, Fault models, Path sensitizing,
VLSI Test pattern generation, Sequential circuit
Testing and test, Built-in Self-Test, JTAG & Boundary
Analysis scan, TAP Controller.