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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Multilevel Power Optimization of
Pipelined A/D Converters
Jintae Kim, Member, IEEE, Sotirios Limotyrakis, Member, IEEE, and Chih-Kong Ken Yang, Senior Member, IEEE
Abstract—Power dissipation of analog and mixed-signal cir-
cuits has emerged as a critical design constraint in today’s
VLSI systems. This paper presents a multilevel design opti-
mization approach for reducing the power dissipation of a
pipelined analog-to-digital converter (ADC). At the circuit-level,
device-types and supply-voltages are jointly optimized for the
residue amplifier of a pipeline stage to minimize power. At the
architecture-level, the nonlinearity contribution from stage gain
error is optimally distributed to further minimize combined power
dissipation. The optimizations take advantage of an analytical
optimization method based on geometric programming for a
quantitative tradeoff analysis. All of the proposed power opti-
mizations are applied to the design of a two-way interleaved 8-bit
320 MS/s pipelined ADC in 90-nm CMOS technology. Measured
performance from a prototype chip shows 7.30-bit of ENOB at
Nyquist input frequency with DNL of 0.35 +
0.45 LSB and INL
of 0.72 + 0.89 LSB, while dissipating 12.77 mW from 2.1 V/1.2
V supplies. The achieved conversion efficiency is 253fJ/conv-step.
Index Terms—Analog circuit, data converter, low-power design,
optimization, pipelined analog-to-digital converter (ADC).
I. INTRODUCTION
P OWER dissipation has emerged as the most critical design
constraint in modern VLSI systems [1]. While tradition-
ally more critical for battery-operated applications, power dis-
sipation has become a universally important design metric due
to growing power density in today’s VLSI as well as the lim-
ited cooling and power delivery capacity of the package. With
ongoing trend of increasing integration of synthesized digital
circuit and custom analog circuit, power dissipation from both
types of circuit blocks must be considered in order to achieve
an overall low power dissipation of VLSI systems. The focus of
this paper is to demonstrate a design approach that minimizes
power dissipation of analog and mixed-signal buliding blocks.
Pipelined analog-to-digital converter (ADC), a popular ADC
architecture for medium-to-high resolutions (8–12 bits), is one
such building blocks that are commonly used in modern mixed-
signal ICs. To minimize the power dissipation, a number of ap-
proaches have been proposed from a wide range of perspec-
tives. Circuit-level techniques such as opamp sharing [2], [3]
and comparator-based charge transfer [4] aim to efficiently use
Manuscript received September 06, 2009; revised January 11, 2010. This
work was supported by DARPA-TEAM.
J. Kim was with the Electrical Engineering Department, University of Cal-
ifornia, Los Angeles, CA 90095 USA. He is now with Agilent Technologies,
Santa Clara, CA 95051 USA (e-mail: jintae.kim@ieee.org).
S. Limotyrakis is with Atheros Communication, Inc, Santa Clara, CA 95051
USA.
C.-K. K. Yang is with the Electrical Engineering Department, University of
California, Los Angeles, CA 90095 USA.
Digital Object Identifier 10.1109/TVLSI.2010.2041077
1063-8210/$26.00 © 2010 IEEE
1
the signal current, leading to a low-power pipeline stage imple-
mentation. At architecture-level, optimizing per-stage resolu-
tion and noise contribution have been commonly used [5]–[10].
Various calibration techniques in both analog and digital do-
main [11]–[13] can compensate the inaccuracy of raw analog
signal processing, relaxing the precision requirement of analog
circuits and thereby achieving low-power dissipation. In many
cases, these techniques are not mutually exclusive.
This work demonstrates an analytical approach for reducing
the power dissipation, which in principle can supplement most
of the existing techniques. We exploit a fundamental observa-
tion that a broader design variable space, when a global op-
timum is found, improves the power-performance envelope of
the system. Two such design approaches are proposed in this
work. At the circuit-level, we propose to jointly optimize de-
vice types and supply voltages of the residue amplifier to imple-
ment low-power pipeline stage. At the architecture-level, contri-
butions of per-stage gain error to the total linearity degradation
are optimized in addition to optimizing per-stage resolution and
noise contributions for minimizing total power dissipation.
Adding degree of freedoms to the variable space increases the
design complexity, often times exponentially. This work takes
advantage of a design optimization method based on geometric
programming (GP) [14], a special type of convex optimization
problem, to address the increased design complexity. An equa-
tion-based pipelined ADC model compatible with GP is de-
veloped to enable an efficient tradeoff analysis for proposed
power optimizations. This approach yields an optimized tran-
sistor-level design when applied to a predefined circuit topology
and process technology, an additional benefit not available in
hand analysis.
The rest of this paper is organized as follows. Section II
presents an overview of the pipelined ADC model that is used
as a testbench of the analysis in this work. Section III explores
the joint-optimization of device-type and supply voltages to
designing low-power pipeline ADC stage. Section IV de-
scribes the optimization of nonlinearity contribution from stage
gain errors at the architecture level. The tradeoff analyses in
Sections III and IV take advantage of the ADC model described
in Section II to quantitatively explore corresponding design
tradeoffs. Proposed power optimizations are applied to the
design of an 8-bit 320 MS/s pipelined ADC in 90-nm CMOS
technology. Sections V and VI describe the chip implemen-
tation details and measured performance from a prototype
chip. Section VII concludes the paper by summarizing main
contributions. In the three Appendies, the GP-based design
methodology is briefly reviewed and the circuit-level pipeline
stage model is described in more detail. Additionally, a mod-
eling technique that can transform a nonconvex inequality to a
set of GP-compatible monomial inequalities is presented.
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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 3. Stage-level model.

Fig. 1. Hierarchies in pipelined ADC model.

front-end stage is a gain-of-one stage without a sub-ADC. The

backend stage is a sub-ADC without an MDAC and redundancy.
Therefore, no separate modeling is necessary for the front-end
and back-end stage.

B. Variables in the Model

The ADC model in the top-level and stage-level considers
following variables. The subscript in the variable refers to the
th stage.
• Peak-to-peak analog input swing: .
Fig. 2. Top-level model. • Stage resolution: .
• Stage total sampling capacitance: .
• MDAC variables.
II. PIPELINED ADC MODEL — Power: .
Illustrated in Fig. 1, the ADC model consists of four levels — Input/output loading: , .
of hierarchy: top-level, stage-level, circuit-level, and transistor- — Open-loop gain of the opamp: .
level. Top-level and stage-level model capture design tradeoffs — Input-referred noise power of the opamp: .
inherent in the pipelined ADC architecture, while circuit-level — Transconductance of the opamp: .
and transistor-level models deal with topology and technology — Input capacitance of the opamp: .
specific design tradeoffs. This section describes the top-level • Sub-ADC variables.
and stage-level ADC model. The circuit-level model as well — Power: .
as a brief introduction to the GP optimization are presented in — Input loading: .
Appendices A and B. — of input-referred offset: .
— Clock-to-data delay: .
A. Model Overview Note that the stage resolution is linked to the various stage
Shown in Fig. 2, top-level model consists of stages design parameters. For instance, the number of 1-bit flash slices
connected in cascade. Front-end stage, or stage, is a track- in the sub-ADC is given by . Also, ideal
and-hold (T/H) amplifier that samples the input and passes held stage gain is given by , where
analog output to the following ADC stages. Internal pipeline and are total capacitance of the two banks of sampling
stage, or th stage, resolves -bit from the analog input and capacitors in Fig. 3, respectively (e.g., ).
passes the residual analog information, or residue, to the th Since the total input capacitance is given by
stage. Backend stage is a special case of the stage which does , and can be chosen subject to and . Note
not pass residue to the following stage. that holds for the backend that does not need
Fig. 3 illustrates a generalized stage model as a single-ended redundancy.
representation. The stage model consists of two building blocks,
an MDAC and a sub-ADC. The topology of the MDAC fol- C. Equation-Based ADC Model
lows a standard flip-around switched-capacitor circuit using a • Total Resolution: Total resolution of the ADC, , must
high-gain opamp with negative feedback as a residue ampli- be same as the summation of the stage resolutions, i.e.,
fier [15]. The sub-ADC is a flash ADC consisting of slices,
each resolving 1-bit of digital information with corresponding
(1)
threshold value. The stage model adopts a standard 1-bit redun-
dancy in the sub-ADC of internal stages [16] in order to relax the
offset requirement in the sub-ADC. Note that T/H and backend where is the total number of the pipeline stages.
stage can be modeled as a special case of the internal stage. The Note that is a discrete variable, which is not found
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KIM et al.: MULTILEVEL POWER OPTIMIZATION OF PIPELINED A/D CONVERTERS 3

by solving a single optimization problem. Rather, we

have to choose the per-stage resolution before optimizing
the problem, e.g.,
or for , where is th
component of . Because optimizing the problem via GP
is very efficient, we can iteratively solve the problem for
various choices of that satisfies (1) to determine which
gives the best result.
• Total power dissipation: Total power of the ADC is the Fig. 4. (a) MDAC model in amplification phase. (b) Linear settling model of
summation of the stage powers, i.e., MDAC output.

(2)

• Input-referred signal-to-noise ratio : SNR is a ratio (6)

between signal power and the input-referred thermal noise
power, and needs to be lower-bounded to achieve a desired where is the effective feed-
noise performance. One can show that the SNR due to the back factor. Second, the dynamic error is a function of both
thermal noise in the pipelined ADC can be constrained as and , where the time constant can be approximately
expressed as [17]

(7)

where is the signal power of the sinusoid with where . Note that the total
peak-to-peak amplitude of , is input referred output capacitance of th stage, , is a lumped total ca-
thermal noise power of the stage and is a pacitance from both internal parasitic and following stage
given specification on the SNR. Since the stage adds noise loading, i.e.,
in the sampling and amplification phase, should
include two uncorrelated noise powers in both phases, i.e.,
(8)
(3) In a pipelined ADC design, in each stage is typi-
cally designed to be sufficiently smaller than the LSB of
remaining stage resolution to preserve the total linearity.
where is the Boltzman constant, is the absolute tem-
Since in (5) contains two components, we can as-
perature and is the time-constant of the MDAC, which
sign each contributing the same amount of error to the
shall be given by (7).
total gain error.1 Note that is also constrained by the
• Stage gain error: An MDAC in the amplification phase can
timing budgets in the amplification phase. Specifically, for
be modeled as a feedback amplifier shown in Fig. 4(a),
a given half-cycle period, non-overlapping clock period be-
and its dynamic response can be approximated as a first-
tween sampling and amplification phase, , and a
order linear settling when the slewing is negligible, which
timing delay in the sub-ADC to generate full logic level
is shown in the Fig. 4(b). While the ideal stage gain is
from sub-ADC input, , add to the total timing
given by , the actual stage gain deviates from
budget, i.e.,
due to the finite open-loop gain and time-constant of the
opamp. In a pipelined ADC that doesn’t incorporate some (9)
calibration techniques, stage gain error is the major source
of the ADC linearity degradation. One can show that the
• Sub-ADC offset: The input-referred offset of the sub-ADC
MDAC output voltage at the end of amplification phase can
needs to be less than allowable correction range in the
be modeled as
stage. Otherwise, output voltage of the stage exceeds the
(4) input range of the following stage, causing linearity error
that cannot be corrected by the digital redundancy. This
where is a static error, is a subtracted voltage in consideration can be constrained as
the MDAC, is a given time period for the settling, and
is the time constant of the MDAC. The total gain error (10)
from both nonzero and can be further simplified as
where is a yield parameter that is linked to the percentage
(5) of the sub-ADC whose offset lies beyond the allowable
We identify two sources of errors in (5). First, the static range in statistical sense.
error arises from the finite open-loop gain of opamp in 1From power dissipation perspective, it is not necessarily an optimal way to
the feedback configuration and can be expressed as [17] split the error evenly, and this is further discussed in Section IV.
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4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

III. DEVICE-TYPE AND SUPPLY COOPTIMIZATION

With the ADC model developed in Section II, this section
describes a design approach that jointly optimizes device-type
and supply voltages in an MDAC design to minimize the power
dissipation.
A. Device-Type Optimization
In an MDAC design that employs an opamp with negative
feedback as a residue amplifier, achieving high open-loop gain
is a common design goal to meet the required accuracy of
the stage. One straightforward way is to use non-minimum
channel length transistors in an opamp to enhance the intrinsic
gain , but it often leads to high power dissipation due
to the tight power-performance tradeoffs in an opamp design.
For instance, the tradeoff involved at the input transistor of an Fig. 5. Simulated intrinsic gain versus L of three types of NFET in 90-nm
opamp can be expressed as CMOS.

(11)
where is the cutoff frequency of the input tran-
sistor. Since increasing channel length of the transistor trades
for , (11) implies that the net benefit of increased
to the total gain error in (5) diminishes by the degraded feed-
back factor and time constant. Additionally, it has been rec-
ognized that exercising the tradeoff between and by
the channel length is noticeably less efficient due to the adverse
effect of a pocket implant, a commonly-adopted channel engi-
neering method in sub-100-nm technology [18]. Therefore, an
attempt to improve by sizing the transistor with longer
channel length is expected to incur excessively high power dis-
sipation in nanometer-scale technologies.
One way to relax the tight tradeoff is to leverage the multi-
tude of devices offered in nanometer CMOS technology. While
this is only applicable method for the process that offers mul-
tiple device types, most of today’s standard foundry processes
commonly offer a device pool with multiple threshold voltages
and oxide thickness for designers to choose from. The primary
use of these devices is to help with digital designs to control
leakage and handle I/O voltages, but their differences in output
resistance can be exploited in analog designs.
Fig. 5 shows a simulated intrinsic gain versus channel
length of regular-threshold (CORE), high-threshold (HVT),
and thick-oxide (I/O) type of NFET offered in a foundry 90-nm
CMOS technology for an identical gate overdrive and head-
room condition. Evidently, a reduced sensitivity of to the
of CORE device results in marginally increasing intrinsic gain
when 0.2 m. However, it is worth noting that the incre-
mental improvement of over varies substantially de-
pending on the type of device, particularly at longer channel
length. For instance, at 0.5 m, of I/O device is
more than 2 higher than that of the CORE device, with the
gap reaching up to 5 at 1 m. The comparison shown in
Fig. 5 suggests that when the highest is not needed, selecting
I/O device instead of CORE device with same and overdrive
leads to higher open-loop gain of the amplifier without com-
promising , since is first-order independent to the oxide
thickness for identical overdrive and . This is in a sharp con-
trast with merely increasing , which must compromise to
improve . Therefore, we can anticipate that a judicious de-
vice-type selection should relax the power-performance tradeoff
Fig. 6. Tradeoff in selecting supply voltages and signal swing.
in an MDAC design. Note that while the advantage of choosing
one device over the other may seem apparent at the device-level,
the best combination of device types as well as the amount of net
benefit in a particular circuit structure has to be carefully exam-
ined by cooptimizing the bias condition and sizing of individual
transistors.
B. Supply Voltage Optimization
In mixed-signal designs, supply voltages can often be design
variables when they are not constrained by system-level speci-
fication. The impact of supply voltage to noise-limited analog
circuit has been discussed considerably in previous literature
[9], [19]. Fundamentally, low supply voltage reduces the avail-
able headroom for signal swing, hence degrading the tradeoff
between signal-to-noise ratio (SNR) and power dissipation.
Fig. 6 illustrates a first-order tradeoff involved in the context
of pipelined ADC. The SNR is related to the signal swing and
sampling capacitor as
(12)
where is peak-to-peak signal swing and is sampling
capacitance. It follows from (12) that linearly increasing
enables a quadratic reduction of for a fixed SNR require-
ment. Using the gain-bandwidth product, or ,
as a measure of the speed, the transconductance and
correspondingly the bias current for a given overdrive voltage
can be quadratically reduced for the same speed requirement.
Therefore, having a large signal swing can potentially reduce
the power dissipation of pipelined ADC.
Increasing signal swing, however, imposes a tighter head-
room constraint that exacerbates the open-loop gain of an
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KIM et al.: MULTILEVEL POWER OPTIMIZATION OF PIPELINED A/D CONVERTERS
Fig. 7. (a) T/H stage model used in the analysis as a test-bench circuit. (b)
Schematic of the telescopic opamp which is used as a stage amplifier.
amplifier because the output resistance of transistor is in-
versely proportional to . To accommodate larger signal
swing without compromising the headroom constraint, one can
increase analog supply while keeping the same gate
overdrive, or , for all transistors. The net result is that
analog power reduction is at best linearly proportion to the
signal swing. In addition, increasing is eventually limited
by the device reliability. A common design constraint is that the
voltage across the gate oxide must be smaller than a designated
limit set by the process during both the normal operation and
power up-down sequence.2 Therefore, the net amount of power
reduction from higher signal swing will depend highly on a
circuit topology and process technology.
Note that increasing signal swing has an impact on the power
dissipation in the digital domain as well. In a typical pipelined
ADC design, analog signal has to pass through the switches
whose allowable range depends on digital supply and
threshold voltage . While the actual voltage range of the
signal is determined by a particular amplifier design, larger
signal swing to the first order requires higher to increase
allowable signal range in the switches. Consequently, higher
signal swing leads to a quadratic increase in the digital power
dissipation, degrading again the potential power reduction by
increasing signal swing.
Foregoing observations reveal that there may exist optimal
and that achieve optimal balance between power
dissipation and SNR, which depend on a particular design spec-
ification as well as circuit topology and process technology.3
In conjunction with the device type selection proposed in
Section III-A, a numerical design framework is necessary to
quantitatively explore the tradeoffs.
C. Tradeoff Analysis
To quantitatively explore the proposed design optimizations,
the stage model introduced in Section II has been extensively
optimized for tradeoff analysis. A particular circuit topology
used here is a front-end T/H stage using telescopic opamp as
a residue amplifier as shown in Fig. 7. A generalized B-bit
stage model previously shown in Fig. 3 is tailored for a T/H
2During the power-up sequence, one simple technique to relieve the device
reliability concern is to set up the bias of the amplifier slightly earlier than
power-up of the main amplifier.
3Having separate supply voltages for analog and digital domain is not un-
common in mixed-mode circuit designs as separate supply helps isolate digital
switching noise from analog supply.
5
TABLE I
DESIGN SPECIFICATION FOR T/H STAGE
500 ps is the non-overlapping period.
stage model that can be optimized for a foundry 90-nm CMOS
process. More details on the optimization methodology as
well as the circuit-level model for telescopic opamp can be
found in Appendices A and B, respectively. Design variables
include transistor-level variables such as width , length
, and bias condition of the transistors in a
telescopic opamp as well as supply voltages ,
signal swing , and sampling capacitance . The
model is optimized for minimum power dissipation for a set
of design constraints listed in Table I, which is chosen for
the front-end stage of an 8-bit pipelined ADC. Note that the
tradeoff analysis demonstrated here is easily applicable to other
amplifier topologies and design specification by modifying
equation-based circuit models.
To find an optimal set of device types, a constrained but ex-
haustive search has been performed. Since the telescopic opamp
consists of five transistors in each side and we consider three de-
vice types (CORE, HVT, and I/O), the total number of possible
device combination is . After optimizing the model for
all 243 cases, the optimal device-type is chosen by picking the
one with the lowest power dissipation. Although this approach
is by no means an efficient method, optimizing the stage model
takes only 2.5 seconds in our linux machine running on Xeon
2.8 GHz CPU with 2-GB memory, making an exhaustive search
among hundreds of data sets a feasible method. The advantage
of relying on such a numerical design framework is obvious; the
proposed device selection would have required tremendous de-
sign effort if every 243 circuit designs were to be handcrafted,
let alone the optimality of each design.
Fig. 8 shows a histogram of the power dissipation collected
from the exhaustive search. There exist 144 feasible designs that
meet given design specifications out of 243 combinations be-
cause the required open-loop gain and time constant are not si-
multaneously met in all cases. The power distribution is widely
spread from 0.61 to 4.2 mW, indicating that there is consider-
able impact of device-type selection on the power-performance
tradeoff of the T/H stage design.
Among 144 feasible solutions, Table II shows the design vari-
ables of the best device type as well as other design variables that
result in the lowest power dissipation. The optimal design oc-
curs when CORE device with close-to-minimum channel length
0.12 m is used for the input transistor to simultane-
ously achieve high and , while long-channel I/O de-
vice 1.12 m in the cascoding transistor maximizes
the open-loop gain while meeting the phase margin require-
ment. For the verification purpose, Table III shows a compar-
ison between predicted performance metrics from the optimizer
and simulated results, showing that there is a reasonably good
matching between them.
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6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

TABLE IV
TEN BEST DEVICE SELECTIONS

Fig. 8. Power histogram of track-and-hold stage from exhaustive search opti-

mizations.

TABLE II
OPTIMAL DESIGN VARIABLES FOR T/H DESIGN

Fig. 9. Optimal tradeoff between power dissipation of T/H and stage gain error.

TABLE V
OPTIMAL DEVICE SELECTION VERSUS GAIN ERROR SPEC

TABLE III
PREDICTED PERFORMANCE AND SIMULATED RESULT

gain error constraint and are listed in Table V; and 3) sub-op-

timal device selection in the Table II, which was found for an
8-bit equivalent gain error. Fig. 9 compares obtained power dis-
The multitude of histogram count in the first bin in sipation by optimizing the model. We first notice that a globally-
Fig. 8 indicates that a group of device-type selections achieves optimal case and a sub-optimal case almost overlap.
near-optimal result. Table IV lists the best-ten device combina- While the optimal device selection in Table V slightly changes
tions in the first bin. Emphasized in boldface, they commonly with gain error specifications, the comparison shows that the
choose CORE device for and I/O device for . The impli- difference is negligible if the device types of critical transistors,
cation is that device selections for transistors in the signal path and in this case, are judiciously chosen, agreeing with
have a more profound impact on the performance while the de- the observation made earlier in this section. A comparison with
vice types of other transistors are not as influential. Also, it is the case that uses only CORE device shows that the optimal
unlikely that the optimal device types in the signal path change device selection reduces the power dissipation by up to 60% or
over process corners since they are mainly circuit-topology de- gain error by 3 , which is a considerable improvement in the
pendent. This observation may be leveraged for larger problems power-performance tradeoff.
having more complicated circuit topologies to help reduce the Fig. 10 specifically explores the tradeoff involved in supply
search space. voltage and signal swing selection. Using the device types in
To quantitatively compare the amount of benefit by the pro- the Table II, it shows the optimized stage power dissipation
posed approach, we optimized the track-and-hold stage model versus for several selected . While the existence
while varying gain error constraints for three different scenarios: of optimal is easily identified ( 0.61 mW when
1) no device selection (CORE device for all transistors); 2) glob- 1.7 V and 1.21 V), it is also worth noting
ally-optimal device selection for corresponding gain error con- that using 1.2 V achieves the lowest the power dissi-
straints, which has been found by exhaustive searches for each pation. Since analog power dominates ( 540 W and
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KIM et al.: MULTILEVEL POWER OPTIMIZATION OF PIPELINED A/D CONVERTERS
Fig. 10. (a) Optimal power dissipation of T/H stage versus V
V values. (b) Correspoding optimal peak-to-peak swing (V
70 W) in the T/H model for a given design speci-
fication, higher signal swing enabled by higher leads to
a lower combined power dissipation. Note that these optimal
supply voltages, 1.73 V and 1.2 V, vary
depending on the design specifications and other stages in the
pipelined ADC. As shall be shown in Section V, 2.1
V is chosen as optimal analog supply when taking into account
all stages in the pipelined ADC.
IV. GAIN ERROR OPTIMIZATION
Reusing the optimal design of a stage in cascade does not
accomplish a globally optimal design. Individually optimizing
pipeline stage therefore has been of considerable interest in the
pipelined ADC design. Traditionally, this has meant optimizing
the stage noise contribution toward the input by optimizing
the sampling capacitance and per-stage resolution while mini-
mizing the total power dissipation. This work extends the scope
by optimizing the nonlinearity contribution from stage gain
error.
A. Stage Gain Error Optimization
The gain error of the stage shifts the residue output from
its ideal value, and its cumulative effect over the stages turns
into a linearity degradation of the overall transfer character-
istic. While the gain error can be calibrated by various tech-
niques in both analog [12] and digital domain [11], [13], it re-
mains as a major source of linearity degradation in an uncali-
7
brated pipelined ADC. A common wisdom has been to design
a stage accurately enough to preserve combined linearity of the
remaining stage resolutions. For example, one can design a stage
with a gain error less than 1/4 LSB of the remaining stage reso-
lution as described in Section II.
Two observations can be made. First, the required accuracy
diminishes along the pipeline, progressively relaxing the gain
error requirement. Together with the sampling capacitor scaling
[6], power dissipation of the first few stages should dominate the
total power dissipation in an optimized design. Second, given
the fact that the first few stages consume the majority of the
total power and their marginal power cost to reduce gain error
is higher than that of the remaining stages, relaxing their gain
error requirements would lead to substantial reduction in the
total power dissipation. From the linearity perspective, while the
relaxed gain error leads to an increased differential nonlinearity
(DNL), it is worth noting that integral nonlinearity (INL) is the
result of the cumulative contribution of DNL. In other words,
the gain errors of all stages, with diminishing weighting factor,
contribute to the INL degradation. Therefore, relaxing the gain
errors in the first few stages and tightening the gain errors in
the later stages can potentially save combined power dissipation
with INL performance being nearly unchanged.
The observations suggest that there can be a design optimiza-
tion that can judiciously balance the gain error contributions
from all stages while minimizing total power dissipation. We
refer to this as a gain error optimization.
for several B. Gain Error Model
).
To carry out proposed gain error optimization, the gain error
model compatible with GP optimization has been developed.
Because a compact equation that accurately links gain error to
the worst-case linearity degradation of an ADC is not straight-
forward, we propose a roundabout metric by referring stage gain
errors to the input of the converter, i.e.,
(13)
where is a total resolution of ADC. Mathemat-
ically, (13) is an input-referred sum of th stage gain errors
, normalized by the LSB of the converter.
The correlation can be verified by behavioral simulations.
Taking an 8-bit pipelined ADC converter as a test vehicle, stage
gain errors less than 0.5 LSB of remaining stage resolution are
randomly generated and INL has been found by behavioral sim-
ulations using MATLAB. Shown in Fig. 11 is a simulated worst-
case INL versus in (13) for 100 experiments,
where a linear correlation between and the can be
identified. Notice that (13) is not compatible with GP optimiza-
tion in its native form, but can be transformed to a compatible
form via numerical function fitting described in Appendix C.
C. Tradeoff Analysis
This section quantitatively explores potential power saving by
the gain error optimization in addition to optimizing per-stage
resolution and noise contribution. The top-level ADC model in-
troduced in Section II is used as a testbench circuit with cir-
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8 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 11. Worst-case INL versus 6 from behavioral simulations.
TABLE VI
DESIGN SPECIFICATION FOR 8-bit 400 M ADC
cuit-level model described in Appendix B. It has previously
been shown that the total power dissipation and input-referred
SNR of such a top-level pipelined ADC model is compatible
with GP optimization [20]. Equation (13) is added to the ADC
model in order to enable gain error optimization. The ADC
model is optimized for minimum power dissipation with the de-
sign specifications shown in Table VI, where the specifications
are chosen for a two-way interleaved 8-bit 400 MS/s ADC. Note
that optimizing the top-level model allows us to explore not only
the optimal distributions of gain errors but optimal stage reso-
lution and sampling capacitance while individually optimizing
the transistor-level device sizing and biasing.
Several design optimization have been performed. First, to
determine an optimal per-stage resolution, the model is iter-
atively optimized for various choices of per-stage resolution
whose sum equals to 8-bit, i.e., , where we consider
either 1- or 2-bit for the internal stage resolution for simplicity.
Twelve such candidates are listed in Table VII, where the th
component of is the resolution of th stage. Fig. 12 shows
the optimized power dissipation for the corresponding choice
of per-stage resolutions, where the number in the horizontal
axis is the index of vectors in Table VII. Several interpre-
tations can be made from Fig. 12. First, the comparison indi-
cates that a minimum power dissipation is obtained for
, which is the optimal case. Second, resolving
two-bits in the first stage in general leads to lower-power dissi-
pation (3–8, 10, 12 versus others in terms of index), which
agrees with a common design practice [21]. Third, however,
the bit distribution among the rest of the stages still has signif-
icant impact on the power dissipation, causing up to 2 dif-
ference (e.g., 6 versus 10) in the total power dissipation. Note
that one may opt for a non-optimal for other considerations
such as layout or required design effort. For instance, choosing
can result in a more compact layout
Fig. 12. Optimal power dissipation versus various bit-per-stage selections for
8-bit total resolution.
TABLE VII
POSSIBLE B FOR 8-bit RESOLUTION
without significantly demanding more power dissipation than
the optimal case.
Fig. 12 also shows how much power benefit can result from
having individual supply domains for each stage as opposed to
a shared and across all stages. When comparing
the result between individual and shared supplies , the
sharing causes only 6% power penalty at the optimal case.
Therefore, the benefit is not considerable given the added
design complexity.
With the optimal per-stage resolution of , we specifically
explored the benefit of the proposed gain error optimization via
comparative design optimizations. Two scenarios of design op-
timization have been performed. The first case is when the ADC
model is optimized while uniformly preassigning stage gain
error to be 0.2 LSB of remaining stage resolution. The second
case is when the stage gain error is optimally chosen by the pro-
posed approach. Shown in Table VIII, the result indicates that
the error of the T/H and first stage in the proposed approach can
be relaxed by and , re-
spectively, while achieving similar total linearity performance
(simulated of 0.23LSB versus 0.3LSB) by assigning
more stringent gain error in the rest of the stages. This optimal
balancing leads to significant power saving compared to uni-
formly-assigned gain error case (31 mW versus 12.12 mW). In-
tuitively, the net power reduction shown in Table VIII agrees
with the observation made in Section IV-A. The power-perfor-
mance tradeoff in the T/H and first stage is very tight, therefore
relaxing the tradeoff leads to substantial power reduction. On
the other hand, tightening the tradeoff in the rest of the stages
incurs insignificant power cost.
The error partition between and in the Table VIII
also merits an attention. For most stages, the finite opamp gain
contributes more error than the incomplete settling (e.g., 79%
versus 21% in T/H). For the speed and resolution specification
of our design, the marginal power cost to reduce settling time is
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KIM et al.: MULTILEVEL POWER OPTIMIZATION OF PIPELINED A/D CONVERTERS
TABLE VIII
COMPARISON FOR GAIN ERROR OPTIMIZATION
Fig. 13. Top-level ADC architecture.
cheaper than an increase in the open-loop gain, which reflects
the difficulty of achieving high open-loop gain in sub-microm-
eter technology.
V. CHIP IMPLEMENTATION
The proposed design optimizations have been applied to im-
plement a low-power 8-bit 320 MS/s pipelined ADC in 90-nm
CMOS technology. This section describes the architecture and
circuit-level details of the design.
A. Architecture-Level Design
The architecture of the ADC is shown in Fig. 13. The ADC
is organized in two slices, each consisting of an input T/H and
pipelined ADC running at 160 Ms/s. The T/H is a standard
flip-around architecture that employs a bootstrapped clock for
the tracking switch. The first stage in the ADC slice is a 2.8-bit
stage, followed by three 1.5-bit stages. The backend stage is
a 3-bit flash converter. A 640 MHz input clock is twice-di-
vided to generate a low-jitter 160 MHz clock, which subse-
quently drives per-stage non-overlapping clock generators that
are shared by both channels. Raw digital outputs from stage
ADCs are combined by two levels of 2-to-1 multiplexers, gen-
erating eight output streams each at 640 Mb/s that are collected
by an off-chip logic analyzer for further analysis.
Shown in Fig. 14 is the stage power and sampling capacitor
scaling adopted in the design. The largest power is assigned to
stage-1 that resolves the two most significant bits, followed by
a rapid power and capacitor scaling from stage-1 to stage-2 to
reduce capacitive load to stage-1. There is essentially no power
scaling from stage-2 to stage-3 because these stages are more
9
Fig. 14. Stage power and sampling capacitance scaling.
tightly designed in terms of gain error and noise, and stage-4
also dissipates as much power due to substantial input capaci-
tance arising from seven 1-bit flash slices in the 3-bit backend
flash converter. The capacitance scales up from T/H to stage-1
because there is no gain in the track-and-hold stage therefore
noise contributions from stage-1 and T/H are equally weighted.
Given that the feedback factor in the T/H is close to 1, it can
still be designed with low power while driving a large capaci-
tive load from stage-1.
B. Stage-Level Design
A standard flip-around MDAC is used to implement all
pipeline stages. A telescopic opamp in Fig. 7(b) with optimized
device type in Table II is used as the stage amplifier. Chosen by
the design optimization described in Section III-B, 2.1
V and 1.2 V with 0.8 V minimize the total
power dissipation while meeting the given SNR requirement
for an 8-bit ADC. Compared to the analysis in Section III-C
that only considers T/H stage, optimal is higher (2.1
V versus 1.73 V) while optimal swing is smaller (0.8
V versus 1.23 V). The selection may look contradictory, but
the 1st stage MDAC that resolves 2-bits puts more stringent
gain-error requirement than T/H due to the reduced ( 0.25 as
opposed to 1 in T/H) feedback factor, favoring higher supply
voltage and smaller signal swing to maximize open-loop gain
and minimize time constant.
Note that while 2.1 V is higher than nominal supply voltage
of a 90-nm CMOS process, the design ensures that none of the
circuit components are stressed beyond its designated voltage
limits under all operating conditions. Specifically, single-ended
voltage range at the output node of the telescopic opamp is be-
tween 0.8 and 1.2 V along with input common-mode voltage of
0.6 V. Therefore, top pMOS transistors ( and in Fig. 7)
experience 1.3 V of combined headroom, or 0.65 V of
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10 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 15. Dynamic comparator in the stage sub-ADC.

each, in a worst case, not jeopardizing the voltage stress limit.

In the case of stage-1, the simulated performance of the opamp
shows a dc gain of 62 dB and gain error of 0.6% for 208 fF Fig. 16. Die micro-photograph.
of total load capacitance, while dissipating 1.65 mW of static
power.
The sub-ADC in stage-1 comprises of six 1-bit flash slices,
each of which consists of a dynamic comparator preceded by a
switched-capacitor reference generator [22]. The dynamic com-
parator, shown in Fig. 15, adopts the switch in the signal
path to reduce static leakage power. Once the decision is made,
a DEC signal flips from low to high, disconnecting the current
path by closing to reduce the leakage flowing through
and .
Three subsequent stages (stages 2–4) are similarly realized as
1.5-bit stages using same circuit topologies but with individu-
ally optimized sizings. The backend stage is a 3-bit flash con-
verter consisting of seven 1-bit flash slices followed by a ther-
mometer-to-binary encoder. The backend flash converter em-
ploys an additional preamplifier between the reference gener- Fig. 17. Measured DNL and INL.
ator and comparator to reduce the input-referred offset, which
is not corrected by the digital redundancy built in the internal
is attributed to the nonlinearity in the front-end track-and-hold
stages.
amplifier. Fig. 19 shows SNDR for different sampling rates with
an 154.7 MHz sinusoidal input. The measured SNDR stays rel-
VI. EXPERIMENTAL RESULT atively constant up to 320 MHz and rolls off to 41.3 dB, which
The prototype ADC has been fabricated in a 90-nm eight- is below 7-bit of ENOB, at 360 MHz. While the design opti-
metal one-poly digital CMOS process. A micro-photograph of mization has been performed for target frequency of 400 MHz,
the implemented chip is shown in Fig. 16, where the ADC core the ADC model used in the optimization did not properly ac-
occupies a silicon area of 750 m 700 m. count parasitic capacitance in the signal path, resulting in mea-
Fig. 17 shows the DNL and INL obtained from a code den- sured ENOB of 7-bit up to 80% of the target speed. For future
sity test. Total 819000 data samples are collected for a low-fre- designs, the ADC model can be modified to include extracted
quency sinusoid input to generate the linearity profile. The mea- parasitic capacitance to yield more accurate performance pre-
sured DNL and INL are 0.45 0.35 LSB and 0.89 0.72 diction.
LSB, respectively. Fig. 20 shows the output spectrum when the input sinusoid is
The dynamic performance of the ADC has been measured at 154.7 MHz. The amplitude of input sinusoid is 0.3 dB below
by sweeping the frequency of an input sinusoid from near dc full-scale. The largest spur is the third-order distortion at a level
to the Nyquist frequency 160 MHz . Fig. 18 shows various of 57 dBc. The tone at 5.3 MHz results from
dynamic performance metrics over different input frequency at the gain mismatch between two interleaved paths at a level of
320 MS/s of sampling rate. The measured peak signal-to-noise 60 dBc. Input-referred offset mismatch also appears at
plus distortion ratio (SNDR) is 46 dB for a low-frequency si- at a level of 60 dBc.4 Note that all the spurs are well-below
nusoid input 3.76 MHz , which is equivalent to 7.35 b of the targeted 8-bit linearity.
effective number of bits (ENOB). Under the same condition, Table IX summarizes the achieved performance and mea-
the peak SNR and spurious-free dynamic range (SFDR) are sured power dissipation of the test chip. Measured total power
47 and 57 dB, respectively. At near-Nyquist input frequency dissipation of the chip is 12.77 mW, excluding digital output
154.7 MHz , the measured SNDR drops down to 45.7 dB, 4Input-referred offset mismatch between two interleaved path has been re-
or 7.3 b of ENOB. The degradation, which is relatively small, moved in the digital domain.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
KIM et al.: MULTILEVEL POWER OPTIMIZATION OF PIPELINED A/D CONVERTERS
Fig. 18. Measured SNDR, SNR, and SFDR versus input frequency.
Fig. 19. Measured SNDR versus various sampling rates.
Fig. 20. Frequency-domain response for near-Nyquist input.
drivers and reference buffers. Out of this, 8.18 mW is con-
sumed by the analog circuits, 0.99 mW by the sub-ADCs,
and 3.60 mW by the clock buffers and nonoverlapping clock
generators, respectively. To compare achieved power-per-
formance metric, commonly referred figure of merit (FOM)
for the ADC performance is calculated, which is defined as
. Fig. 21 compares FOM of the pro-
totype chip (=253 fJ/conv-step) with that of recently published
11
Fig. 21. Comparison of FOM with previously published 8-bit ADCs.
TABLE IX
SUMMARY OF PROTOTYPE ADC
8-bit pipelined converters with comparable sampling-speed.5 6
The comparison indicates that proposed power optimization
yielded an ADC with one of the best energy efficiency in its
class.
VII. CONCLUSION
This paper demonstrated an analytical design optimization
approach to reduce power dissipation of pipelined ADC. En-
abled by a model-based design optimization method via geo-
metric programming, presented quantitative tradeoff analysis as
well as measured result from a prototype ADC indicates that
substantial power reduction is possible by proposed device-type
and supply voltage selection at the circuit-level and optimal bal-
ancing of per-stage gain error at the architecture-level. Fabri-
cated in 90-nm CMOS technology, a prototype ADC optimized
by proposed design approaches achieves 7.30-bit of ENOB at
Nyquist input running at 320 Ms/s with best in-class power ef-
ficiency of 253 fJ/conv.
Additional contribution of this paper is to demonstrate the
viability of model-based design optimization for analog and
5We only compared 8-bit ADCs in 90-nm or older generations. It has been
reported that an 8-bit ADCs in 65 nm such as [23] achieves similar conversion
efficiency as this design.
6Power dissipaton of the reference buffer is 5.6 mW, and it was not intended
to be optimized by proposed design approaches.
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12 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

mixed-signal circuits. While demonstrated for a pipelined ADC comparator. The circuit topology of the comparator is shown
design, the same approach can be applicable to a general class in Fig. 15.
of analog and mixed-signal building blocks. When combined A) Model Variables: The circuit-level model considers fol-
with analytical power optimization approach of digital circuits, lowing variables. Note that transistors in differential-symmetry
it will up the possibility of a truly global power optimization such as and are identically sized.
of complex mixed-signal VLSI driven from the top-level design • The width and length of all transistors: and
specification. .
• The and current of all transistor: and
APPENDIX A .
CIRCUIT OPTIMIZAITON VIA GP • The width of all switches: .7
Circuit optimization via geometric programming (GP) is a de- • The scaling factor for sub-ADC : .
sign methodology that has been gaining interest to optimize var- • The analog and digital supply voltages: and
ious mixed-signal circuit systems [14], [29]. The central idea is Here, is a total number of the switches in the stage, which
to develop a circuit model that captures design constraints for a depends on the resolution of the stage. Switches are either
predefined circuit topology, but the model has to be formulated pMOS or complementary depending on the signal range they
using special set of functions called posynomial and monomial. handle. The sub-ADC model is a simplified model that has a
Posynomial functions are real-valued functions of real, pos- single scaling variable, .
itive variable with nonnegative coefficients and any B) MDAC Model: The subscript in the transistor-level pa-
real exponents , i.e., rameters in this section refers to the transistor designator, e.g.,
is a gate-drain overlap capacitance of transistor in
Fig. 7(b).
(14)
• Power: is comprised of analog power dissipated in
opamp and digital power consumed in the switches
Posynomials are closed under addition, multiplication, and
nonnegative scaling. Monomial is a special case of a single-term (17)
posynomial, i.e.,
where is a summation of total active capacitance
(15) from all the switches.
• Terminal capacitance: The input capacitance at the sam-
Note that monomial is closed under division while posynomial pling phase is dominated by the sampling capacitor, i.e.,
is not.
GP is an optimization problem that has the following format: (18)

minimize The output capacitance due to self-loading can be ex-

subject to pressed as sum of parasitic capacitance, i.e.,

(19)
(16)
• Bias constraints: KCL dictates the relation between bias
where are posynomial functions and are monomial current of transistors, i.e.,
functions. Once a circuit model is formulated in the form of (3),
the model can be optimized for desired performance specifica- (20)
tions and an objective value over process corners to yield an
optimized circuit netlist. Limitations such as inability to handle Also, the summation of drain-to-source voltages of stacked
all functional forms can be alleviated by incorporating some it- transistors must be less than the supply voltage
erative or condensation methods. The important feature of GP
is that: 1) large problems can be very efficiently solved and 2) (21)
the obtained solution is globally optimal, enabling an efficient
exploration of globally-optimal design tradeoffs. Here, is the drain-to-source voltage with balanced in-
puts, or zero differential voltage.
APPENDIX B The transistors in the opamp must be in saturation region
CIRCUIT-LEVEL MODEL at the full-swing condition. This is particularly critical to
and which experience a large voltage excursion at
This appendix describes the circuit models used in the their drains. This condition translates into following design
pipeline stage in this paper. A particular circuit topology constraint
used in the MDAC is a fully-differential switched-capac-
itor circuit using telescopic opamp as a stage amplifier. The
opamp topology is shown in Fig. 7(b). The sub-ADC consists
(22)
of of 1-bit flash slices where each slice is a
switched-capacitor reference generator followed by a dynamic 7All switches use minimum channel length.
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KIM et al.: MULTILEVEL POWER OPTIMIZATION OF PIPELINED A/D CONVERTERS 13

(34)

• Noise: Input-referred noise power of a telescopic opamp gain of differential mode to that of common-mode. We can
can be modeled as impose a lower bound as

(23) (31)

where is a thermal noise factor. Note the noise contri- or equivalently

butions from cascoding devices and are negligible
(32)
and therefore not included for simplicity.
• Open-loop gain: Ignoring body-effect, the open-loop gain
of telescopic opamp can be approximated by • Switches: On-resistance of the switches must not limit set-
tling response in the amplification phase. It can be com-
(24) monly constrained as

• Phase margin: Phase margin is defined as a total phase shift (33)

in the loop gain subtracted from at gain crossover fre-
quency . The gain crossover frequency of the telescopic
opamp in Fig. 7(b) is approximately expressed as
(25)
We consider only one non-dominant pole arising from node
, which is given by
where is the effective capacitance that a particular
switch charges or discharge. In this model,
is used.
C) Sub-ADC and Transistor-Level Model: An empirical
modeling method has been applied to create GP-compatible
sub-ADC model and transistor-level model in 90-nm CMOS
process. Interested readers are referred to [30].

(26) APPENDIX C
POSYNOMIAL TRANSFORMATION OF THE INPUT-REFERRED
STAGE GAIN ERROR
Because the phase contribution by the dominant pole is
nearly 90 around unity gain bandwidth (assuming the One difficulty in incorporating (13) into the optimization
open-loop gain is larger than 10), the phase margin can then framework is that is not a posynomial function. It is
approximately be given by apparent from (5) that the second term in , or ,
does not conform to posynomial defined in (14). To address
(27) this issue, a posynomial approximation of is created by
a convex piece-wise linear fitting as8 shown in (34) at the top
of the page, where . The numerical error due
Here, we use an approximation of , which is
to this approximation is found to be 10.5% at the worst case
quite accurate for . By using (25) and (27), the
and 5% on average in the domain of and
phase margin can be constrained as
. Not only does this posynomial gain error
model enable optimal distribution of stage gain errors, it also
(28)
determines an optimal error partition between and
in a given stage.
• Slewing: We impose a lower-bound on the slew rate so that
the settling behavior is close to the ideal linear settling. The REFERENCES
slew rate can be constrained as [1] M. Horowitz, E. Alon, D. Patil, S. Naffziger, and R. Kumar, “Scaling,
power, and the future of CMOS,” in Proc. IEEE Int. Electron Devices
(29) Meet., 2005, pp. 7–15.
[2] K. Nagaraj, H. Fetterman, J. Anidjar, S. Lewis, and R. Renninger, “A
250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with re-
or equivalently duced number of amplifiers,” IEEE J. Solid-State Circuits, vol. 32, no.
3, pp. 312–320, Mar. 1997.
[3] B.-M. Min, P. Kim, F. I. Bowman, D. Boisvert, and A. Aude, “A
(30) 69-mW 10-bit 80-MSample/s pipelined CMOS ADC,” IEEE J.
Solid-State Circuits, vol. 38, no. 12, pp. 2031–2039, Dec. 2003.
• Common-mode rejection: Low-frequency common-mode 8Strictly speaking, (39) is a generalized posynomial, which still can be han-
rejection (CMRR) is defined here as the ratio between dc dled in GP.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
14
[4] J. K. Fiorenza, T. Sepke, P. Holloway, C. G. Sodini, and H.-S. Lee,
“Comparator-based switched-capacitor circuits for scaled CMOS tech-
nologies,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2658–2668,
Dec. 2006.
[5] S. H. Lewis, “Optimizing the stage resolution in pipelined, multistage,
analog-to-digital converters for video-rate applications,” IEEE Trans.
Circuits Syst. II, Analog Digit. Signal Process., vol. 39, no. 8, pp.
516–523, Aug. 1992.
[6] D. Cline and P. Gray, “A power optimized 13-b 5 m samples/s
pipelined analog-to-digital converter in 1.2 m CMOS,” IEEE J.
Solid-State Circuits, vol. 31, no. 3, pp. 294–303, Mar. 1996.
[7] J. Goes, J. Vital, and J. Franca, “Systematic design for optimization
of high-speed self-calibrated pipelined A/D converters,” IEEE Trans.
Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 12, pp.
1513–1526, Dec. 1998.
[8] P. Kwok and H. Luong, “Power optimization for pipeline analog-to-
digital converters,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal
Process., vol. 46, no. 5, pp. 549–553, May 1999.
[9] Y. Chiu, P. Gray, and B. Nikolic, “A 14-b 12-MS/s CMOS pipeline
ADC with over 100-dB SFDR,” IEEE J. Solid-State Circuits, vol. 39,
no. 12, pp. 2139–2151, Dec. 2004.
[10] Y.-T. Chien, D. Chen, J.-H. Lou, G.-K. Ma, R. Rutenbar, and T.
Mukherjee, “Designer-driven topology optimization for pipelined
analog to digital converters,” Proc. Des., Autom. Test Eur., pp.
279–280, 2005.
[11] A. N. Karnicolas, H.-S. Lee, and K. L. Barcrania, “A 15-b 1-Msample/s
digitally self-calibrated pipeline ADC,” IEEE J. Solid-State Circuits,
vol. 28, no. 12, pp. 1207–1215, Dec. 1993.
[12] J. Ming and S. H. Lewis, “An 8-b 80-msample/s pipelined analog-to-
digital converter with background calibration,” IEEE J. Solid-State Cir-
cuits, vol. 36, no. 10, pp. 1489–1497, Oct. 2001.
[13] B. Murmann and B. E. Boser, “A 12-bit 75-MS/s pipelined ADC using
open-loop residue amplification,” IEEE J. Solid-State Circuits, vol. 38,
no. 12, pp. 2040–2050, Dec. 2003.
[14] M. Hershenson, S. P. Boyd, and T. H. Lee, “Optimal design of a CMOS
opamp via geometric programming,” IEEE Trans. Comput.-Aided Des.
Integr. Circuits Syst., vol. 20, no. 1, pp. 1–21, Jan. 2001.
[15] B. Song, M. F. Tompsett, and K. R. Lakshmikumar, “A 12-bit
1-Msample/s capacitor error-averaging pipelined A/D converter,”
IEEE J. Solid-State Circuits, vol. 23, no. 12, pp. 1324–1333, Dec.
1988.
[16] S. Lewis, H. Fetterman, J. Gross, R. Ramachandran, and T.
Viswanathan, “A 10-b 20-msample/s analog-to-digital converter,”
IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 351–358, Mar. 1992.
[17] B. Razavi, Design of Analog CMOS Integrated Circuits. New York:
McGraw Hill, 2000.
[18] D. Buss, B. Evans, J. Bellay, W. Krenik, B. Haroun, D. Leipold, K.
Maggio, J.-Y. Yang, and T. Moise, “SOC CMOS technology for per-
sonal internet products,” IEEE Trans. Electron Devices, vol. 50, no. 3,
pp. 546–556, Mar. 2003.
[19] A.-J. Annema, B. Nauta, R. van Langevelde, and H. Tuinhout, “Analog
circuits in ultra-deep-submicron CMOS,” IEEE J. Solid-State Circuits,
vol. 40, no. 1, pp. 132–143, Jan. 2005.
[20] M. Hershensons, “Design of pipeline analog-to-digital converters via
geometric programming,” in Proc. ICCAD, San Jose, CA, Nov. 2002,
pp. 317–324.
[21] W. Yang, D. Kelly, I. Mehr, M. T. Sayuk, and L. Singer, “A 3-V
340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at
nyquist input,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp.
1931–1936, Dec. 2001.
[22] S. Limotyrakis, S. D. Kulchycki, D. K. Su, and B. A. Wooley, “A
150-MS/s 8-b 71-mW CMOS time-interleaved ADC,” IEEE J. Solid-
State Circuits, vol. 40, no. 5, pp. 1057–1067, May 2005.
[23] W.-H. Tu and T.-H. Kang, “A 1.2 v 30 mW 8b 800 MS/s time-inter-
leaved ADC in 65 nm CMOS,” in Symp. VLSI Circuits Dig. Techn.
Papers, 2008, pp. 72–73.
[24] P. Wu, V.-L. Cheung, and H. Luong, “A 1-V 100-MS/s 8-bit CMOS
switched-opamp pipelined ADC using loading-free architecture,”
IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 730–738, Apr. 2006.
[25] J. Mulder, C. Ward, C.-H. Lin, D. Kruse, M. Westra, J. R. Lugthart, E.
Arslan, R. van de Plassche, K. Bult, and F. van der Goes, “A 21 mW
8b 125MS/s ADC occupying 0.09 mm in 0.13 m CMOS,” in Proc.
IEEE Int. Solid-State Circuits Conf., Feb. 2004, pp. 260–261.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
[26] H.-C. Kim, D.-K. Jeong, and W. Kim, “A 30 mW 8b 200 MS/s
pipelined CMOS ADC using a switched-opamp technique,” in Proc.
IEEE Int. Solid-State Circuits Conf., 2005, pp. 284–598.
[27] L. Brooks and H.-S. Lee, “A zero-crossing-based 8-bit 200 ms/s
pipelined ADC,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp.
2677–2687, Dec. 2007.
[28] Y. Shimizu, S. Murayama, K. Kudoh, and H. Yatsuda, “A split-load
interpolation-amplifier-array 300 ms/s 8b subranging ADC in 90 nm
CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2008, pp.
552–553.
[29] S. Boyd, S.-J. Kim, and S. Mohan, “Geometric programming and its ap-
plications to EDA problems,” Proc. Des., Autom. Test Eur., Nov. 2004.
[30] J. Kim, “Multi-level design optimizations of pipelined A/D converter,”
Ph.D. degree, Dept. Elect. Eng., Univ. California, Los Angeles, 2008.
Jintae Kim (S’02–M’08) was born in Seoul, Korea.
He received the B.S. degree in electrical engineering
from Seoul National University, Seoul, Korea, in
1997, and the M.S. and Ph.D. degrees in electrical
engineering from University of California, Los
Angeles, in 2004 and 2008, respectively.
From 1997 to 2001, he was with Xeline, Seoul,
Korea, designing baseband ICs for high-speed power
line communication. During the summer of 2003 and
2004, he was with Barcelona Design, Sunnyvale, CA,
developing CAD algorithms for analog circuit opti-
mization. Since 2008, he has been with the Mixed-Signal Electronics Depart-
ment, Agilent Technologies, Santa Clara, CA, as a member of technical staff.
His research interests include the design and CAD methodologies of high per-
formance mixed-signal circuits in CMOS.
Dr. Kim was a recipient of the IEEE Solid-State Circuits Predoctoral Fellow-
ship in 2007.
Sotirios Limotyrakis (S’91–M’05) was born in
Athens, Greece, in 1971. He received the B.S.
degree from the National Technical University of
Athens, Athens, Greece, in 1995 and the M.S. and
Ph.D. degrees from Stanford University, Stanford,
CA, in 1997 and 2005, respectively, all in electrical
engineering.
In the Summer of 1993, he was with KDDI
Corporation, Saitama R&D Labs, Saitama, Japan,
working on the design of communication protocols.
During the Summers of 1996 and 1997, he was with
the RF Design Group, Texas Instruments, Inc., R&D Center, Dallas, TX, where
he focused on LNA, RF oscillator design, and GSM transmit architectures. In
November 2004, he joined Atheros Communications, Inc., Santa Clara, CA,
where he is now a Senior Member of the technical staff. His current research
interests include the design of mixed-signal and RF circuits for low-power data
conversion and broadband communications.
Dr. Limotyrakis was a recipient of the W. Burgess Dempster Memorial Fel-
lowship at Stanford University in 1995, the 2004 Analog Devices Outstanding
Student Designer Award, and the corecipient of the 2004 IEEE Beatrice Winner
Award for Editorial Excellence.
Chih-Kong Ken Yang (S’94–M’98–SM’07) was
born in Taipei, Taiwan. He received the B.S. and
M.S. degrees and the Ph.D. degree from Stanford
University, Stanford, CA, in 1992, 1992, and 1998,
respectively, all in electrical engineering.
He joined the University of California at Los
Angeles as an Assistant Professor in 1999 and has
been a Professor since 2009. His current research
interests are high-performance mixed-mode circuit
design for VLSI systems such as clock generation,
highperformance signaling, low-power digital func-
tional blocks, and analog-to-digital conversion