Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
– They transfer:
• Data between registers.
• Data Byte to a register or memory location.
• Data between a memory location and a register.
• Data between an I\O Device and the accumulator.
LXI B 40 00H B 40 00 C
The Memory “Register”
• Most of the instructions of the 8085 can use a
memory location in place of a register.
– The memory location will become the “memory” register M.
• MOV M B
– copy the data from register B into a memory location.
– Which memory location?
• RLC
7 6 5 4 3 2 1 0
Accumulator
Carry Flag
• RAL 7 6 5 4 3 2 1 0
Accumulator
Logical Operations
• Compare
• Compare the contents of a register or memory location with the
contents of the accumulator.
– CMP R/M Compare the contents of the register
or memory location to the contents of
the accumulator.
– CPI # Compare the 8-bit number to the
contents of the accumulator.
• The compare instruction sets the flags (Z, Cy, and S).
– CALL Address
• Jump to the address specified but treat it as a subroutine.
– RET
• Return from a subroutine.
– MVI A, 32
• Operation: MVI A
• Operand: The number 32
• Binary Code:
0011 1110 3E 1st byte.
0011 0010 32 2nd byte.
Instruction with a Memory
Address
• Operation: go to address 2085.
Initialize
Body of loop
No Is this
Final
Count?
Yes
Sample ALP for implementing a loop
Using DCR instruction
MVI C, 15H
LOOP DCR C
JNZ LOOP
Using a Register Pair as a Loop
Counter
• Using a single register, one can repeat a loop for a
maximum count of 255 times.
LXI B, 1000H
LOOP DCX B
MOV A, C
ORA B
JNZ LOOP
Delays
• It was shown in Chapter 2 that each instruction
passes through different combinations of Fetch,
Memory Read, and Memory Write cycles.
• Knowing the combinations of cycles, one can
calculate how long such an instruction would
require to complete.
• The table in Appendix F of the book contains a
column with the title B/M/T.
– B for Number of Bytes
– M for Number of Machine Cycles
– T for Number of T-State.
Delays
• Knowing how many T-States an instruction
requires, and keeping in mind that a T-State is one
clock cycle long, we can calculate the time using
the following formula:
• TO = 7 T-States
– Delay of the MVI instruction
( )
Using a Register Pair as a Loop
Counter
• Using a single register, one can repeat a loop for a
maximum count of 255 times.
• TO = 10 T-States
– The delay for the LXI instruction
( )
Nested Loops Initialize loop 2
Body of loop 2
loop. Is this
No
– In the figure, the body of Final
Count?
loop2 can be before or
Yes
after loop1.
Nested Loops for Delay
• Instead (or in conjunction with) Register Pairs, a
nested loop structure can be used to increase the
total delay produced.
• Total Delay
– TDelay = 57412 X 0.5 Sec = 28.706 mSec
Increasing the delay
• The delay can be further increased by using
register pairs for each of the loop counters
in the nested loops setup.
• It can also be increased by adding dummy
instructions (like NOP) in the body of the
loop.