1.

Floor Planning
1. Define width & height of core & die. Consider dimensions of the standard cells first.
Utilization factor = Net list area/ core area typically .5 or 0.6. Aspect ratio is height/width
2. Identify locations of pre placed cells (Macros /IPs) based on their connectivity with the
complete netlist. Pre placed cells are implemented once and black boxed and re used
multiple places & placed before actual placement and routing so that they are not
touched by PNR tools.
3. Surround the pre placed cells with the de coupling capacitors so that required excess
power is fed by these caps to the pre placed cells during signal transitions.

4. Power planning is done with creating power mesh such that multiple Vdd & Vss lines
arranged in a grid fashion so that logic gates can draw power from nearest point to avoid
voltage droop & ground bounce and so multiple Vdd/Vss pins
5. Pin placement is carried out in the area between die & core and located the respective
logic associated with. Require interaction between front end & back end teams. Clock
pins are bigger to offer least resistance.
6. There is logical cell placement blockage area in which no logic cells are placed (in the pin
area)
2. Placement & Route (Netlist binding & placement optimization)
1. Replace logic gates with the physical gates with actual dimensions. Place the netlist on
the floorplan.
2. Make placement of cells in the appropriate locations such that net connection becomes
easy
3. Optimize the placement by inserting buffers (based on the net length) on the nets so
that signal can reach the respective cell without deterioration
4. Carry out setup time check with ideal clocks after placement is optimized.
5. Data slew (transition) check is carried out (ex between 20ps to 200ps). If the transition is
very less, it leads to huge current demand & lead to power over shoot. If it’s very huge
both PMOS & NMOS are on for longer time and lead to huge short circuit current. When
CMOS output load capacitance CL is high reduces Isc short circuit current??. Should be
used carefully as output transition delay increased in the subsequent stage. Each logic
cell is characterized to operate for a range of input signal transition (min & max slew
rates). If input slew rate falls out of the range, logic gate may not operate as expected.
6. CTS: Insert buffers in the clock path such that clock reaches all the flops at the same
time. Clock buffers are placed to improve clock transition caused by RC delays on clock
tree. Clock buffers have equal rise & fall times.
7. Clock net shielding is the protection of the clock nets from the cross talk. Coupling
capacitance is broken by a shield net which is connected to VDD or GND such that shield
doesn’t switch
8. STA with real clocks is carried out (data paths are not routed at this stage, only clock is
routed) setup equation: C2q+Tc+Launch clk delay + Ts + SU = T clk + Capture clk delay
9. Route the design based on the netlist connectivity such that existing (CTS stage) timing is
not deteriorated.
10. Clean up the DRC. Ex minimum spacing (pitch) between two nets should not be less than
x micron. Width of net should be more than a min value. Via width should be more than
a min value, Via spacing, Signal shorts can be avoided by routing in different metal
layers.
11. Extract complete parasitic in spef. STA with actual net delays

PHYSICAL DEIGN FLOW

•Floorplanning
•Partitioning
•Placement
•Clock-Tree Synthesis (CTS)
•Routing
•Physical Verification
•GDS II Generation