Lecture 5: CMOS

Transistor Theory

Deming Chen

Slides based on the initial set from David Harris

CMOS VLSI Design 4th Ed.

 Outline
 Introduction
 MOS Capacitor
 nMOS I-V Characteristics
 pMOS I-V Characteristics
 Gate and Diffusion Capacitance
 Nonideal Transistor Behavior
– High Field Effects
– Channel Length Modulation
– Threshold Voltage Effects
– Leakage
 Process and Environmental Variations

 Reading 2.1-2.4

CMOS Transistor Theory CMOS VLSI Design 4th Ed. 2

 Introduction
 So far, we have treated transistors as ideal switches
 An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
 Transistor gate, source, drain all have capacitance
– I = C (DV/Dt) -> Dt = (C/I) DV
– Capacitance and current determine speed

CMOS Transistor Theory CMOS VLSI Design 4th Ed. 3

 MOS Capacitor
 Gate and body form MOS
capacitor
 Operating modes
polysilicon gate
V <0
g
silicon dioxide insulator
+

– Accumulation
- p-type body

– Depletion (a)

– Inversion

CMOS Transistor Theory CMOS VLSI Design 4th Ed. 4

 Terminal Voltages
 Mode of operation depends on Vg, Vd, Vs Vg

– Vgs = Vg – Vs Vgs
+ +
Vgd
– Vgd = Vg – Vd - -

– Vds = Vd – Vs = Vgs - Vgd Vs

-
Vds +
Vd

 Source and drain are symmetric diffusion terminals

– By convention, source is terminal at lower voltage
– Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
– Cutoff
– Linear
– Saturation

CMOS Transistor Theory CMOS VLSI Design 4th Ed. 5

 nMOS Cutoff
 No channel
 Ids ≈ 0

Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b

CMOS Transistor Theory CMOS VLSI Design 4th Ed. 6

 nMOS Linear
 Channel forms
 Current flows from d to s
– e from s to d
V > Vt
- gs
+ g +
Vgd = Vgs

- -
 Ids increases with Vds s d
Vds = 0

 Similar to linear resistor

n+ n+

p-type body
b

Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b

CMOS Transistor Theory CMOS VLSI Design 4th Ed. 7

 nMOS Saturation
 Channel pinches off
 Ids independent of Vds
 We say current saturates
 Similar to current source

Vgs > Vt
Vgd < Vt
+ g
+
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b

CMOS Transistor Theory CMOS VLSI Design 4th Ed. 8

 I-V Characteristics
 In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?

CMOS Transistor Theory CMOS VLSI Design 4th Ed. 9

 Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversions
– Gate – oxide – channel
 Qchannel = CV
 C = Cg = eoxWL/tox = CoxWL Cox = eox / tox
 V = Vgc – Vt = (Vgs – Vds/2) – Vt
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, eox = 3.9) p-type body
p-type body

CMOS Transistor Theory CMOS VLSI Design 4th Ed. 10

 Carrier velocity
 Charge is carried by e-
 Electrons are propelled by the lateral electric field
between source and drain
– E = Vds/L
 Carrier velocity v proportional to lateral E-field
– v = mE m called mobility
 Time for carrier to cross channel:
– t=L/v

CMOS Transistor Theory CMOS VLSI Design 4th Ed. 11

 nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds 
t
 mCox
W V  V  Vds V
 gs 2  ds
L  
t

W
  Vgs  Vt  ds Vds
V  = mCox
 2 L

CMOS Transistor Theory CMOS VLSI Design 4th Ed. 12

 nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current

I ds    Vgs  Vt  dsat V
V
2  dsat
 


V  Vt 
2

2
gs

CMOS Transistor Theory CMOS VLSI Design 4th Ed. 13

 nMOS I-V Summary
 Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds     Vgs  Vt   ds linear
 2 

ds dsat

 
Vgs  Vt  Vds  Vdsat saturation
2
 2

CMOS Transistor Theory CMOS VLSI Design 4th Ed. 14

 Example
 Use 0.6 mm process
– From AMI Semiconductor
– tox = 100 Å 2.5
– m = 350 cm2/V*s
Vgs = 5

2
– Vt = 0.7 V 1.5 Vgs = 4

 Plot Ids vs. Vds

Ids (mA)
1
– Vgs = 0, 1, 2, 3, 4, 5 0.5
Vgs = 3

– Use W/L = 4/2 l

Vgs = 2
Vgs = 1
0
0 1 2 3 4 5
 3.9  8.85 1014   W
  m Cox   350  
W  W Vds
   120 μA/V 2
L  100 10  L  L
8

CMOS Transistor Theory CMOS VLSI Design 4th Ed. 15

 pMOS I-V
 All dopings and voltages are inverted for pMOS
– Source is the more positive terminal
 Mobility mp is determined by holes
– Typically 2-3x lower than that of electrons mn
– 120 cm2/V•s in AMI 0.6 mm process
 Thus pMOS must be wider to
0
Vgs = -1
Vgs = -2

provide same current

-0.2
Vgs = -3

– In this class, assume -0.4

Ids (mA)
mn / mp = 2
Vgs = -4

-0.6

Vgs = -5
-0.8
-5 -4 -3 -2 -1 0
Vds

CMOS Transistor Theory CMOS VLSI Design 4th Ed. 16

 Capacitance
 Any two conductors separated by an insulator have
capacitance
 Gate to channel capacitor is very important
– Creates channel charge necessary for operation
 Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is
associated with source/drain diffusion

CMOS Transistor Theory CMOS VLSI Design 4th Ed. 17

 Gate Capacitance
 Approximate channel as connected to source
 Cgs = eoxWL/tox = CoxWL = CpermicronW
 Cpermicron is typically about 2 fF/mm

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, eox = 3.9e0)
p-type body

CMOS Transistor Theory CMOS VLSI Design 4th Ed. 18

 Diffusion Capacitance
 Csb, Cdb
 Undesirable, called parasitic capacitance
 Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg
for contacted diff
– ½ Cg for uncontacted
– Varies with process

CMOS Transistor Theory CMOS VLSI Design 4th Ed. 19

 Ideal Transistor I-V
 Shockley long-channel transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds     Vgs  Vt   ds linear
 2 

ds dsat

 
Vgs  Vt  Vds  Vdsat saturation
2
 2

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 20

Ideal vs. Simulated nMOS I-V Plot
 65 nm IBM process, VDD = 1.0 V

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 21

 ON and OFF Current
 Ion = Ids @ Vgs = Vds = VDD
– Saturation

 Ioff = Ids @ Vgs = 0, Vds = VDD

– Cutoff

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 22

 Electric Fields Effects
 Vertical electric field: Evert = Vgs / tox
– Attracts carriers into channel
– Long channel: Qchannel  Evert
 Lateral electric field: Elat = Vds / L
– Accelerates carriers from drain to source
– Long channel: v = mElat

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 23

 Coffee Analogy
 Tired student runs from ECE425 lab to ECE cafe
 Freshmen are pouring out of the ECE 120 lecture hall
 Vds is how long you have been up
– Your velocity = fatigue × mobility
 Vgs is a wind blowing you against the glass (SiO2) wall
 At high Vgs, you are buffeted against the wall
– Mobility degradation
 At high Vds, you scatter off freshmen, fall down, get up
– Velocity saturation
• Don’t confuse this with the saturation region

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 24

 Threshold Voltage Effects
 Vt is Vgs for which the channel starts to invert
 Ideal models assumed Vt is constant
 Really depends (weakly) on almost everything else:
– Body voltage: Body Effect
– Drain voltage: Drain-Induced Barrier Lowering
– Channel length: Short Channel Effect

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 25

 Body Effect
 Body is a fourth transistor terminal
 Vsb affects the charge required to invert the channel
– Increasing Vs or decreasing Vb increases Vt
Vt  Vt 0  g  fs  Vsb  fs 
 fs = surface potential at threshold
NA
fs  2vT ln
ni
– Depends on doping level NA
– And intrinsic carrier concentration ni
 g = body effect coefficient
tox 2qe si N A
g  2qe si N A 
e ox Cox

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 26

 Body Effect Cont.
 For small source-to-body voltage, treat as linear

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 27

 DIBL
 Electric field from drain affects channel
 More pronounced in small transistors where the
drain is closer to the channel
 Drain-Induced Barrier Lowering
VVV
– Drain voltage also affect Vt
ttds

Vt  Vt  Vds
 High drain voltage causes current to increase.

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 28

 Short Channel Effect
 In small transistors, source/drain depletion regions
extend into the channel
– Impacts the amount of charge required to invert
the channel
– And thus makes Vt a function of channel length
 Short channel effect: Vt increases with L
– Some processes exhibit a reverse short channel
effect in which Vt decreases with L

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 29

 Leakage
 What about current in cutoff?
 Simulated results
 What differs?
– Current doesn’t
go to 0 in cutoff

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 30

 Leakage Sources
 Subthreshold conduction
– Transistors can’t abruptly turn ON or OFF
– Dominant source in contemporary transistors
 Gate leakage
– Tunneling through ultrathin gate dielectric
 Junction leakage
– Reverse-biased PN junction diode current

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 31

 Subthreshold Leakage
 Subthreshold leakage exponential with Vgs
Vgs Vt 0 Vds  kg Vsb
 Vds

I ds  I ds 0 e nvT
 1  e vT 
 
 
 n is process dependent
– typically 1.3-1.7
 Rewrite relative to Ioff on log scale

 S ≈ 100 mV/decade @ room temperature

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 32

 Gate Leakage
 Carriers tunnel thorough very thin gate oxides
 Exponentially sensitive to tox and VDD

– A and B are tech constants

– Greater for electrons
• So nMOS gates leak more
 Negligible for older processes (tox > 20 Å)
From [Song01]

 Critically important at 65 nm and below (tox ≈ 10.5 Å)

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 33

 Temperature Sensitivity
 Increasing temperature
– Reduces mobility
– Reduces Vt
 ION decreases with temperature
 IOFF increases with temperature

I ds

increasing
temperature

Vgs

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 34

 So What?
 So what if transistors are not ideal?
– They still behave like switches.
 But these effects matter for…
– Supply voltage choice
– Logical effort
– Quiescent power consumption
– Pass transistors
– Temperature of operation

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 35

 Parameter Variation
 Transistors have uncertainty in parameters
– Process: Leff, Vt, tox of nMOS and pMOS
– Vary around typical (T) values
 Fast (F)

fast
FF

– Leff: short
SF

TT

– Vt: low

pMOS
– tox: thin
FS
SS

 Slow (S): opposite

slow
slow fast

 Not all parameters are independent

nMOS

for nMOS and pMOS

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 36

 Environmental Variation
 VDD and T also vary in time and space
 Fast:
– VDD: high
– T: low

Corner Voltage Temperature

F 1.98 0C
T 1.8 70 C
S 1.62 125 C

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 37

 Process Corners
 Process corners describe worst case variations
– If a design works in all corners, it will probably
work for any variation.
 Describe corner with four letters (T, F, S)
– nMOS speed
– pMOS speed
– Voltage
– Temperature

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 38

 Important Corners
 Some critical simulation corners include

Purpose nMOS pMOS VDD Temp

Cycle time S S S S

Power F F F F

Subthreshold F F F S
leakage

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 39

 Summary
 Fundamental transistor theory
 Transistors are non-ideal
 Leakage can be a big concern while scaling down
 Also parameter variation is an issue

 Next lecture
– DC & Transient Response
– Readings 2.5, 4.1-4.3

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 40

Backup Slides

CMOS VLSI Design 4th Ed. 41

 Mobility Degradation
 High Evert effectively reduces mobility
– Collisions with oxide interface

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 42

 Velocity Saturation
 At high Elat, carrier velocity rolls off
– Carriers scatter off atoms in silicon lattice
– Velocity reaches vsat
• Electrons: 107 cm/s
• Holes: 8 x 106 cm/s
– Better model

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 43

 Vel Sat I-V Effects
 Ideal transistor ON current increases with VDD2
W Vgs  Vt 
 Vgs  Vt 

2

I ds  mCox
2

L 2 2
 Velocity-saturated ON current increases with VDD

I ds  CoxW Vgs  Vt  vmax

 Real transistors are partially velocity saturated

– Approximate with a-power law model
– Ids  VDDa
– 1 < a < 2 determined empirically (≈ 1.3 for 65 nm)

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 44

 a-Power Model

  Vt 
 0 Vgs  Vt

cutoff 
I dsat  Pc
a
 V V
I ds   I dsat ds Vds  Vdsat 2
gs
linear
Vdsat  Pv Vgs  Vt 
 Vdsat a /2
 I dsat Vds  Vdsat saturation

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 45

Channel Length Modulation
 Reverse-biased p-n junctions form a depletion region
– Region between n and p with no carriers
– Width of depletion Ld region grows with reverse bias
– Leff = L – Ld
GND V V DD DD
Source Gate Drain

 Shorter Leff gives more current

Depletion Region
Width: L d

– Ids increases with Vds n n

– Even in saturation
L
+ L +
eff
p GND bulk Si

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 46

 Chan Length Mod I-V

I ds 

V  Vt  1  lVds 
2

2
gs

 l = channel length modulation coefficient

– not feature size
– Empirically fit to I-V characteristics

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 47

 Junction Leakage
 Reverse-biased p-n junctions have some leakage
– Ordinary diode leakage
– Band-to-band tunneling (BTBT)
– Gate-induced drain leakage (GIDL)

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 48

 Diode Leakage
 Reverse-biased p-n junctions have some leakage
 VvD 
I D  I S  e  1
 
T

 
 At any significant negative diode voltage, ID = -Is
 Is depends on doping levels
– And area and perimeter of diffusion regions
– Typically < 1 fA/mm2 (negligible)

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 49

 Band-to-Band Tunneling
 Tunneling across heavily doped p-n junctions
– Especially sidewall between drain & channel
when halo doping is used to increase Vt
 Increases junction leakage to significant levels

– Xj: sidewall junction depth

– Eg: bandgap voltage
– A, B: tech constants

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 50

Gate-Induced Drain Leakage
 Occurs at overlap between gate and drain
– Most pronounced when drain is at VDD, gate is at
a negative voltage
– Thwarts efforts to reduce subthreshold leakage
using a negative gate voltage

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 51