Experiment 1

Aim: To design and simulate the functionality of logic gates ( IC 7408,7432,7400,7402,7486,7404 )using

Verilog HDL and verify its operation practically.

Tools Required: PC loaded with the Xlinx ISE Design Suite 14

Apparatus: IC Trainer, IC 7408,7432,7400,7402,7486,7404,Patch cards

Procedure:

1. Open the xlinx project navigator.

2. Create new project using the file menu
3. Create a new source file

Note: For file name don’t use inbuilt primitives like and, or etc.
4. Write the program use appropriate modeling

5. Verify the syntax error using check syntax (compilation) and correct those errors

6. Synthesize the program

7. View the RTL schematic

 8. Simulate the program using simulation mode

9. Apply inputs as per truth table

10. Run the Program

11. Verify all the entries in the truth table either by writing test bench or by giving the inputs.

Program:

Dataflow modelling:

module andgate(input A, input B, output Y);

assign Y= A&B;

endmodule
 Gatelevel modeliing:

module andgate (input A, input B, output Y);

and X1(Y,A,B);

endmodule

Note: Similarly , write the program in both gate level and dataflow modeling for the remaining gates and
observe the output.

Pin diagram of logic gates:

Result:Verified the functionality of logic gates practically and by simulation using Verilog HDL.
 Experiment 2

Aim: To desin and simulate the functionality of 3 to 8 decoder (74x138) using Verilog HDL and verify its
operation practically

Tools Required: PC loaded with the Xlinx ISE Design Suite 14

Apparatus: IC Trainer, IC 74x138,Patch cards

Procedure:

1. Open the xlinx project navigator.

2. Create new project using the file menu
3. Create a new source file
4. Write the program use appropriate modeling
5. Verify the syntax error using check syntax (compilation) and correct those errors
6. Synthesize the program
7. View the RTL schematic
8. Simulate the program using simulation mode
9. Apply inputs as per truth table
10. Run the Program
11. Verify all the entries in the truth table either by writing test bench or by giving the inputs.

Program: // Program is given for 2 to 4 decoder, based on this write a program for 3 to 8 decoder as per the
given truth table

(Dataflow modeling)

module decoder2_4(din, dout);

input [1:0] din;

output [3:0] dout;

assign dout[0]=(din==2’b00 ? 1’b1 : 1’b0); // this is conditional statement, if din=00 then dout=1 else dout=0

assign dout[1]=(din==2’b01 ? 1’b1 : 1’b0); // or assign dout[1]=(~din[1])&(~din[0]);

assign dout[2]=(din==2’b10 ? 1’b1 : 1’b0);

assign dout[3]=(din==2’b11 ? 1’b1 : 1’b0);

endmodule

(Gatelevel modeling)

module decoder2_4data( din0,din1,dout0,dout1,dout2,dout3);

input din0,din1;

output dout0,dout1,dout2,dout3;

wire d0bar,d1bar;

not x1(d0bar,din0);

not x2(d1bar,din1);
and x3(dout0,d0bar,d1bar);

and x4(dout1,din0,d1bar);

and x5(dout2,d0bar,din1);

and x6(dout3,din0,din1);

endmodule

Truth table for 2 to 4 decoder

Input(din) Output(dout)
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

3 to 8 decoder -74x138IC pin diagram, Logic diagram, Truth table:

Result: Hence verified the functionality of 3 to 8 decoder practically and by simulation using Verilog HDL
 Experiment-3

Aim: To simulate the functionality of 8x1 multiplexer (74x151) and 2x4 De-Multiplexer (74x155) using
Verilog HDL and verify its operation practically

Tools Required: PC loaded with the Xlinx ISE Design Suite 14

Apparatus: IC Trainer, IC 74x151,74x155, Patch cards

Procedure:

1. Open the xlinx project navigator.

2. Create new project using the file menu
3. Create a new source file
4. Write the program use appropriate modeling
5. Verify the syntax error using check syntax (compilation) and correct those errors
6. Synthesize the program
7. View the RTL schematic
8. Simulate the program using simulation mode
9. Apply inputs as per truth table
10. Run the Program
11. Verify all the entries in the truth table either by writing test bench or by giving the inputs.

Program: write a program for 8x1 multiplexer and 2x4 demultiplexer with inputs and outputs as given in the
truth table (Both dataflow and gate level modelling)

8x1 Multiplexer-74x151IC pin diagram, Logic diagram, Truth table:

2x4 De-Multiplexer-74x155 IC pin diagram, Truth table:

Result: Hence verified the functionality of 8x1 multiplexer and 2x4 demultiplexer practically by simulation
using Verilog HDL.
 Experiment-4

Aim: To simulate the functionality of BCD to Seven segment Decoder (74x49) using Verilog HDL and verify
its operation practically

Tools Required: PC loaded with the Xlinx ISE Design Suite 14

Apparatus: IC Trainer, IC 74x49, Patch cards

Procedure:

1. Open the xlinx project navigator.

2. Create new project using the file menu
3. Create a new source file
4. Write the program use appropriate modeling
5. Verify the syntax error using check syntax (compilation) and correct those errors
6. Synthesize the program
7. View the RTL schematic
8. Simulate the program using simulation mode
9. Apply inputs as per truth table
10. Run the Program
11. Verify all the entries in the truth table either by writing test bench or by giving the inputs.

Program: write a program for BCD to Seven segment decoder with inputs and outputs as given in the truth table
(Both dataflow and gate level modelling)

BCD to Seven segment decoder-74x49 IC pin diagram, Logic diagram, Truth table:
Result: Hence verified the functionality of BCD to Seven segment Decoder practically by simulation using
VerilogHDL.
 Experiment 5

Aim: To simulate the functionality of digital IC 74x85 ( 4 bit comparator ) using Verilog HDL and verify its

operation practically

Tools Required: PC loaded with the Xilinx ISE Design Suite version 14

Apparatus: IC Trainer, IC 74x85,Patch cards

Procedure:
1. Open the xlinx project navigator.
2. Create new project using the file menu
3. Create a new source file
4. Write the program use appropriate modeling
5. Verify the syntax error using check syntax (compilation) and correct those errors
6. Synthesize the program
7. View the RTL schematic
8. Simulate the program using simulation mode
9. Apply inputs as per truth table
10. Run the Program
11. Verify all the entries in the truth table either by writing test bench or by giving the inputs.
Program: write a program for 4-bit comparator with inputs and outputs as given in the truth table
Hints:Key statements using behavioral model

always @ (*)
begin
if (A>B)
begin AgB=1; AlB=0;AeB=0; end

4-bit comparator-74x85 IC pin diagram, Logic diagram, Truth table:

Logic Diagram:

Result: Hence verified the functionality of 4-bit comparator practically and by simulation using VerilogHDL.
 Experiment 6

Aim: To simulate the functionality of digital IC 74x83( 4-Bit Binary Adder) using Verilog HDL and verify its

operation practically

Tools Required: PC loaded with the Xilinx ISE Design Suite version 14.7

Apparatus: IC Trainer, IC 74x83,Patch cards

Procedure:
1. Open the xlinx project navigator.
2. Create new project using the file menu
3. Create a new source file
4. Write the program use appropriate modeling
5. Verify the syntax error using check syntax (compilation) and correct those errors
6. Synthesize the program
7. View the RTL schematic
8. Simulate the program using simulation mode
9. Apply inputs as per truth table
10. Run the Program
11. Verify all the entries in the truth table either by writing test bench or by giving the inputs.

Program: Write a program for 4-bit comparator with inputs and outputs as given in the truth table in behavioral
model
4-Bit binary adder -IC74x83 Pin diagram, Logic diagram, Truth table:

Logic diagram:
Result: Hence verified the functionality of 4-bit binary adder practically and by simulation using VerilogHDL.
 Experiment 7

Aim: To simulate the functionality of digital IC 74x74( D-flip flop) using Verilog HDL and verify its operation

practically

Tools Required: PC loaded with the Xilinx ISE Design Suite version 14.7

Apparatus: IC Trainer, IC 74x74,Patch cards

Procedure:
1. Open the xlinx project navigator.
2. Create new project using the file menu
3. Create a new source file
4. Write the program use appropriate modeling
5. Verify the syntax error using check syntax (compilation) and correct those errors
6. Synthesize the program
7. View the RTL schematic
8. Simulate the program using simulation mode
9. Apply inputs as per truth table
10. Run the Program
11. Verify all the entries in the truth table either by writing test bench or by giving the inputs.
Program: Write a program for D-Flipflop with inputs and outputs as given in the truth table in behavioral model
Hint: use behavioral programming to cover all the cases in truth table.

always @ (*)
begin
if (~pr)
begin Q=1’b1; Q_bar=~Q;end

D-Flipflop-IC74x74 Pin diagram, Logic diagram, Truth table:

Result: Hence verified the functionality of D-Flipflop practically and by simulation using VerilogHDL.
 Experiment-8

Aim: To simulate the functionality of Decade counter (74x90) using Verilog HDL and verify its operation
Tools Required: PC loaded with the Xlinx ISE Design Suite 14
Apparatus: IC Trainer, IC 74x90, Patch cards

Procedure:
1. Open the xlinx project navigator.
2. Create new project using the file menu
3. Create a new source file
4. Write the program use appropriate modeling
5. Verify the syntax error using check syntax (compilation) and correct those errors
6. Synthesize the program
7. View the RTL schematic
8. Simulate the program using simulation mode
9. Apply inputs as per truth table
10. Run the Program
11. Verify all the entries in the truth table either by writing test bench or by giving the inputs.
Program: write a program for Decade counter with inputs and outputs as given in the truth table in behavioral
modeling.
Hint: First, create a module for JK filpflop (use switch case) and then decade counter using this module.
Decade counter-74x90 IC pin diagram, Logic diagram, Truth table:

Result: Hence verified the functionality of Decade counter practically and by simulation using VerilogHDL .
 Experiment-9

Aim: To simulate the functionality of 4-bit counter (74x93) using Verilog HDL and verify its operation
practically

Tools Required: PC loaded with the Xlinx ISE Design Suite 14

Apparatus: IC Trainer, IC 74x93,Patch cards

Procedure:

1. Open the xlinx project navigator.

2. Create new project using the file menu
3. Create a new source file
4. Write the program use appropriate modeling
5. Verify the syntax error using check syntax (compilation) and correct those errors
6. Synthesize the program
7. View the RTL schematic
8. Simulate the program using simulation mode
9. Apply inputs as per truth table
10. Run the Program
11. Verify all the entries in the truth table either by writing test bench or by giving the inputs.

Program: write a program for 4-bit counter with inputs and outputs as given in the truth table in behavioral
modeling

Hint: First create a module for JK filpflop (use switch case) and then 4-bit counter using this module.

4-bit counter-74x93 IC pin diagram, Logic diagram, Truth table:

Result: Hence verified the functionality of 4-bit counter practically and by simulation using VerilogHDL.
 Experiment-10

Aim: To simulate the functionality of Universal shift register (74x195) using Verilog HDL and verify its
operation

Tools Required: PC loaded with the Xlinx ISE Design Suite 14

Apparatus: IC Trainer, IC 74x195, Patch cards

Procedure:

1. Open the xlinx project navigator.

2. Create new project using the file menu
3. Create a new source file
4. Write the program use appropriate modeling
5. Verify the syntax error using check syntax (compilation) and correct those errors
6. Synthesize the program
7. View the RTL schematic
8. Simulate the program using simulation mode
9. Apply inputs as per truth table
10. Run the Program
11. Verify all the entries in the truth table either by writing test bench or by giving the inputs.

Program: write a program for Universal shift register with inputs and outputs as given in the truth table in
behavioral modeling

Hint: First create a module for SR filpflop (use switch case, if else) and then universal shift register using this
module.

Universal shift register-74x195 IC pin diagram, Logic diagram, Truth table:

Result: Hence verified the functionality of universal shift register practically and by simulation using Verilog.
 Additional Experiment-1

Aim: To simulate and verify the functionality of barrel shift register

Tools Required: PC loaded with the Xlinx ISE Design Suite 14

Procedure:

1. Open the xlinx project navigator.

2. Create new project using the file menu
3. Create a new source file
4. Write the program use appropriate modeling
5. Verify the syntax error using check syntax (compilation) and correct those errors
6. Synthesize the program
7. View the RTL schematic
8. Simulate the program using simulation mode
9. Apply inputs as per truth table
10. Run the Program
11. Verify all the entries in the truth table either by writing test bench or by giving the inputs.

Program: write a program for barrel shift register with inputs and outputs as given in the truth table in behavioral
modeling

Truth Table of a Right Rotate 4-Bit Barrel Shifter

‘S’ is a control signal which represents the amount of shift or rotate, ‘W’ are the input vectors and ‘Y’ are the
outputs of an 4 or 8 -bit vector.

Truth Table of a Right Rotate 8-Bit Barrel Shifter

Result: Hence verified the functionality of barrel shift register using verilogHDL.
 Additional Experiment-2

Aim: To simulate and verify the functionality of Priority encoder (74x148)

Tools Required: PC loaded with the Xlinx ISE Design Suite 14

Procedure:

1. Open the xlinx project navigator.

2. Create new project using the file menu
3. Create a new source file
4. Write the program use appropriate modeling
5. Verify the syntax error using check syntax (compilation) and correct those errors
6. Synthesize the program
7. View the RTL schematic
8. Simulate the program using simulation mode
9. Apply inputs as per truth table
10. Run the Program
11. Verify all the entries in the truth table either by writing test bench or by giving the inputs.

Program: write a program for priority encoder with inputs and outputs as given in the truth table in behavioral
modeling.

Priority encoder-74x148 IC pin diagram, Logic diagram, Truth table:

Pin diagram

TRUTH TABLE
Result: Hence verified the functionality of priority encoder by simulation using VerilogHDL.