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Instructor: NguyenVanTuan LabAssitance: VuVanThanh

Table of Contents
I. Introduction ................................................................................................................. 5
II. Architecture Design:.................................................................................................... 6
1. Design Specifications ................................................................................................ 6
1.1. Input signal specifications ............................................................................... 6
1.2. Equipment available for testing ...................................................................... 6
1.3. Minimum Design Specification of the amplifier ............................................. 6
2. Block Diagram ....................................................................................................... 7

3. Discussion on the chosen architecture................................................................. 7

4. Trade offs................................................................................................................ 8
III. Circuit Design: ............................................................................................................. 9
1. Schematics................................................................................................................. 9

2. Explanation for working of each stages ............................................................... 9

2.1 The differential stage .......................................................................................... 9
2.2 The middle stage............................................................................................... 10
2.3 The Darlington stage ......................................................................................... 10
3. Design equations and calculation ...................................................................... 11
3.1. For the Darlington stage ................................................................................ 11
3.2. For the middle stage...................................................................................... 12
3.3. For the differential stage ............................................................................... 14
IV. Conclusion ................................................................................................................... 3
V. References ................................................................................................................... 4
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Instructor: NguyenVanTuan LabAssitance: VuVanThanh

I. Introduction

This design project aims to utilize every single skill we have learned in EE 332 this
quarter. We will use our newly acquired knowledge to build an audio amplifier that
can take the input from a CD player or portable music player and amplify the signal to
drive a loudspeaker. Our design could utilize passive electronic components, discrete
BJT’s, and operational amplifiers.
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Instructor: NguyenVanTuan LabAssitance: VuVanThanh

II. Architecture Design:

1. Design Specifications

1.1. Input signal specifications

 Signal voltage: 0.5VAC.

 Signal source resistance 50 Ω.

1.2. Equipment available for testing

 Hardware: Oscilloscope, DMM, Generator, power supply.
 Software: PSPICE.

1.3. Minimum Design Specification of the amplifier

 Output power: 0.5W (minimum).
 Load Impedance (speaker): 8Ω.
 Unity Gain Bandwidth: 20Hz – 20 kHz (-3dB).
 Idling power: < 1W.
 Distortion: No distortion.
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Instructor: NguyenVanTuan LabAssitance: VuVanThanh

2. Block Diagram

Figure 1: Block Diagram

3. Discussion on the chosen architecture

After some debates, we decided to choose Power amplifier OCL to be the
architecture for our design. The reason behind is the architecture has so many
advantages over other architectures; for example, high efficiency, bandwidth gain,
power using factor, amplitude of output,…

Go deeply into the circuit:

- Choosing BJT bases on the maximum values that match between our
calculation and database. These values must be made sure that we would
have maximum current, voltage and power.
- Choosing diode bases on familiar ones that used in the previous lab and
pre-lab.
- Choosing resistors that must match between the calculation and available
resistors in the market. Moreover, the number of diodes and their connection
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Instructor: NguyenVanTuan LabAssitance: VuVanThanh

in the circuit must bring a guarantee that the transistors will work correctly as
our design in the circuit.
- At the first time, we chose class-AB output stage since it has low output
impedance, high efficiency, reducing distortion… Then, we improve it into
Darlington Amplifier with protecting circuit to increase the safety of circuit in
case unwanted problems occurring.

4. Trade offs
- Using class AB and its improvement (Darlington circuit) instead of class B at
output. The trade off in this case is lower efficiency, but minimized distortion.
- Negative feedback using in this circuit leads the circuit to be more complicated,
but it’s must be safer.
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Instructor: NguyenVanTuan LabAssitance: VuVanThanh

III. Circuit Design:

1. Schematics

Figure 2: Overall Circuit

2. Explanation for working of each stages

2.1 The differential stage

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Instructor: NguyenVanTuan LabAssitance: VuVanThanh

o Q7 is polarized to make the current, which can be adjusted by R8, stable;

and adjusted power for the middle point to be equal 0.
o Q8 and Q9 severed for differential circuit, made circuit stable.
o Q10 and Q11 made minor current.
o C2 used for short circuit in AC mode.
o R9 and R10 polarized for Q8 and Q9, and removed high frequency
signals in AC mode.
o R11 and R12 polarized for Q10 and Q11, controlled Q6, and determined
current ratio for minor part Q10 and Q11.
o R13 and R14 determine gain. R13 polarized for Q8 in DC mode.
o R15 polarized for Q9 in DC mode.

2.2 The middle stage

o D4 and D5 create difference voltage 2VD to polarize Q5 to create current in E of

Q5. This current can be adjusted thank to R6.
o R5 makes forward bias for D4 and D5
o D1, D2, D3, and R7 used to get bias voltage for Darlington circuit (work
in AB stage).
o Q6 created output that is changed 360o with input.

2.3 The Darlington stage

When input signal is in positive half:


 VBE of Q3 increases
=>Q3 is forward bias.
Then, the current goes
into B of Q1 => Q1 is
forward bias => current
goes through +VCC to
Speaker and to mass.
 In this case, Q4 is inverse bias=> Q2 doesn’t draw current.

When input signal is in negative half:

 VBE of Q4 decreases => Q4 is forward bias. Then, the current withdraw

of Q2 => Q2 is forward bias => current goes from mass to Speaker to

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Instructor: NguyenVanTuan LabAssitance: VuVanThanh

−V .

.
 In this case, Q3 is inverse bias=> Q1 doesn’t work.

3. Design equations and calculation

3.1. For the Darlington stage

2
 IL  VL2  RL
3W  PL    RL  2
 2  2  R1  RL 

We choose R1≪ L, which is R1 = 0.5Ω => because it should be received

this value to satisfy the requirement of Darlington circuit.

Unfortunately, in the market, we just find the minimum resistor, which is

0.68 Ω. Hence, in our circuit, R1 = R2 = 0.68 Ω.
Then, VL  2 PL ( RL  R1 )  2  3  8.68  7.22V

VL 7.22
IL    0.83 A
RL  R1 0.68  8
VPL 7.22
With   0.8 , VCC    9.025V
 0.8

=>We choose VCC = 10V, and VEE = -10V

2
2VCC
PCC   7.33W
 ( RL  R1 )

I EQ1  0.05 A (Darlington Circuit)

I R1  0.05  0.83  0.88 A

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Instructor: NguyenVanTuan LabAssitance: VuVanThanh

1
PR1  0.882  0.68  0.26W
2
PQ1  PCC  PL  PR1  7.33  3  0.26  4.07W

Value of BJT Q1 should be as follow:

+) P  4.7W
+) VCE  2VCC
+) I C max  2 I C  2  0.88  1.76 A
Hence, using datasheet, we choose: Q1= 2 2073
2 = 2 940
I CQ 1 0.88
One has: I C Q 1  0.88 A  I BQ 1    12 m A
h feC 2073 75
To protect Q1 and Q2, as well as make Q3 and Q4 stable, we add R3 and R4 into the
circuit.
I BQ1
We choose: I R 3, R 4   1.2mA
10
 I EQ 2  12  1.2  13.2mA
Choose R3=R4=220Ω
,
ℎ
ℎ ℎ , ℎ 3 = 2 2073
4 = 2 940

3.2. For the middle stage

Since diode D1, D2, D3, D4, D5 work with small current, we choose
D1= D2=D3=D4=D5=D1N4007

Characteristics of D1N4007 is:

+) I  1A
D max

+) V  0.7V
D at I D  10mA
VCC  2VD
Choose R5: R5   860
ID
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Instructor: NguyenVanTuan LabAssitance: VuVanThanh

Hence, we choose R5=1kΩ

VR 5  VCC  2VD  8.6V
VEQ 5  VR 5  VD  VCC  19.3V
To get I EQ 6  4  15mA
VD V
R6min   47 and R 6 max  D  175
15mA 4mA
Hence, choose R6=100Ω
Vbias  VBEQ1  VBEQ 2  VBEQ 3  VBEQ 4  4  0.6  2.4V
Vbias _ max  4  0.7  2.8V
With ID = 10mA and Vbias = 2.4÷2.8V, one has:
V  3VD Vbias _ max  3VD
R7 min  bias _ min  30 and R 7 max   100
10mA 10mA
Hence, choose R7=75Ω
one has: I CQ 5  I CQ 6
then, 2VDD  VR 6  VECQ 5  3VD  VR 7  VECQ 6
2VDD  VECQ 5  3VD  VECQ 6
IQ 
R6  R7

Total current goes through Q5 is:

I CQ 5  I CQ 5  I CQ 5
dc ac

I EQ 5 13.2
Since we need I CQ 5  I B _ Q 3_ max    0.17 mA
75  1 75  1
While a diode needs VD = 0.7V at ID = 10mA for polarizing
hence, I CQ 5  10  0.17  10.17mA
choose quite point of Q5 is Q(10mA, 10V)
VCEQ 5  VEQ 5  (VECQ 6  Vbias _ max )  19.3  (10  2.8)  6.5
PCQ 5  I CQ 5  VCQ 5  (0.17 mA)(6.5V )  1.105mW
PCQ 6  I CQ 6  VCQ 6  (0.17 mA)(10V )  1.7mW
Values of BJT Q5 and Q6 should be satisfied:
+) P>2 x 17mW = 3.4mW
+) VCE > 2VCC = 20V
+)ICmax > 2IC = 2 x 10mA =20mA
Hence, using datasheet, we choose: Q5=2SA940; Q6=Q2SC2073
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Instructor: NguyenVanTuan LabAssitance: VuVanThanh

3.3. For the differential stage

The differential stage has function of reduce noise in the changing noise.
Combining with negative feedback from Darlington circuit (third stage), this first
stage play a very important role in quality of amplifier.

From previous calculation, one has:

I BQ 6  ICQ 3 75  0.17mA 75  2.27  A

For the differential circuit works stably,
ICQ11  I BQ 6 , then, we can neglect I B
Q6

Hence, I EQ11  I CQ11  75I BQ 6  0.17mA

and I C9  I CQ11  I BQ 6  0.17mA

from VthQ11  I EQ11  R12  VthQ10  I EQ10  R11

for I CQ 8  I CQ 9  I CQ10  I CQ11 happens, R11=R12
the same explanation, one gets: R9=R10

I CQ 7  I EQ 8  I EQ 9  2  0.17mA  0.34mA
For I CQ 7 ranging from 1mA to 10mA,
VD V
R8min   1k  and R8max  D  10k 
10mA 1mA
hence, we choose R8=1.5kΩ

Values of BJT Q7, Q8, Q9, Q10 and Q11 should be satisfied:
+)PQ8 = PQ9 >0.17mA x 10V=1.7mW
+)PQ7 > 2PQ8 =3.4mW
+)ICmax > 2IC_Q9 =2 x 0.17mA = 3.4mA
We also have the two pairs, Q9 and Q11; Q8 and Q10 are complement together
Hence, using datasheet, we choose: Q7=Q8=Q9=Q2SA1015
Q10=Q11=Q2N3904

The rest components are chosen based on the previous

lab in this course.