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Published in IET Power Electronics
Received on 14th March 2013
Revised on 29th August 2013
Accepted on 26th October 2013
doi: 10.1049/iet-pel.2013.0182

ISSN 1755-4535

Predictive modulation schemes to reduce

common-mode voltage in three-phase
inverters-fed AC drive systems
Seyed Kazem Hoseini, Jafar Adabi, Abdolreza Sheikholeslami
Faculty of Electrical and Computer Engineering, Babol (Noshirvani) University of Technology, P.O. Box 47135-484,
Babol 47144, Iran
E-mail: k.hoseini@stu.nit.ac.ir; hoseini.elc@gmail.com

Abstract: Pulse width modulation controlled inverters produce common-mode voltage, which has been reported to cause many
system drawbacks. This voltage along with high dv/dt raises leakage currents which can result in serious problems such as motor
damage and electromagnetic interference to the surrounding equipment. Also common-mode voltage is responsible for bearing
failure and overvoltage stress to the winding insulation of an AC motor. Therefore knowledge of reducing common-mode voltage
is essential to provide a correct insight into the design of the drive system. Previous methods for common-mode voltage reduction
cause extra harmonic in output currents, since they are based on voltage control. This study proposes new modulation strategies
based on predictive current control (PCC) for three-phase pulse width modulation inverters-fed AC motor drive systems which
mitigate the common-mode voltage and moreover, decrease the harmonic contents of output currents. As PCC can be employed in
low voltage and medium voltage drive applications, the proposed strategies have been implemented on two-level and three-level
neutral-point clamped inverter. A comparative study of proposed techniques with traditional ones has been carried out from the
output current total harmonic distortion point of view. Simulation results and mathematical analyses, along with experimental
tests for two-level inverter using Texas Instrument DSP model TMS320F28335, confirm that the new strategies improve
behavior of drive systems in comparison with previous methods.

1 Introduction CMV causes some unwanted drawbacks. Fig. 1b shows the

Motor drives are used in a very large range of power, from a
few watts to thousands of kilowatts, in broad applications
such as pumps, textile and paper mills, elevators, cement
and steel mills, robotics, and so on. In drive systems, pulse
width modulation (PWM) inverters are widely used as an
interface between input and motor to control the speed and
position efficiently [1]. A typical motor drive system is
shown in Fig. 1a.
Development of power electronics switching devices such
as MOSFETs and IGBTs has led to high speed operation of
PWM inverters and therefore, improvement of their
performance. However, these developments have increased
adverse effects of PWM inverters. Common-mode voltage
(CMV) appears as a voltage between the neutral point of
the load (node n in Fig. 1a) and the system ground (node
g in Fig. 1a), that is, Vng. This can be decomposed into
Vno (the voltage from the motor neutral point to the
DC-link midpoint) and Vog (the voltage from the DC-link
midpoint to the system ground). Vog` depends on the
grounding and connection of the input transformer [2]. In
three-phase applications of PWM inverters, because of
asymmetrical output pulses, Vno is produced during
switching action of the PWM inverter and hence, can be
controlled by the applied modulation scheme.
structure of an AC motor together with the parasitic capacitive
couplings (r, s, f, and b stand for rotor, stator, frame and
bearing, respectively). High dVng/dt generates currents
flowing to earth through parasitic capacitors (which are
more significant in high frequencies) inside motor [3].
These currents may have an unpleasant impact on the motor
current control and also produce electromagnetic
interference (EMI) which probably leads to undesirable
performance of peripheral electronic devices [4].
Furthermore, CMV induces a voltage across the shaft of
motor, which is known as shaft voltage, through
electrostatic couplings between the rotor and stator
windings (Crs), and the rotor and the frame (Crf ), as shown
in Fig. 1c. The relationship between CMV and shaft voltage
can be obtained as
Crs
Vshaft = × Vng (1)
Cb + Crs + Crf
Shaft voltage leads to bearing currents which have been found
the major cause of premature failure of motor’s bearings
[5, 6]. In order to reduce the bearing currents, we need to
lower the magnitude of Vng as well as dVng/dt [7–9]. Thus,
CMV is an important factor in designing and development

840 IET Power Electron., 2014, Vol. 7, Iss. 4, pp. 840–849

& The Institution of Engineering and Technology 2014 doi: 10.1049/iet-pel.2013.0182
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One of the important control methods for three-phase
PWM inverters in adjustable speed drives is current control
which improves their dynamic performance. The major
objective of the current control is to track the desired
current in different intervals. The three main schemes for
the current control are ramp comparison control, hysteresis
control [20, 21], and predictive control [22–26]. In
hysteresis current control, despite fast response, good
accuracy, and simplicity, the switching frequency is variant
which is its main disadvantage and causes changes in the
load parameters and operating conditions. Predictive current
control (PCC) uses converter and load models to predict
behavior of the current and can result in precise current
control, minimum current ripple, and very low current error.
Recently, a feature of PCC has been used to control the
CMV in power electronic converters [27]. Although
implementation of predictive control is difficult and requires
more calculations, with the development of powerful and
fast microprocessors, such as DSPs, the use of PCC is
increasingly increased.
This paper presents new techniques based on PCC to
mitigate CMV in three-phase PWM inverters. These
techniques have been applied on two-level and three-level
neutral-point clamped (NPC) inverter. The simulation and
experimental results illustrate the superiority of the
proposed strategies, and the system has better performance
than that of the traditional ones for CMV reduction.

2 Load model
As can be seen from Fig. 1a, ia, ib, and ic are three-phase
currents of the induction motor. The phase voltages of
inverter Van, Vbn, and Vcn fed an induction motor can be
calculated as follows
⎧
⎪ di
⎪
⎪ Van = Vao − Vno = Ria + L a + ea
⎪
⎪ dt
⎨
dib
Vbn = Vbo − Vno = Rib + L + eb (2)
Fig. 1 Typical motor drive system ⎪
⎪ dt
⎪
⎪
a Power electronic motor drive system ⎪
⎩ V = V − V = Ri + L dic + e
b Capacitive coupling in induction motor cn co no c c
c Shaft voltage generated by CMV through parasitic capacitances dt

where R and L are per phase equivalent resistance and leakage

inductance of motor, respectively, and, ea, eb, and ec are
of AC drives which attracted many investigations by
back-EMF of motor. Adding the both sides of (2), the
researchers and industries.
following equation is achieved
Recently, many studies have been done to reduce CMV and
consequently reduce the associated problems, and many  
di 
methods have been proposed which can be divided into two Vao + Vbo + Vco = 3.Vno + R + L . ia + ib + ic
groups. One is to change physical structure, such as four-leg dt (3)
inverter [10], dual bridge inverter [11], passive filters [12] or + ea + eb + ec
active filters [13], and etc, which needs extra cost and size,
and also is not suitable for high voltage or large capacity
systems. Another cheap and appropriate method for CMV since sum of phase currents for a balanced three-phase load is
reduction is to improve control algorithm. In this method, in zero, that is, ia + ib + ic = 0, and, ea + eb + ec = 0
order to reduce or eliminate CMV, different PWM 
modulation techniques are used which are based on selection Vno = Vao + Vbo + Vco /3 (4)
of non-zero vectors in two-level three-phase PWM inverters
[14, 15], and in multilevel PWM inverters the basic idea is where Vno is the voltage between neutral point of the load and
to choose vectors that produce zero or the lowest levels of DC-link midpoint which is referred to as CMV in the
CMV [2, 16–19]. These PWM modulation techniques that remainder of this paper.
have ever been proposed were based on voltage control, and
since some of voltage vectors are eliminated in order to 3 Proposed CMV reduction strategies
achieve desired CMV, these methods decrease the quality of
output waveforms of PWM inverters [unacceptable output As mentioned earlier, cancelling some switching states to
currents total harmonic distortion (THD)]. suppress/reduce CMV considerably affects the quality of

IET Power Electron., 2014, Vol. 7, Iss. 4, pp. 840–849 841

doi: 10.1049/iet-pel.2013.0182 & The Institution of Engineering and Technology 2014
www.ietdl.org
resulting output currents. To solve the problem, this work
uses PCC-based modulation strategies. The principle of
PCC is to force the output currents to follow the reference
currents by using the measured inverter output voltages and
currents. Since in conventional PCC each phase is
controlled separately, all switching vectors might be used in
different switching intervals, therefore, it cannot be used to
eliminate required switching states and their resultant CMV
levels. Thus, the proposed PCC based modulation strategies
are developed in the αβ frame to improve the current
control performance. Using Clark transformation
⎛ 1 1⎞
1 − − achieve the reference current, as shown in Fig. 2b for a
 ⎜ √2
(3) The average voltages are applied to a symmetrical SVM to
constitute the output voltages.
(4) The undesirable CMV levels can be eliminated without
using their relevant switching states in SVM scheme.
For a desired reference current, the proposed modulation
strategy proceeds as a PCC method and predefined
equations are used to choose the inverter switching states.
Block diagram of the proposed strategy is illustrated in
Fig. 2a. The outputs from the PCC, V
a and V
b , are the
inputs for the SVM to produce the signals for the switches.
The proposed predictive SVM strategy combines various
switching states of the inverter within one PWM period to

√
2
⎟
2 ⎜⎜ 3 3⎟
⎟ seven-segment switching sequence. Va and Vb are
Ks = .⎜ − ⎟ (5)
3 ⎜0 2 2 ⎟
the voltage vectors that surround the sector in which
⎝ ⎠ reference voltage falls, and Vx and Vy are the sector’s
1 1 1
neighbor voltage vectors. Therefore the phase currents are
2 2 2 forced to follow the reference currents with reasonable
accuracy which makes the harmonic contents be decreased.
the equations of three-phase inverter (2) can be transformed
into αβ
3.2 Error minimisation
⎧
⎪ di
⎨ Vb = R.ib + L b + eb Generally, PCC scheme uses load model to predict the output
dt (6) quantities of the inverter. The objective of this method for
⎪ di
⎩ V = R.i + L a + e CMV reduction is to select appropriate switching state so
a a a that the error between the load current and reference current
dt

where Vβ and Vα are output voltages in β-axis and α-axis;

iβ and iα are output currents in β-axis and α-axis.
It should be mentioned that αβ equations are identical to
those of three-phase, thus, the control of three-phase
inverter can be greatly simplified. Proposed strategies aim
to mitigate the CMV and consequently decrease the
associated adverse effects.

3.1 SVM-Based PCC

PCC based on SVM are widely used in three-phase inverters

which can benefit the advantages of both schemes [24]. In this
method, to compensate current error, a PCC algorithm is
developed to predict the average reference voltage for SVM
so that the output currents can reach its references in one
PWM period. The discrete-time model of (6) can be written as
⎧  
⎪
⎪ i ∗
(k + 1) − i (k)
⎪
⎪ b b
⎨ Vb (k) = R.ib (k) + L + eb (k)
Ts
⎪  (7)
⎪
⎪
⎪ i∗a (k + 1) − ia (k)
⎩ V a (k) = R.ia (k) + L + ea (k)
Ts

where i∗b (k + 1) and i∗a (k + 1) are current references at the end

of the next sample time, and V
b (k) and V
a (k) are required
average voltages for the next sample time, and iβ(k) and
iα(k) are load currents at the end of present sample. Thus,
V
b (k) and V
a (k) should be applied in order to reach
reference currents i∗b (k + 1) and i∗a (k + 1) at the end of the
next sample time. This strategy can be summarised in
following steps:

(1) Load currents at the end of present sample time, iβ(k) and
iα(k), are measured and current references at the end of the
next sample time, i∗b (k + 1) and i∗a (k + 1), are obtained.
(2) The system model (7) is used to predict the average
voltages, V
b (k) and V
a (k), for the next sample time.
Fig. 2 Block diagram of the proposed strategies
a Block diagram of proposed SVM-based PCC
b Required inverter output voltage vectors for the proposed SVM-based PCC
c Block diagram of proposed error minimisation

842 IET Power Electron., 2014, Vol. 7, Iss. 4, pp. 840–849

& The Institution of Engineering and Technology 2014 doi: 10.1049/iet-pel.2013.0182
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is minimised. This strategy is based on the fact that in an and Sc. Each of these switching variables can be defined as
inverter, the number of possible switching states is finite. + 1 (or − 1) when the upper (or lower) switch of the leg is
As discussed earlier, in order to mitigate CMV in switched on. Note that the two switches of a leg are
three-phase inverters, only switching states with desired switched complementarily, that is, if the upper switch of a
levels of CMV are included in the applied modulation leg is ON the lower one is OFF and vice versa. The
scheme. Comparing the predicted output currents with two-level three-phase inverter has eight switching states
reference currents for those switching states, achieves some which are presented in Table 1 with their corresponding leg
error vectors and the switching state which has the lowest
error is selected for the next sample. In this strategy, a
selection criteria is defined to choose the appropriate
switching state for a PWM cycle. This selection criteria is
an error function which is employed to determine the
behavior of variables. Using the discrete–time model of (6)
⎧
⎪ T  
⎨ ib (k + 1) = s . Vb (k) − R.ib (k) − eb (k) + ib (k)
L (8)
⎪ T 
⎩ i (k + 1) = s . V (k) − R.i (k) − e (k) + i (k)
a a a a a
L

where iβ(k + 1) and iα(k + 1) are the predicted load currents at

the end of next sample time. The error function is defined as
[23]
   
 
g = i∗b (k + 1) − ib (k + 1) + i∗a (k + 1) − ia (k + 1) (9)

where i∗b (k + 1) and i∗a (k + 1) are reference currents at the end

of next sample time. This strategy can be summarised in
following steps:

(1) The values of output currents at the end of present sample

time, iβ(k) and iα(k), are measuredand current references at the
end of the next sample time, i∗b (k + 1) and i∗a (k + 1), are
obtained.
(2) The system model (8) is used to predict the output currents
at the end of next sample time, iβ(k + 1) and iα(k + 1), for
switching states with desirable CMV levels.
(3) The error function (9) calculates the error between
reference currents and predicted load currents at the end of
next sample time for the all acceptable switching states, and
the switching state which minimises the error function is
selected for the sample time.

In fact, the selected switching state is the one whose

predicted load currents are closest to the reference currents,
and therefore, CMV is mitigated by applying only
switching states with expected CMV and also load currents
are made to track the reference currents with high accuracy
which considerably decreases the harmonic contents of
output currents. Block diagram of the proposed error
minimisation strategy is illustrated in Fig. 2c.
In drive systems, PWM inverters are widely used as an
interface between input and motor. Two-level inverters are
more effective for low power applications. In high voltage
and high power drive applications the two-level inverter,
however, has some limitations because of constraints of
device rating and switching losses. Multilevel inverters are
more advantageous in such applications [28].

4 Two-level three-phase inverter

4.1 Topology, Switching States, and CMV
The topology of a two-level inverter connected to an
induction motor is shown in Fig. 3a. The switching states
of inverter are determined by switching variables Sa, Sb,
Fig. 3 Two-level inverter connected to an induction motor
a Topology of two-level inverter
b Leg voltages and CMV in a typical switching pattern
c Space vector diagram for different switching states of the two-level inverter

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Table 1 Switching states, leg voltages, and CMV for two-level
three-phase inverter

Vectors Switching Vao Vbo Vco CMV

states
(Sa Sb Sc)

V1 (1 − 1 − 1) + Vdc/2 − Vdc/2 − Vdc/2 − Vdc/6

V2 (1 1 − 1) + Vdc/2 + Vdc/2 − Vdc/2 + Vdc/6
V3 ( − 1 1 − 1) − Vdc/2 + Vdc/2 − Vdc/2 − Vdc/6
V4 ( − 1 1 1) − Vdc/2 + Vdc/2 + Vdc/2 + Vdc/6
V5 ( − 1 − 1 1) − Vdc/2 − Vdc/2 + Vdc/2 − Vdc/6
V6 (1 − 1 1) + Vdc/2 − Vdc/2 + Vdc/2 + Vdc/6
V7 (1 1 1) + Vdc/2 + Vdc/2 + Vdc/2 + Vdc/2
V0 ( − 1 − 1 − 1) − Vdc/2 − Vdc/2 − Vdc/2 − Vdc/2

voltages and CMV. Fig. 3b shows the leg voltages and CMV
of the two-level inverter for a given switching pattern. Fig. 3c
illustrates the space vector diagram obtained from all
switching states.
As can be seen from Table 1, the zero vectors (V0, V7)
produce the highest CMV in magnitude ( − Vdc/2, + Vdc/2)
and active vectors (V1-V6) generate the two others ( − Vdc/
6, + Vdc/6). CMV is accompanied by numerous problems in
AC drive systems, Thus, in two-level three-phase inverter, it
is reasonable to eliminate the highest CMV (−Vdc/2, +Vdc/2)
in the applied modulation method in order to reduce the
adverse effects of them, that is, the zero vectors would not
be used.
The basic idea for CMV reduction in two-level inverter is
to cancel the use of zero vectors in switching patterns.
However, doing so, the remained vectors in a switching
pattern may not meet the volt-second balancing principle
and consequently, this leads to variant switching frequency.
For example in conventional SVM, when Vref is in sector 1
as shown in Fig. 3c, it can be synthesised by V1, V2, and
V0. The volt-second balancing principle can be written as
follows
 = 5 kHz, Vdc = 220 V, modulation index = 0.85, and an
Vref .Ts = V1 .T1 + V2 .T2 + V0 .T0
(10)
Ts = T1 + T2 + T0
where Ts is the sampling period and T1, T2, and T0 are dwell
times for the vectors V1, V2, and V,0 respectively [29]. Now, if
T0 be omitted, since T1 and T2 are not the same in different
sampling periods, it causes variant switching frequency. In
order to solve the problem, active vectors must be used to
replace the zero vectors. Previously, two SVM-based
modulation methods, symmetrical SVM [14] and near state
PWM [15], have been proposed to reduce CMV in
two-level inverter. However, these methods lead to extra
harmonic distortion of output currents. To get rid of the
problem, hence, this work proposes PCC-based modulation
strategies to reduce the CMV which have been investigated
in Section 3. The desired switching states for two-level
inverter in the proposed strategies are non-zero vectors to
remove the highest levels of CMV.
Assuming that the reference voltage falls in sector 1, as
shown in Fig. 3c, voltage vector sequence for conventional
SVM and proposed SVM-based PCC for CMV reduction
are (V0, V1, V2, V7, V2, V1, V0) and (V3, V2, V1, V6, V1, V2,
V3), respectively. The proposed PCC strategy using error
minimisation for CMV reduction, in each sample time,
calculates the error function for those non-zero vectors and
the switching state whose vector has the lowest error is
selected for the sample time.
Fig. 4 CMV of two-level inverter for
a Conventional SVM
b Proposed PCC strategy based on SVM for CMV reduction
c Proposed PCC strategy using error minimiation for CMV reduction
4.2 Simulation results
Simulation parameters for a two-level three-phase inverter are
as follows: reference frequency = 50 Hz, switching frequency
0.18 kW induction motor is considered as the load.
Simulation results of CMV for conventional SVM and
proposed strategies are presented in Fig. 4. THD of output
current in conventional SVM (Fig. 5a) is 1.78% and in
traditional CMV reduction techniques, symmetrical SVM
and near state PWMon the same parameters are 3.29% and
3.26%, respectively. Therefore in these methods, CMV
reduction leads to an increase in THD of output current. As
can be seen from Fig. 4b, the proposed PCC based on
SVM for CMV reduction reduces CMV by one third such
as previous methods. Furthermore, in this method, THD of
output current is 2.69% (Fig. 5b) which shows a better
performance than previous methods for CMV reduction.
However, this percentage is more than the one for
conventional SVM. Fig. 4c shows that the proposed PCC
using error minimisation for CMV reduction eliminates the
highest levels of CMV such as previous techniques for
CMV reduction. In this method, THD of output current is
1.01% (Fig. 5c) which demonstrates a significant reduction
than previous techniques for CMV reduction, and even this
percentage is considerably lower than conventional SVM.
4.3 Experimental results
To verify the effectiveness of the proposed strategies in
reducing CMV, an experimental setup has been developed
for obtaining experimental results. The main circuit of

844 IET Power Electron., 2014, Vol. 7, Iss. 4, pp. 840–849

& The Institution of Engineering and Technology 2014 doi: 10.1049/iet-pel.2013.0182

Fig. 5 Waveform and harmonic spectrum of phase a current for
a Conventional SVM
b Proposed PCC strategy based on SVM for CMV reduction
c Proposed PCC strategy using error minimiation for CMV reduction
two-level inverter is constituted by 8 IGBTsand tested with a
0.18 KW induction motor. The central controller is a Texas
Instrument DSP model TMS320F28335. Sampling of output
currents for the proposed current controlled-based strategies
are carried out using HV7800 high side current monitor ICs
and transferred to the DSP through analog-to-digital
converter. The DC-link voltage is set to 220 Volt. The
control code for the traditional and proposed techniques has
been written in C, applying the output frequency of 50 Hz
and sampling frequency of 5 KHz. A series of tests have
been performed in order to compare the properties of
traditional and proposed approaches for CMV reduction.
Figs. 6 and 7 depict the experimental results of CMV and
current waveform of phase a, respectively, for conventional
SVM and proposed strategies. As can be observed, the
CMV is reduced by one third by applying proposed
IET Power Electron., 2014, Vol. 7, Iss. 4, pp. 840–849
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Fig. 6 CMV; 35 V/div, 2.5 ms/div, for
a Conventional SVM
b Proposed PCC strategy based on SVM for CMV reduction
c Proposed PCC strategy using error minimiation for CMV reduction
strategies for CMV reduction (Figs. 6b and c) as well as
traditional ones rather than conventional SVM (Fig. 6a).
Moreover, as observed in the laboratory tests, THD of
output current in conventional SVM (Fig 7a) is 4.4% and
in the two previous methods for CMV reduction,
symmetrical SVM and near state PWM on the same
parameters are 7.9% and 7.7%, respectively, which shows
an undesirable increase in harmonic contents of output
currents. THD of output current in the proposed predictive
strategies for CMV reduction, PCC based on SVM and PCC
using error minimisation are 5.8% and 3.2%, respectively.
Therefore harmonic contents of output currents of
proposed strategies for CMV reduction are noteably lower
than traditional ones and more qualified output current is
achieved using the proposed strategies.
5 Three-level NPC inverter
In comparison with two level inverters, for high power
applications, multilevel inverters have some advantages
such as lower voltage stress on the switching devices,
reduced harmonic distortions, and lower dv/dt [30]. Among
multilevel inverters topologies, the three-level NPC inverter
has found broad application in high power drives.
5.1 Topology, Switching States, and CMV
Fig. 8a shows the power circuit diagram of the three-level
NPC inverter, which is applied in medium-voltage AC
845
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Fig. 7 Waveform of phase a current; 1 A/div, 10 ms/div

a Conventional SVM
b Proposed PCC strategy based on SVM for CMV reduction
c Proposed PCC strategy using error minimisation for CMV reduction

drives. The operating condition for each leg of the inverter can
be defined by switching states P, O, and N. For example for leg
a, switching state P indicates that the upper two switches in the
leg are ON and the voltage between terminal a and neutral
point o, that is, the inverter terminal voltage Vao, is + Vdc/2,
while N denotes that the lower two switches are ON,
leading to Vao = − Vdc/2 [29]. Switching state O indicates
that the inner two switches conduct and Vao is clamped to
zero. Switches S1 and S3 are switched complementarily as
well as S2 and S4, that is, if one is ON, the other must be
OFF. As mentioned, there are three possible switching states
(P, O, N) for the operation of each NPC inverter phase leg.
Therefore taking into account all three phases, there are a
total of 27 combinations of switching states for the NPC
inverter which are listed in Table 2 with their related voltage
vectors and CMV. Fig. 8b shows the leg voltages and CMV
of the three-level NPC inverter for a typical switching
pattern. As shown in Fig. 8c, the switching states produce
19 voltage vectors, that is, some voltage vectors represent Fig. 8 Three-level NPC inverter applied in medium-voltage AC
more than one switching state and have different CMV drives
magnitude. As can be seen from Table 2, Out of 27 a Power circuit of the three-level NPC inverter
switching states, 7 switching states have zero CMV, 12 b Leg voltages and CMV in a typical switching pattern
switching states have the CMV with magnitude of Vdc/6, 6 c Space vector diagram and division of sectors and regions for the NPC
switching states have the CMV with magnitude of Vdc/3, inverter
and 2 switching states have the magnitude of Vdc/2.
The multilevel inverter has the ability of suppressing CMV presented to suppress the CMV in three–level NPC
as well as reducing it. In [17], two modulation schemes are inverters. The basic idea for CMV suppression is to limit

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Table 2 Switching states of the NPC inverter with their related switching states with desirable CMV and selects the
CMV and voltage vectors switching state with minimum error.
Switching state Space vector Vector magnitude CMV

[OOO] V0 0 0 5.2 Simulation results

[NNN] V0 0 − Vdc/2
[PPP] V0 0 + Vdc/2 Relevant parameters of the simulated topology are as the same
[POO] V1 Vdc/3 + Vdc/6 as the two-level inverter. Simulation results of proposed
[ONN] V1 Vdc/3 − Vdc/3 strategies for the NPC inverter are shown in Figs. 9 and 10.
[PPO] V2 Vdc/3 + Vdc/3
[OON] V2 Vdc/3 − Vdc/6 It can be observed from Figs. 9a and b that the proposed
[OPO] V3 Vdc/3 + Vdc/6 strategies for CMV suppression, cancel CMV such as
[NON] V3 Vdc/3 − Vdc/3 traditional techniques for CMV elimination, furthermore,
[OPP] V4 Vdc/3 + Vdc/3 the THD of output current for proposed PCC strategy based
[NOO] V4 Vdc/3 − Vdc/6
[OOP] V5 Vdc/3 + Vdc/6
on SVM (Fig. 10a) and PCC strategy using error
[NNO] V5 Vdc/3 − Vdc/3 minimisation (Fig. 10b) for CMV suppression are 1.56%
[POP] V6 Vdc/3 + Vdc/3 and 1.30%, respectively. Whereas, the output current THD
[ONO] V6 √V

dc/3 − Vdc/6 for the traditional methods for CMV suppression [17] on
[PON] V7 3.Vdc/3
√

0 the same parameters is 1.91%. Also, proposed strategies

[OPN] V8 3.Vdc/3
√

0
[NPO] V9 have been employed to reduce CMV in the NPC inverter.
√3

.Vdc/3 0
[NOP] V10 √3

.Vdc/3 0 Figs. 9c and d show that the proposed strategy can

[ONP] V11 3.Vdc/3
√

0 successfully reduce CMV, moreover, as seen from Figs. 10c

[PNO] V12 3.Vdc/3 0 and 10d, THD of output current for the proposed PCC
[PNN] V13 2.Vdc/3 − Vdc/6
[PPN] V14 2.Vdc/3 + Vdc/6
strategy based on SVM and PCC strategy using error
[NPN] V15 2.Vdc/3 − Vdc/6
[NPP] V16 2.Vdc/3 + Vdc/6
[NNP] V17 2.Vdc/3 − Vdc/6
[PNP] V18 2.Vdc/3 + Vdc/6

the switching states only to those which generate zero CMV,

that is, (OOO), (PON), (OPN), (NPO), (NOP), (ONP), and
(PNO). Using only 7 switching states to delete CMV
reduces maximum level of output voltages as well as
increases harmonic distortions of output currents. Therefore
some researches have dealt with CMV reduction for the
NPC inverter. These methods restrict the CMV within the
range of ± Vdc/6. To do this, the operation of the NPC
inverter should be limited to the 19 switching states with
the magnitude of zero and Vdc/6. Other eight switching
states are excluded in modulation schemes for CMV
reduction in the NPC inverter. Therefore the employed
switching states decrease the redundancy and every voltage
vector has only one switching state and CMV. [18]
proposes a PWM strategy to reduce the CMV in the
three-level NPC inverter. However, the modulation schemes
for CMV suppression/reduction noteably increase harmonic
contents of output currents. Therefore this paper proposes
PCC-based modulation strategies for both CMV
suppression and reduction in the NPC inverter which have
been discussed earlier in Section 3.
The voltage vectors with zero CMV can divide the voltage
vector space into six sectors as shown in Fig. 8c in green
lines. To synthesise the reference voltage in the proposed
SVM-based PCC for CMV suppression three nearest
vectors with zero CMV are employed. For example when
reference voltage locates between − 30^° and 30^°, as
shown with vector Q in Fig. 8c, the voltage vector
sequences can be as (V0, V7, V8, V7, V0). In each sample
time, To reduce the CMV within the magnitude of Vdc/6,
the proposed SVM-based PCC for CMV reduction uses
only 19 switching states. (V2, V7, V14, V2, V14, V7, V2) and
(V0, V1, V2, V0, V2, V1, V0) are the voltage vector sequences Fig. 9 CMV of NPC inverter for
for a low (vector Q in Fig. 8c) and high (vector P in
a Proposed PCC strategy based on SVM for CMV suppression
Fig. 8c) magnitude reference voltage, respectively. The b Proposed PCC strategy using error minimisation for CMV suppression
proposed PCC strategy using error minimisation for CMV c Proposed PCC strategy based on SVM for CMV reduction
suppression/reduction calculates the error for those d Proposed PCC strategy using error minimisation for CMV reduction.

IET Power Electron., 2014, Vol. 7, Iss. 4, pp. 840–849 847

doi: 10.1049/iet-pel.2013.0182 & The Institution of Engineering and Technology 2014
www.ietdl.org
Fig. 10 Waveform and harmonic spectrum of phase a current for
a Proposed PCC strategy based on SVM for CMV suppression
b Proposed PCC strategy using error minimisation for CMV suppression
c Proposed PCC strategy based on SVM for CMV reduction
d Proposed PCC strategy using error minimisation for CMV reduction
848
& The Institution of Engineering and Technology 2014
minimisation for CMV reduction are 1.09% and 0.47%,
respectively. While the THD for the traditional method for
CMV reduction [18] on the same parameters is 1.46%.
Thus, proposed strategies for CMV suppression/reduction in
the NPC inverter considerably decrease the harmonic
contents of output current rather than previous methods.
6 Conclusion
To avoid premature bearing damage, EMI, and insulation
breakdown of motor windings because of motor shaft
voltages and circulating leakage currents through parasitic
capacitors inside motor, it is crucial to reduce the CMV and
to limit this voltage within a certain range in AC drive
systems. New modulation strategies based on SVM and
PCC for three-phase inverter-fed induction motor has been
proposed to mitigate CMV. To verify the accuracy of the
proposed predictive strategies, they have been implemented
on two-level and three-level NPC inverter. The results of
two-level inverter conclude that the proposed strategies are
able to keep the CMV within ± Vdc/6. Since the NPC
inverter has the ability of suppressing CMV as well as
reducing it, the proposed strategies heve been successfully
used to suppress/reduce this voltage.Also, performance of
new strategies has been compared with previous methods
for CMV mitigation by calculating the THD of output
current. The results show that harmonic contents of output
currents of proposed strategies are significantly less than
previous ones for CMV mitigation in two-level and
three-level NPC inverter, that is, the quality of output
current waveforms of proposed methods are much more
better. Therefore proposed strategies are more effective and
have a better performance than previous techniques.
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