Sei sulla pagina 1di 4

VHDL IMPLEMENTATION OF A DMX512 DECODER ON AN FPGA

Nicholas Attard, Steve Camilleri, Roberto Drago, Maverick Hili, Owen Casha, Edward Gatt and Ivan Grech

Faculty oflnformation and Communication Technology


Department of Microelectronics and Nanoelectronics
University of Malta, Msida, Malta.
E-mail: oecash @eng.um.edu.mt

ABSTRACT constant stream of DMX512 data packets at the transmitter


side or to decode them at the receiver side. Other
This paper presents the hardware implementation and implementations make use of the readily available
verification of an FPGA-based DMX512 decoder using XILKemel® embedded processor to obtain DMX packet
VHDL as a Hardware Description Language. The generation and control through TCP/IP network using a
stack [6]. Such a system may be used where various devices
implementation is proposed to provide a single chip
need to be controlled simultaneously using a Real-Time
solution to decode the DMX512 serial data generated
Operating System (RTOS) with few or no delays. The
from a control desk, whilst providing control data and
XIPKemel® can also be used to implement other services
processing mechanisms on the same chip. In particular, such as networking, video and audio [7]. Conversely, in this
such an FPGA solution would be superior to a implementation, the DMX decoder is independent of any
microcontroller counterpart in a scenario where a large embedded processor/so Such an implementation also allows
number of integrated chips need to communicate together for more than one DMX decoder on the same chip if control
to perform their respective tasks. Moreover, more than of more than one device is needed. Although the generation of
one system can be implemented on the same FPGA chip DMX packets is not complicated, it is wasteful of the
processor's resources due to the precise timing and quantity of
thus reducing costs and physical size. As a proof of
delays that have to be generated. If the controller is expected
concept, the developed architecture is applied to a
to generate packets for more than one DMX system, the
laser-based light pattern projection system.
situation is further complicated. Repetitive tasks such as
packet generation and decoding are better implemented in
Index Terms Automation, DMX512, Field custom hardware removing the need for the processor to do
Programmable gate arrays, Hardware Description Languages, the task [4]. Any hardware description language such as
Lighting, RS-485. VHDL or Verilog can be used to implement a finite state
machine to generate the DMX512 data packets, freeing up the
1. INTRODUCTION processor's time for the user interface and the processing of
lighting patterns or sequences. The use of hardware-based
DMX512 is a standard for digital communication networks DMX512 packet generation or decoding is also scalable,
that are commonly used to control stage lighting and effects. It enabling designers to control as many DMX systems from the
was developed by the Engineering Commission of the United same FPGA as required, without any risk of incurring
States Institute for Theatre Technology (US ITT), and was performance limitations as the capabilities of the design
originally intended as a standardised method for controlling increase. FPGAs can also be used to generate pulse width
modulation signals (PWM) for dimming lights, along with
light dimmers, which prior to DMX512, had employed
servo motor controllers for the pan and tilt functionality. This
various incompatible proprietary protocols. However, it soon
enables designers to deliver a single chip solution for
became the primary solution for linking not only controllers
DMX512 enabled lighting fixtures.
and dimmers, but also more advanced fixtures and special
effects devices such as moving lights and fog machines. The
This work presents the implementation of an FPGA-based
standard allows controlling a large number of lighting
DMX512 decoder with an 8-bit output per channel. The
channels on the stage using a remote control desk without the
hardware description of the decoder was made using VHDL.
need to run large lengths of mains electrical cable for each
In particular, as a test bed, the decoder was used to control the
lighting channel. The DMX512 standard uses a low voltage
galvanometers in a laser pattern projection system.
control cable, linking the control desk and the dimmer packs,
Nonetheless, the modularity of the design makes it feasible to
and is based on the RS-485 serial standard of signalling. Each
be used in any light control application.
DMX512 link can control up to 512 different lighting
channels over a single pair of wires [1].
2. DMX512 COMMUNICATION PROTOCOL
Many solutions implement the DMX512 protocol using a
The DMX512 protocol is an asynchronous 8-bit serial
microcontroller architecture [2, 3] in addition to different chip
sets to provide the various required functions. Field protocol and works in a unidirectional line generated by a
programmable gate arrays (FPGA) are an excellent candidate master device. The protocol can handle up to 512 devices in
to provide a single chip embedded implementation. A large the network and communicates with a frequency of 250 kHz.
percentage of the processing power of traditional Each bit in the frame is generated every 4 Ils. Every slave in
microcontrollers would be typically required to generate the the network is addressed using one specific start byte in the

978-1-4244-8157-6/10/$26.00 ©2010 IEEE 710 ICECS 2010


frame, followed by a number of other bytes depending on the 3. DMX DECODING STAGES
device. For example, a moving light would typically require
The designed DMX512 decoding module is divided into three
various channels for movement, speed, colour and shape.
main levels, which have the overall function of filtering out
Moreover, since a one byte data word is used, each byte in the
the required data for each channel, selecting the needed
frame describes 256 possible control levels [2].
channels and ignoring the others. A description of each
MAB
2HI
�IMTBF 2HI 2HI decoding level is given in the following sub-sections. The
bits bits MTBF bits MTBF
· DMX decoder was implemented and tested on a Digilent
- . BASYS2 FPGA development board [5].
.
· .
DATA DATA DATA
8 bits 8 bits 8 bits 3.1. Stage 1 - Data Sampler
512 Dala
· . Packets
""-- , ""-- , -'
Break
·
Break
The data sampler is the first level in the decoder module.
1LO • 1LO 1LO
22LObits bi1 bit bit 22 LObits It is responsible for sampling the DMX512 data received from
the lighting control desk at the clock rate of 50 MHz. Since
Figure 1. DMX512 Data Protocol DMX512 operates at an approximate frequency of 250 kHz,
the data arriving from the control desk is sampled 200 times
DMX512 data is transmitted sequentially in asynchronous every cycle. An in-built counter keeps track of the number of
serial format, starting with channel 0 and ending with channel th
samples taken per DMX512 bit, and selects the 100 sample
511. Prior to the first data channel being transmitted, there is a and passes it to stage 2. To provide synchronisation amongst
reset sequence consisting of a BREAK followed by a MARK all stages, a readPulse signal is momentarily set high, to
AFTER BREAK (MAB) signal. Valid data values under a indicate to the second stage that a new DMX512 bit has been
START code are between 0 and 255. Fig. 1, Fig. 2 and Fig. 3 sampled and is ready for further processing (refer to Fig. 4).
show detailed information on the different elements in the This provides a clean signal for the next stages whilst
DMX512 data frame protocol. These images, showing the allowing re-synchronisation of the internal counters with each
constituents of the DMX512 data packet, were captured using rising- and falling-edges on the received serial data. This
the HAMEG HM03522 oscilloscope. ensures a high fidelity system.

J I ....

DMX512 data
... r "" lJlM
Read Pulses

Figure 2. DMX512 data packet (Time-base: 10ms/div)

The BREAK indicates the start of a new packet, whilst


the MAB separates the break and start code time slots. The
Resynchronization
START CODE of the channel zero follows the MAB and
contains a typical data value of zero. The other data channels Figure 4. readPulses with re-synchronisation from the data
follow subsequently. The data on each channel determines sampler stage to stage 2 (Time-base: 20 Ils/div)
the control levels for the receiving device. The time between
any two data channels is known as MARK TIME BETWEEN 3.2. Stage 2 - Data Analyser
FRAMES (MTBF). This can last from a little more than 0
seconds up to a maximum of 1 second, during which time the The function of the second stage within the decoder is to
signal is high. On the other hand, the MARK TIME analyse the bits being received from the data sampler. With
BETWEEN PACKETS (MTBP) is the time between the last each falling-edge on the readPulse signal received from stage
channel of a packet and the BREAK signal of a new packet. 1, a new bit is inputted and serially shifted in a 24-bit buffer
Note that the MTBP is a console-dependent time period, whilst being constantly compared to the pre-defined pattern
during which the signal is also high [2]. "110000000000000000000000". This particular pattern
signifies a BREAK signal of at least 22 low-bits and 2 high­
bits from the MAB. Once this pattern is received, a flag
signifying that the BREAK was detected is set. As soon as a
Idle High
falling-edge follows, the system goes into the RECEIVING
Channel
DATA state. In this state, the system receives a total of eleven
bits, consisting of one low start bit (which is actually the first
Signal sampled
falling-edge before entering into this state), eight data bits and
and rebuilt in Break
two high stop bits. The start and stop bits ensure error
FPGA detection. As soon as the data is verified, the data byte is sent
to stage 3 together with a positive pulse to signal to stage 3
Figure 3. Idle, Break, MAB, Channel and MTBF that a new channel data byte is available for further
(Time-base: 100IlS/div)

711
processing. FoIlowing this, the system then returns to the
WAITING FOR FALLING EDGE state.
Once that one whole DMX512 packet has been received,
the system wiIl reset the breakDetected bit during the first few
no
bits of the BREAK foIlowing the IDLE state on the line. This
Falling Edge on
is necessary because the system assumes that data is present
readPulse?
immediately after the first faIling-edge foIlowing the IDLE
stage, given that breakDetected is still set to binary '1' from
the previous DMX512 packet. The system will thus start yes
receiving bits as though it expects to receive a channel. On the ,-__________ t1�_________,

contrary to normal operation, since the stop bits in this case Shift DMX512 data from stage 1 into buffer from right
would be low, the system senses that there must be something
wrong, and returns breakDetected to binary '0'. This is one of
the situations in which the error detection mechanism plays an
important role. Further to this, due to the fact that the BREAK ,---<. State = WFFE?
signal is much longer than the typical channel data, the system
resumes normal operation, with normal BREAK detection and
successive channel data readings. y�s

no
Buffer = Set breakDetected Flag
yes
Pattern? Send positive resetPulse to stage 3

no
no

DMX512 data Read Pulses


reakDetected set
AND
Start Bit detected?

Figure 5. readPulse from the second stage to the third stage


(Time-base: 50 Ils/div)

Once the bits carrying the channel data are detected, the
� "0-----1

whole byte is passed on to the third stage. A similar


yes
signalling system to that between stage 1 and stage 2 is
implemented. A readPulse is thus sent to stage 3 when
every new channel data is available. This is clearly shown
in Fig. 5. Further to this, a resetPulse is sent from stage 2 to
stage 3 with every BREAK detection as indicated in Fig. 6.
This ensures that only the required channels are captured Start Bit is reset
� Error has occured
by stage 3, whilst ignoring the others. AND no --,.,
Reset breakDetected flag
Stop Bits are set?

3.3. Stage 3 - Channel Data Selection


yes
The final stage is a made up of a counter which records the
number of readPulses received from stage 2. As soon as Send data byte to stage 3
the counter value is within the range specified by the user, Send positive read Pulse to stage 3
the system outputs the received channel data byte to one of
its outputs for further processing. In the specific lighting
WFFE means WAITINGJORJALLlNG_EGDE
control application described in Section 4, eight separate RD means RECEIVING_DATA
channels were needed for the LASER projection system. Pattem means" 11 0000000000000000000000"

Figure 7. Flowchart describing the processes taking place in the


second stage of the DMX512 decoder.

Break The eight channels are identified by an offset marker inputted


through the selection switches on the FPGA development
board itself. Thus, for example, if one sets the switches to a
DMX512 data decimal value of 20, the channel numbers 20, 21, 22, 23, 24,
ResetPulse
Set when break 25, 26 and 27 would be read from the DMX512 line. Further
detected to this, for synchronisation issues, a resetPulse from stage 2 is
sent at this stage to reset the channel number counter. This

Figure 6. resetPulse from the second stage to the third stage


caters for sudden connections of the DMX512 cable, or for
(Time-base: 200IlS/div) intermittent or loose connections.

712
4. LASER PATTERN PROJECTION SYSTEM Following these components, the following table
summarises the FPGA utilisation in terms of its available
This DMX512 decoder module was implemented together resources:
with a LASER pattern projection system. Fig. 8 shows the
schematic for this system. Given that the LASER system Number of Slices 100
requires control through various parameters, the DMX512 Number of Slice Flip Flops 129
protocol proved to be adequate for serialising the multiple Number of 4 input Look Up Tables 100
channel data and facilitate use via a control desk. This decoder Number of bonded 110 blocks 76
was therefore used to generate the required control words for Number of GCLKs 3
the deflection galvanometers used as mirrors for the X- and
Y - planes as shown in Fig. 9a. These control words are then Given that the DMX512 decoder uses few resources, it
processed by the processing unit. The galvanometers are can be easily implemented in applications with more than one
driven via pulse width modulated (PWM) signals generated processing block resident on the same FPGA chip since
by the processing unit. The mirrors attached to their shafts are blocks can be made to run in parallel on the same FPGA. This
made to oscillate in a particular fashion by specifYing a further reduces costs and size limitations, and improves
starting position, amplitude of oscillation and speed, in order efficiency. Moreover, it allows the control of more than one
to generate the required light pattern. The single chip system device from the same FPGA chip.
proved to be very reliable due to fewer interconnections
amongst components when compared to one based on a
microcontroller architecture.

c.
� Processing unit

LCil
DMX co ' -' �
tEO 'daia5ided" � " .. .""owI �
ChannelO(10) ,,,,,OJ p'MflHigllO _.0
Channell(10) ,,,,OJ ."" ... �
� ,,,.
Chamel2(10) ,,,OJ
Figure 9. (a) Laser light reflecting on the X-Y galvanometer
ChJmel3(10) lifne(70)
mirrors (b) A particular light effect that can be generated
�� Chami!IJ(10) �10J
using the developed system.
Chamel5(10) :,tl(10)

Chamel6(10) ){70j
()mI( AddreS5 7 0\ 0I.«Addftst(70)
)frle{70)
Chantlel1j10)
REFERENCES

Figure 8. Schematic of the DMX512 decoder with LASER


processing unit. [I] "Entertainment Technology USITT DMX512-A
Asynchronous Serial Digital Data Transmission
The dataOkLed is programmed to pulse with Standard for Controlling Lighting Equipment and
every BREAK detection, to indicate correct operation of the Accessories", ANSI El.ll-2004J, November 8, 2004.
decoder. The decoder module was tested with various control
desks to ensure compatibility. Mainly, these were the Showtec [2] O. Luna and D. Torres, "DMX512 Protocol
© ©
Showmaster 24 and the Zero88 FatFrog . Implementation Using MC9S08GT60 8-Bit MCU",
Freescale Semiconductor, Application Note
5. CONCLUSION (AN3315), September 2006.

Due to the common use of the DMX512 protocol in almost all


[3] P. Pandya, "Using a PIC® Microcontroller for
lighting designs, the decoder described in this paper achieves
DMX512 Communication", Microchip, Application
the targets of being reliable and cost-effective when
Note (AN1076), February 2007.
implemented with one or many lighting devices. In such
lighting setups, it is important that the data on the serial
[4] R. Griffin, "DMX512 Stage Lighting for
protocol is carefully extracted not to have sudden flickering of
Begineers", Avnet Silica.
the lights and irregular behaviour of the devices. With respect
to the developed DMX512 decoder, when the VHDL code
was translated to hardware through a Hardware Design [5] Digilent Inc., "Digilent BASYS2 Board Reference
Language synthesiser, the following components were Manual", May 25, 2009.
utilised:
[6] S. Yoowattana, C. Nantajiwakornchai, M.
• Ix 8-bit adder, Sangworasil, "A design of embedded DMX512
• Ix 9-bit adder, controller using FPGA and XILKemel", IEEE
• Ix 9-bit subtractor, Symposium on Industrial Electronics & Applications
• 2x 4-bit up-counters, (ISIEA 2009), pp. 73-77, December 2009.
• 121x Flip-flops, and
• 2x 9-bit comparators. [7] Xilinx, "Xilkernel", December 12, 2006

713

Potrebbero piacerti anche