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Nicholas Attard, Steve Camilleri, Roberto Drago, Maverick Hili, Owen Casha, Edward Gatt and Ivan Grech
J I ....
DMX512 data
... r "" lJlM
Read Pulses
711
processing. FoIlowing this, the system then returns to the
WAITING FOR FALLING EDGE state.
Once that one whole DMX512 packet has been received,
the system wiIl reset the breakDetected bit during the first few
no
bits of the BREAK foIlowing the IDLE state on the line. This
Falling Edge on
is necessary because the system assumes that data is present
readPulse?
immediately after the first faIling-edge foIlowing the IDLE
stage, given that breakDetected is still set to binary '1' from
the previous DMX512 packet. The system will thus start yes
receiving bits as though it expects to receive a channel. On the ,-__________ t1�_________,
contrary to normal operation, since the stop bits in this case Shift DMX512 data from stage 1 into buffer from right
would be low, the system senses that there must be something
wrong, and returns breakDetected to binary '0'. This is one of
the situations in which the error detection mechanism plays an
important role. Further to this, due to the fact that the BREAK ,---<. State = WFFE?
signal is much longer than the typical channel data, the system
resumes normal operation, with normal BREAK detection and
successive channel data readings. y�s
no
Buffer = Set breakDetected Flag
yes
Pattern? Send positive resetPulse to stage 3
no
no
Once the bits carrying the channel data are detected, the
� "0-----1
712
4. LASER PATTERN PROJECTION SYSTEM Following these components, the following table
summarises the FPGA utilisation in terms of its available
This DMX512 decoder module was implemented together resources:
with a LASER pattern projection system. Fig. 8 shows the
schematic for this system. Given that the LASER system Number of Slices 100
requires control through various parameters, the DMX512 Number of Slice Flip Flops 129
protocol proved to be adequate for serialising the multiple Number of 4 input Look Up Tables 100
channel data and facilitate use via a control desk. This decoder Number of bonded 110 blocks 76
was therefore used to generate the required control words for Number of GCLKs 3
the deflection galvanometers used as mirrors for the X- and
Y - planes as shown in Fig. 9a. These control words are then Given that the DMX512 decoder uses few resources, it
processed by the processing unit. The galvanometers are can be easily implemented in applications with more than one
driven via pulse width modulated (PWM) signals generated processing block resident on the same FPGA chip since
by the processing unit. The mirrors attached to their shafts are blocks can be made to run in parallel on the same FPGA. This
made to oscillate in a particular fashion by specifYing a further reduces costs and size limitations, and improves
starting position, amplitude of oscillation and speed, in order efficiency. Moreover, it allows the control of more than one
to generate the required light pattern. The single chip system device from the same FPGA chip.
proved to be very reliable due to fewer interconnections
amongst components when compared to one based on a
microcontroller architecture.
c.
� Processing unit
LCil
DMX co ' -' �
tEO 'daia5ided" � " .. .""owI �
ChannelO(10) ,,,,,OJ p'MflHigllO _.0
Channell(10) ,,,,OJ ."" ... �
� ,,,.
Chamel2(10) ,,,OJ
Figure 9. (a) Laser light reflecting on the X-Y galvanometer
ChJmel3(10) lifne(70)
mirrors (b) A particular light effect that can be generated
�� Chami!IJ(10) �10J
using the developed system.
Chamel5(10) :,tl(10)
Chamel6(10) ){70j
()mI( AddreS5 7 0\ 0I.«Addftst(70)
)frle{70)
Chantlel1j10)
REFERENCES
713