JK FLIP FLOP

The basic S-R NAND flip-flop circuit has many advantages and uses in sequential logic
circuits but it suffers from two basic switching problems.
 1. the Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided
 2. if Set or Reset change state while the enable (EN) input is high the correct
latching action may not occur
Then to overcome these two fundamental design problems with the SR flip-flop design,
the JK flip Flop was developed.
This simple JK flip Flop is the most widely used of all the flip-flop designs and is
considered to be a universal flip-flop circuit. The two inputs labelled “J” and “K” are not
shortened abbreviated letters of other words, such as “S” for Set and “R” for Reset, but
are themselves autonomous letters chosen by its inventor Jack Kirby to distinguish the
flip-flop design from other types.
The sequential operation of the JK flip flop is exactly the same as for the previous SR
flip-flop with the same “Set” and “Reset” inputs. The difference this time is that the “JK
flip flop” has no invalid or forbidden input states of the SR Latch even when S and R are
both at logic “1”.
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input
circuitry that prevents the illegal or invalid output condition that can occur when both
inputs S and R are equal to logic level “1”. Due to this additional clocked input, a JK flip-
flop has four possible input combinations, “logic 1”, “logic 0”, “no change” and “toggle”.
The symbol for a JK flip flop is similar to that of an SR Bistable Latch as seen in the
previous tutorial except for the addition of a clock input.
The Basic JK Flip-flop

Both the S and the R inputs of the previous SR bistable have now been replaced by two
inputs called the J and K inputs, respectively after its inventor Jack Kilby. Then this
equates to: J = S and K = R.
The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-
input NAND gates with the third input of each gate connected to the outputs at Q and Q.
This cross coupling of the SR flip-flop allows the previously invalid condition of S = “1”
and R = “1” state to be used to produce a “toggle action” as the two inputs are now
interlocked.
If the circuit is now “SET” the J input is inhibited by the “0” status of Q through the
lower NAND gate. If the circuit is “RESET” the K input is inhibited by the “0” status
of Q through the upper NAND gate. As Q and Q are always different we can use them
to control the input. When both inputs J and K are equal to logic “1”, the JK flip flop
toggles as shown in the following truth table.
The Truth Table for the JK Function
Input Output Description

J K Q Q

0 0 0 0
Memory
no change
same as 0 0 0 1
for the
SR Latch 0 1 1 0
Reset Q » 0
0 1 0 1

1 0 0 1
Set Q » 1
1 0 1 0

1 1 0 1
toggle Toggle
action
1 1 1 0
Then the JK flip-flop is basically an SR flip flop with feedback which enables only one of
its two input terminals, either SET or RESET to be active at any one time thereby
eliminating the invalid condition seen previously in the SR flip flop circuit.
Also when both the J and the K inputs are at logic level “1” at the same time, and the
clock input is pulsed “HIGH”, the circuit will “toggle” from its SET state to a RESET
state, or visa-versa. This results in the JK flip flop acting more like a T-type toggle flip-
flop when both terminals are “HIGH”.
Although this circuit is an improvement on the clocked SR flip-flop it still suffers from
timing problems called “race” if the output Q changes state before the timing pulse of
the clock input has time to go “OFF”. To avoid this the timing pulse period ( T ) must be
kept as short as possible (high frequency). As this is sometimes not possible with
modern TTL IC’s the much improved Master-Slave JK Flip-flop was developed.
Master-Slave JK Flip-flop
The master-slave flip-flop eliminates all the timing problems by using two SR flip-flops
connected together in a series configuration. One flip-flop acts as the “Master” circuit,
which triggers on the leading edge of the clock pulse while the other acts as the “Slave”
circuit, which triggers on the falling edge of the clock pulse. This results in the two
sections, the master section and the slave section being enabled during opposite half-
cycles of the clock signal.
The TTL 74LS73 is a Dual JK flip-flop IC, which contains two individual JK type
bistable’s within a single chip enabling single or master-slave toggle flip-flops to be
made. Other JK flip flop IC’s include the 74LS107 Dual JK flip-flop with clear, the
74LS109 Dual positive-edge triggered JK flip flop and the 74LS112 Dual negative-edge
triggered flip-flop with both preset and clear inputs.
Asynchronous Upcounter
binary count sequences follow a pattern of octave (factor of 2) frequency
division, and that J-K flip-flop multivibrators set up for the “toggle” mode are capable
of performing this type of frequency division, we can envision a circuit made up of
several J-K flip-flops, cascaded to produce four bits of output. The main problem
facing us is to determine how to connect these flip-flops together so that they toggle
at the right times to produce the proper binary sequence. Examine the following
binary count sequence, paying attention to patterns preceding the “toggling” of a bit
between 0 and 1:

Note that each bit in this four-bit sequence toggles when the bit before it (the bit
having a lesser significance, or place-weight), toggles in a particular direction: from 1
to 0. Small arrows indicate those points in the sequence where a bit toggles, the head
of the arrow pointing to the previous bit transitioning from a “high” (1) state to a “low”
(0) state:
Starting with four J-K flip-flops connected in such a way to always be in the
“toggle” mode, we need to determine how to connect the clock inputs in such a way
so that each succeeding bit toggles when the bit before it transitions from 1 to 0. The
Q outputs of each flip-flop will serve as the respective binary bits of the final, four-bit
count:

If we used flip-flops with negative-edge triggering (bubble symbols on the clock

inputs), we could simply connect the clock input of each flip-flop to the Q output of the
flip-flop before it, so that when the bit before it changes from a 1 to a 0, the “falling
edge” of that signal would “clock” the next flip-flop to toggle the next bit:
 This circuit would yield the following output waveforms, when “clocked” by a
repetitive source of pulses from an oscillator:

The first flip-flop (the one with the Q0 output), has a positive-edge triggered
clock input, so it toggles with each rising edge of the clock signal. Notice how the
clock signal in this example has a duty cycle less than 50%. I’ve shown the signal in
this manner for the purpose of demonstrating how the clock signal need not be
symmetrical to obtain reliable, “clean” output bits in our four-bit binary sequence. In
the very first flip-flop circuit shown in this chapter, I used the clock signal itself as one
of the output bits. This is a bad practice in counter design, though, because it
necessitates the use of a square wave signal with a 50% duty cycle (“high” time =
“low” time) in order to obtain a count sequence where each and every step pauses for
the same amount of time. Using one J-K flip-flop for each output bit, however, relieves
us of the necessity of having a symmetrical clock signal, allowing the use of
practically any variety of high/low waveform to increment the count sequence.
As indicated by all the other arrows in the pulse diagram, each succeeding
output bit is toggled by the action of the preceding bit transitioning from “high” (1) to
“low” (0). This is the pattern necessary to generate an “up” count sequence.
A less obvious solution for generating an “up” sequence using positive-edge
triggered flip-flops is to “clock” each flip-flop using the Q’ output of the preceding flip-
flop rather than the Q output. Since the Q’ output will always be the exact opposite
state of the Q output on a J-K flip-flop (no invalid states with this type of flip-flop), a
high-to-low transition on the Q output will be accompanied by a low-to-high transition
on the Q’ output. In other words, each time the Q output of a flip-flop transitions from
1 to 0, the Q’ output of the same flip-flop will transition from 0 to 1, providing the
positive-going clock pulse we would need to toggle a positive-edge triggered flip-flop
at the right moment:
 One way we could expand the capabilities of either of these two counter
circuits is to regard the Q’ outputs as another set of four binary bits. If we examine the
pulse diagram for such a circuit, we see that the Q’ outputs generate a down-counting
sequence, while the Q outputs generate an up-counting sequence:

Unfortunately, all of the counter circuits shown thusfar share a common

problem: the ripple effect. This effect is seen in certain types of binary adder and data
conversion circuits, and is due to accumulative propagation delays between cascaded
gates. When the Q output of a flip-flop transitions from 1 to 0, it commands the next
flip-flop to toggle. If the next flip-flop toggle is a transition from 1 to 0, it will command
the flip-flop after it to toggle as well, and so on. However, since there is always some
small amount of propagation delay between the command to toggle (the clock pulse)
and the actual toggle response (Q and Q’ outputs changing states), any subsequent
flip-flops to be toggled will toggle some time after the first flip-flop has toggled. Thus,
when multiple bits toggle in a binary count sequence, they will not all toggle at exactly
the same time:

As you can see, the more bits that toggle with a given clock pulse, the more
severe the accumulated delay time from LSB to MSB. When a clock pulse occurs at
such a transition point (say, on the transition from 0111 to 1000), the output bits will
“ripple” in sequence from LSB to MSB, as each succeeding bit toggles and
commands the next bit to toggle as well, with a small amount of propagation delay
between each bit toggle. If we take a close-up look at this effect during the transition
from 0111 to 1000, we can see that there will be false output counts generated in the
brief time period that the “ripple” effect takes place:

Instead of cleanly transitioning from a “0111” output to a “1000” output, the

counter circuit will very quickly ripple from 0111 to 0110 to 0100 to 0000 to 1000, or
from 7 to 6 to 4 to 0 and then to 8. This behavior earns the counter circuit the name
of ripple counter, or asynchronous counter.
In many applications, this effect is tolerable, since the ripple happens very,
very quickly (the width of the delays has been exaggerated here as an aid to
understanding the effects). If all we wanted to do was drive a set of light-emitting
diodes (LEDs) with the counter’s outputs, for example, this brief ripple would be of no
consequence at all. However, if we wished to use this counter to drive the “select”
inputs of a multiplexer, index a memory pointer in a microprocessor (computer) circuit,
or perform some other task where false outputs could cause spurious errors, it would
not be acceptable. There is a way to use this type of counter circuit in applications
sensitive to false, ripple-generated outputs, and it involves a principle known
as strobing.
Most decoder and multiplexer circuits are equipped with at least one input
called the “enable.” The output(s) of such a circuit will be active only when the enable
input is made active. We can use this enable input to strobe the circuit receiving the
ripple counter’s output so that it is disabled (and thus not responding to the counter
output) during the brief period of time in which the counter outputs might be rippling,
and enabled only when sufficient time has passed since the last clock pulse that all
rippling will have ceased. In most cases, the strobing signal can be the same clock
pulse that drives the counter circuit:

With an active-low Enable input, the receiving circuit will respond to the binary
count of the four-bit counter circuit only when the clock signal is “low.” As soon as the
clock pulse goes “high,” the receiving circuit stops responding to the counter circuit’s
output. Since the counter circuit is positive-edge triggered (as determined by
the first flip-flop clock input), all the counting action takes place on the low-to-high
transition of the clock signal, meaning that the receiving circuit will become disabled
just before any toggling occurs on the counter circuit’s four output bits. The receiving
circuit will not become enabled until the clock signal returns to a low state, which
should be a long enough time after all rippling has ceased to be “safe” to allow the
new count to have effect on the receiving circuit. The crucial parameter here is the
clock signal’s “high” time: it must be at least as long as the maximum expected ripple
period of the counter circuit. If not, the clock signal will prematurely enable the
receiving circuit, while some rippling is still taking place.
Another disadvantage of the asynchronous, or ripple, counter circuit is limited
speed. While all gate circuits are limited in terms of maximum signal frequency, the
design of asynchronous counter circuits compounds this problem by making
propagation delays additive. Thus, even if strobing is used in the receiving circuit, an
asynchronous counter circuit cannot be clocked at any frequency higher than that
which allows the greatest possible accumulated propagation delay to elapse well
before the next pulse.
The solution to this problem is a counter circuit that avoids ripple altogether.
Such a counter circuit would eliminate the need to design a “strobing” feature into
whatever digital circuits use the counter output as an input, and would also enjoy a
much greater operating speed than its asynchronous equivalent. This design of
counter circuit is the subject of the next section.

BCD or Decade Counter Circuit

A binary coded decimal (BCD) is a serial digital counter that counts ten digits .And it
resets for every new clock input. As it can go through 10 unique combinations of output,
it is also called as “Decade counter”. A BCD counter can count 0000, 0001, 0010, 1000,
1001, 1010, 1011, 1110, 1111, 0000, and 0001 and so on.
A 4 bit binary counter will act as decade counter by skipping any six outputs out of the
16 (24) outputs. There are some available ICs for decade counters which we can readily
use in our circuit, like 74LS90. It is an asynchronous decade counter.

The above figure shows a decade counter constructed with JK flip flop. The J output
and K outputs are connected to logic 1. The clock input of every flip flop is connected to
the output of next flip flop, except the last one.
The output of the NAND gate is connected in parallel to the clear input ‘CLR’ to all the
flip flops. This ripple counter can count up to 16 i.e. 24.

Decade Counter Operation

When the Decade counter is at REST, the count is equal to 0000. This is first stage of
the counter cycle. When we connect a clock signal input to the counter circuit, then the
circuit will count the binary sequence. The first clock pulse can make the circuit to count
up to 9 (1001). The next clock pulse advances to count 10 (1010).
Then the ports X1 and X3 will be high. As we know that for high inputs, the NAND gate
output will be low. The NAND gate output is connected to clear input, so it resets all the
flip flop stages in decade counter. This means the pulse after count 9 will again start the
count from count 0.

Truth Table of Decade Counter

The above table describes the counting operation of Decade counter. It represents the
count of circuit for decimal count of input pulses. The NAND gate output is zero when
the count reaches 10 (1010).
The count is decoded by the inputs of NAND gate X1 and X3. After count 10, the logic
gate NAND will trigger its output from 1 to 0, and it resets all flip flops.
Full Adder
This type of adder is a little more difficult to implement than a half-adder. The
main difference between a half-adder and a full-adder is that the full-adder has three
inputs and two outputs. The first two inputs are A and B and the third input is an input
carry designated as CIN. When a full adder logic is designed we will be able to string
eight of them together to create a byte-wide adder and cascade the carry bit from one
adder to the next.
The output carry is designated as COUT and the normal output is designated as
S. Take a look at the truth-table.
INPUTS OUTPUTS
A B CIN COUT S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
From the above truth-table, the full adder logic can be implemented. We can see
that the output S is an EXOR between the input A and the half-adder SUM output with B
and CIN inputs. We must also note that the COUT will only be true if any of the two
inputs out of the three are HIGH.
Thus, we can implement a full adder circuit with the help of two half adder
circuits. The first will half adder will be used to add A and B to produce a partial Sum.
The second half adder logic can be used to add CIN to the Sum produced by the first
half adder to get the final S output. If any of the half adder logic produces a carry, there
will be an output carry. Thus, COUT will be an OR function of the half-adder Carry
outputs. Take a look at the implementation of the full adder circuit shown below.

Full Adder Circuit

Though the implementation of larger logic diagrams is possible with the above
full adder logic a simpler symbol is mostly used to represent the operation. Given below
is a simpler schematic representation of a one-bit full adder.
 Single-bit Full Adder
With this type of symbol, we can add two bits together taking a carry from the next lower
order of magnitude, and sending a carry to the next higher order of magnitude. In a
computer, for a multi-bit operation, each bit must be represented by a full adder and
must be added simultaneously. Thus, to add two 8-bit numbers, you will need 8 full
adders which can be formed by cascading two of the 4-bit blocks. The addition of two 4-
bit numbers is shown below.
 BASIC ELECTRICAL AND ELECTRONICS ENGINEERING

Assignment III

1.Explain the construction andoperation of JK flip flop.

2.With neat diagram discuss the three bit asynchronous up counter

3.Discuss the construction and working principle of decade counter

4.Briefthe operation of full adder with necessary diagram.