Three-dimensional integrated circuit

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In electronics, a three-dimensional integrated circuit (3D IC, 3D-IC, or 3-D IC) is a

chip in which two or more layers of active electronic components are integrated both
vertically and horizontally into a single circuit. The semiconductor industry is hotly
pursuing this promising technology in many different forms, but it is not yet widely used;
consequently, the definition is still somewhat fluid.

Contents
[hide]

• 1 3D ICs vs. 3D packaging

• 2 Manufacturing technologies
• 3 Benefits
• 4 Challenges
• 5 References
• 6 Further reading
• 7 External links
o 7.1 Potential Applications
o 7.2 Early products
o 7.3 Organizations

o 7.4 Selected press references

[edit] 3D ICs vs. 3D packaging

3D packaging saves space by stacking separate chips in a single package. This packaging,
known as System in Package (SiP) or Chip Stack MCM, does not integrate the chips into
a single circuit. The chips in the package communicate with off-chip signaling, much as
if they were mounted in separate packages on a normal circuit board. In contrast, a 3D IC
is a single chip. All components on the layers communicate with on-chip signaling,
whether vertically or horizontally. Essentially, a 3D IC bears the same relation to a 3D
package that an SoC bears to a circuit board.

[edit] Manufacturing technologies

As of 2008 there are four ways to build a 3D IC:
Monolithic – Electronic components and their connections (wiring) are built in layers on
a single semiconductor wafer, which is then diced into 3D ICs. There is only one
substrate, hence no need for aligning, thinning, bonding, or through-silicon vias.
Applications of this method are currently limited because creating normal transistors
requires enough heat to destroy any existing wiring. This monolithic 3D-IC technology
has been researched at Stanford university under a DARPA sponsored grant.

Wafer-on-Wafer – Electronic components are built on two or more semiconductor

wafers, which are then aligned, bonded, and diced into 3D ICs. Each wafer may be
thinned before or after bonding. Vertical connections are either built into the wafers
before bonding or else created in the stack after bonding. These “through-silicon vias”
(TSVs) pass through the silicon substrate(s) between active layers and/or between an
active layer and an external bond pad.

Die-on-Wafer – Electronic components are built on two semiconductor wafers. One

wafer is diced; the singulated dies are aligned and bonded onto die sites of the second
wafer. As in the wafer-on-wafer method, thinning and TSV creation are performed either
before or after bonding. Additional dies may be added to the stacks before dicing.

Die-on-Die – Electronic components are built on multiple dies, which are then aligned
and bonded. Thinning and TSV creation may be done before or after bonding.

[edit] Benefits
3D ICs offer many significant benefits, including:

Footprint – More functionality fits into a small space. This extends Moore’s Law and
enables a new generation of tiny but powerful devices.

Speed – The average wire length becomes much shorter. Because propagation delay is
proportional to the square of the wire length, overall performance increases.

Power – Keeping a signal on-chip reduces its power consumption by ten to a hundred
times.[1] Shorter wires also reduce power consumption by producing less parasitic
capacitance. Reducing the power budget leads to less heat generation, extended battery
life, and lower cost of operation.

Design – The vertical dimension adds a higher order of connectivity and opens a world of
new design possibilities.

Cost - Partitioning a large chip to be multiple smaller dies with 3D stacking could
potentially improve the yield and reduce the fabrication cost. [2]

Heterogeneous integration – Circuit layers can be built with different processes, or even
on different types of wafers. This means that components can be optimized to a much
greater degree than if they were built together on a single wafer. Even more interesting,
components with completely incompatible manufacturing could be combined in a single
device[3].

Circuit security - The stacked structure hinders attempts to reverse engineer the
circuitry. Sensitive circuits may also be divided among the layers in such a way as to
obscure the function of each layer.[4]

Bandwidth - 3D integration allows large numbers of vertical vias between the layers.
This allows construction of wide bandwidth buses between functional blocks in different
layers. A typical example would be a processor+memory 3D stack, with the cache
memory stacked on top of the processor. This arrangement allows a bus much wider than
the typical 128 or 256 bits between the cache and processor. Wide buses in turn alleviate
the memory wall problem.[5]

[edit] Challenges
Because this technology is new it carries new challenges, including:

Cost - Each active plane of a 3DIC has its own 2D manufacturing cost. In the fully
stacked product, the manufacturing costs obviously add up.

Yield - Each extra manufacturing step adds a risk for defects. In order for 3D ICs to be
commercially viable, defects must be avoided or repaired[6].

Heat - Thermal buildup within the stack must be prevented or dissipated. This is an
inevitable issue as electrical proximity goes hand-in-hand with thermal proximity.

Design complexity - Taking full advantage of 3D requires intricate and elegant multi-
level designs. Chip designers will need new CAD tools to address the 3D paradigm.[7]

Lack of standards - There are currently no standards for TSV-based 3DIC packaging. In
addition, there are still many integration options which are being explored, such as via-
last, via-first, via-middle, etc.

Lack of relevance after insertion - With the use of TSVs, bandwidth and speed and
power consumption are no longer dominated by the long-distance interconnects, but by
the performance of individual discrete components on each individual chip active layer.
Any further improvements in the 3DIC package or interconnect technology will not be
obviously noticed until improvements to the various component technologies are carried
out.

Heterogeneous integration supply chain - In heterogeneously integrated systems, the

delay of one part from one of the different parts suppliers delays the delivery of the whole
product, and so delays the revenue for each of the 3DIC part suppliers.
Lack of clearly defined ownership - It is unclear who should own the 3DIC integration
and packaging/assembly. It could be assembly houses like ASE or the product OEMs.

[edit] References
1. ^ William J. Dally, “Future Directions for On-Chip Interconnection Networks”
page 17, http://www.ece.ucdavis.edu/~ocin06/talks/dally.pdf Computer Systems
Laboratory Stanford University, 2006
2. ^ Xiangyu Dong and Yuan Xie, "System-level Cost Analysis and Design
Exploration for 3D ICs", Proc. of Asia and South Pacific Design Automation
Conference, 2009, http://www.cse.psu.edu/~yuanxie/3d.html
3. ^ James J-Q Lu, Ken Rose, & Susan Vitkavage “3D Integration: Why, What,
Who, When?” http://www.future-fab.com/documents.asp?d_ID=4396 Future Fab
Intl. Volume 23, 2007
4. ^ "3D-ICs and Integrated Circuit Security"
http://www.tezzaron.com/about/papers/3D-
ICs_and_Integrated_Circuit_Security.pdf Tezzaron Semiconductor, 2008
5. ^ "Predicting the Performance of a 3D Processor-Memory Chip Stack" Jacob, P.,
McDonald, J.F. et al.Design & Test of Computers, IEEE Volume 22, Issue 6,
Nov.-Dec. 2005 Page(s):540 - 547
6. ^ Robert Patti, "Impact of Wafer-Level 3D Stacking on the Yield of ICs"
http://www.future-fab.com/documents.asp?d_ID=4415 Future Fab Intl. Volume
23, 2007
7. ^ "EDA's big three unready for 3D chip packaging"
http://www.eetasia.com/ART_8800485666_480300_NT_fcb98510.HTM EE
Times Asia October 25, 2007

[edit] Further reading

• Philip Garrou, Christopher Bower, Peter Ramm: Handbook of 3D Integration,
Technology and Applications of 3D Integrated Circuits 2nd Edition. Wiley-VCH,
Weinheim 2008, ISBN: 978-3527-32034-9.
• Yuan Xie, Jason Cong, Sachin Sapatnekar: Three-Dimensional Integrated Circuit
Design: Eda, Design And Microarchitectures, Publisher: Springer, ISBN:
1441907831,9781441907837,978-1441907837, Publishing Date: Dec 2009
• Advancements in Stacked Chip Scale Packaging (S-CSP), Provides System-in-a-
Package Functionality for Wireless and Handheld Applications White Paper
• Evaluation for UV Laser Dicing Process and its Reliability for Various Designs of
Stack Chip Scale Package White Paper

[edit] External links

[edit] Potential Applications
 • 2007, 3D FPGA: [1] "Performance Benefits of Monolithically Stacked 3D-FPGA
(invited)", Mingjie Lin, Abbas El Gamal, Yi-chang Lu, and Simon Wong, IEEE
Transactions on Computer-aided Design of Integrated Circuits and Systems,
Volume 26, Issue 2.

[edit] Early products

• 2001, Monolithic write-once memory: “Matrix preps 64-Mbyte write-once

memory” EE Times
• 2004, Wafer-to-wafer RAM: “MagnaChip, Tezzaron form partnership for 3D
chips” EE Times
• 2007, Die-to-wafer focal plane array: “Ziptronix, Raytheon Prove 3-D Integration
of 0.5 µm CMOS Device” Semiconductor International

[edit] Organizations

• 3D-IC Alliance
• EMC3D
• RTI “TechVenture” Forum
• SEMATECH
• IMEC
• Amkor Technology

[edit] Selected press references

• 2003, EE Design: “Three-dimensional SoCs perform for future”

• 2004, EDN: “3D Interconnect Technology Coming to Light”
• 2005, Semiconductor International: “Three-Dimensional ICs Solve the
Interconnect Paradox”
• 2006, Solid State Technology: “Mapping progress in 3D IC integration”
• 2007, Nikkei Electronics Asia: “Vertical Stacking to Redefine Chip Design”
• 2008, Semiconductor International: “How Might 3-D ICs Come Together?”
• 2009, Advanced Packaging: “Signs of 3D Maturity”

Retrieved from "http://en.wikipedia.org/wiki/Three-dimensional_integrated_circuit"

Categories: Integrated circuits | Semiconductor device fabrication | Packaging
(microfabrication)

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