Structure and Style of the UG Project Report

(Instructions for BE IV Electronics)

The UG project reports should follow the following structure and sequence:

1. Title – First (on the cover) and Second (inside).

2. Certificate
3. Acknowledgement
4. Abstract –one-two pages giving salient features of the project.
5. Detailed table of contents – with chapter, section and subsection numbers.
6. List of figures – numbered as per the sequence in which they appear in the report.
7. List of tables – numbered as per the sequence in which they appear in the report.
8. Chapter 1 (Introduction) – overview of the project and brief description of the contents
of other chapters.
9. Chapter 2 (Theoretical Background) – should give the theoretical aspects of the project
including the working principle.
10.Chapter 3 (Functional Description) – implementation details including hardware and
software designs with necessary diagrams, algorithms, flowcharts etc.
11.Chapter 4 (Simulation and Testing) – details of simulation and testing actually carried
out along with procedures and necessary diagrams.
12.Chapter 5 (Results and Conclusion) – discussion of the simulation and testing results and
conclusions drawn. Possibilities for further extension of the work.
13.Bibliography – in IEEE format.
14.Index

Formatting Instructions

 Font size – Title (20), heading (16), subheading (14), text (12).
 Fonts – Times New Roman/Arial/Calibri
 Page – size A4, line spacing 1.5.
 Margins – left 1.25 inches and others 1 inch.
 Page number – bottom center. Page numbers for items 1 to 7 should be in Romans.
 No other header, footer or borders.

Note: 1. For the formats of the Title and Certificate refer last year project reports which are
available in the library
2. See to it that, the content of your report include more of write-up and less of images &
Pictures
 Figure 2.1: PD explanatory model due to void
Figure 2.5.1 A typical finite element subdivision of an irregular domain.
Figure 2.5.2Typical triangular element; the local node numbering 1-2-3 must be counterclockwise as indicated by the arrow.
Figure 3.1 A schematic diagram of a void in an insulation system

Figure 3.2(a) Gemant and Philippoff’s capacitive model

Figure 3.2(b) : The Void Model
Figure 3.3: Cross-sectional area of an XLPE cable indicating the void location
between the core and outer-sheath
Figure 3.5 flow chart for FEMM
figure 3.6 Model configuration in MATLAB simulink
Figure 4.1(a) single core XLPE cable in FEMM and it’s Electric field Density (stress).
Figure 4.1(b) stress distribution in insulation of XLPE
Figure 4.2.1 stress distribution with spherical void
Figure 4.2.2 stress distribution in cylindrical cavity
Figure 4.2.3 stress distribution in elliptical void
Figure 4.3.1 effect of different void size
Figure 4.3.2 effect of different void location
Figure 4.3.3 effect of different void size
Figure 4.4.1: PD Current result for 1.0 mm void distance location………..…. 26
Figure 4.4.2: PD Current result for 1.5mm void distance location…………… 27
Figure 4.4.3: PD Current result for 2.0mm void distance location…………… 27
Figure 4.4.4: PD Current result for 2.5mm void distance location …….……. 28
Figure 4.4.5: PD Voltage result for 3.0mm void distance location…………... 28
Figure 4.4.6: Plot of PD current for varied void distances…....……………… 29
Figure 4.4.7: PD current against void sizes…………………………………...

2.3.1 Void ….………………………………………………….................. 5

2.3.2 Irregularities (e.g. sharp points) on the surface of insulating
material……………………………………………………………..
5
2.3.3 Bubbles in liquid insulation ………………………….……………. 5
2.3 4 Discharges around an electrode in gas (corona activity)……….…... 6
2.3.5 Mechanical failure or damage to insulation materials
2.4.1 In Solid Dielectric ……………………………………………….... 7
2.4.2 In paper-insulated high-voltage cables
2.5.1 Finite Element Discretization
2.5.2 Element Governing Equations
2.5.3 Assembling of All Elements
2.5.4 Solving the Resulting Equations
4.2.1 Spherical void inside the insulation
4.2.2 Cylindrical void inside the insulation.
4.2.3 Eliptical void inside the insulation.
4.3.1 Effect of Different Void Sizes
4.3.2 Effect of Different Void Locations
4.3.3 Effect of Different Void Shapes
4.4.1 Change in pd current with void location.
4.4.2 Simulation result of PD current compared with different void sizes
Table 1 Calculated parameters for the considered void locations
Table 2 change in stress with change in void size
Table 3 change in stress with change in void location
table 4 change in stress with change in void shapes.
Table 5 PD current of each void distances from the conductor