Data Sheet No.

PD60251

IRS2112(-1,-2,S)PbF
HIGH AND LOW SIDE DRIVER
Features
• Floating channel designed for bootstrap operation Product Summary
• Fully operational to +600 V
• Tolerant to negative transient voltage, dV/dt VOFFSET 600 V max.
immune
• Gate drive supply range from 10 V to 20 V IO+/- 200 mA / 440 mA
• Undervoltage lockout for both channels
• 3.3 V logic compatible VOUT 10 V - 20 V
• Separate logic supply range from 3.3 V to 20 V
• Logic and power ground +/- 5 V offset ton/off (typ.) 135 ns & 105 ns
• CMOS Schmitt-triggered inputs with pull-down
• Cycle by cycle edge-triggered shutdown logic Delay Matching 30 ns
• Matched propagation delay for both channels
• Outputs in phase with inputs Packages
• RoHS compliant
Description 14-Lead PDIP
IRS2112
The IRS2112 is a high voltage, high speed power 16-Lead PDIP
MOSFET and IGBT driver with independent high- and (w/o leads 4 & 5)
low-side referenced output channels. Proprietary HVIC IRS2112-2
and latch immune CMOS technologies enable rug-
14-Lead PDIP
gedized monolithic construction. Logic inputs are com- (w/o lead 4)
patible with standard CMOS or LSTTL outputs, down IRS2112-1
to 3.3 V logic. The output drivers feature a high pulse
16-Lead SOIC
current buffer stage designed for minimum driver IRS2112S
cross-conduction. Propagation delays are matched
to simplify use in high frequency applications. The
floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration
which operates up to 600 V.

up to 600 V
Typical Connection

HO
V DD VDD VB
HIN HIN VS
TO
SD SD LOAD

LIN LIN VCC

V SS VSS COM
V CC LO

(Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only. Please
refer to our Application Notes and DesignTips for proper circuit board layout.

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 IRS2112(-1,-2,S)PbF

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figs. 28 through 35.
Symbol Definition Min. Max. Units
VB High-side floating supply voltage -0.3 625
VS High-side floating supply offset voltage VB - 25 VB + 0.3
VHO High-side floating output voltage VS - 0.3 VB + 0.3
VCC Low-side fixed supply voltage -0.3 25 V
VLO Low- side output voltage -0.3 VCC + 0.3
VDD Logic supply voltage -0.3 VSS + 25
VSS Logic supply offset voltage VCC - 25 VCC + 0.3
VIN Logic input voltage (HIN, LIN & SD) VSS - 0.3 VDD + 0.3
dVs/dt Allowable offset supply voltage transient (Fig. 2) — 50 V/ns
(14 Lead DIP) — 1.6
PD Package power dissipation @ TA ≤ +25 °C W
(16 Lead SOIC) — 1.25
(14 Lead DIP) — 75
RTHJA Thermal resistance, junction to ambient °C/W
(16 Lead SOIC) — 100
TJ Junction temperature — 150
TS Storage temperature -55 150 °C
TL Lead temperature (soldering, 10 seconds) — 300

Recommended Operating Conditions

The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15 V differential. Typical
ratings at other bias conditions are shown in Figs. 36 and 37.
Symbol Definition Min. Max. Units
VB High-side floating supply absolute voltage VS + 10 VS + 20
VS High-side floating supply offset voltage Note 1 600
VHO High-side floating output voltage VS VB
VCC Low-side fixed supply voltage 10 20
V
VLO Low- side output voltage 0 VCC
VDD Logic supply voltage VSS + 3 VSS + 20
VSS Logic supply offset voltage -5 (Note 2) 5
VIN Logic input voltage (HIN, LIN & SD) VSS VDD
TA Ambient temperature -40 125 °C
Note 1: Logic operational for VS of -5 V to +600 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design
Tip DT97-3 for more details).
Note 2: When VDD < 5 V, the minimum VSS offset is limited to -VDD.

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 IRS2112(-1,-2,S)PbF

Dynamic Electrical Characteristics

VBIAS (VCC , VBS, VDD ) = 15 V, CL = 1000 pF, TA = 25 °C and VSS = COM unless otherwise specified. The dynamic
electrical characteristics are measured using the test circuit shown in Fig. 3.

Symbol Definition Min. Typ. Max. Units Test Conditions

ton Turn-on propagation delay — 135 180 VS = 0 V
toff Turn-off propagation delay — 130 160
VS = 600 V
tsd Shutdown propagation delay — 130 160
ns
tr Turn-on rise time — 75 130
tf Turn-off fall time — 35 65
MT Delay matching, HS & LS Turn-on/off — — 30

Static Electrical Characteristics

VBIAS (VCC, VBS, VDD) = 15 V, TA = 25 °C and VSS = COM unless otherwise specified. The VIN, VTH, and IIN parameters
are referenced to VSS and are applicable to all three logic input leads: HIN, LIN, and SD. The VO and IO parameters are
referenced to COM and are applicable to the respective output leads: HO or LO.

Symbol Definition Min. Typ. Max. Units Test Conditions

VIH Logic “1” input voltage 9.5 — —
VIL Logic “0” input voltage — — 6.0
V
VOH High level output voltage, VBIAS - VO — 0.05 0.2
IO = 2 mA
VOL Low level output voltage, VO — 0.02 0.1
ILK Offset supply leakage current — — 50 VB = VS = 600 V
IQBS Quiescent VBS supply current — 25 100
IQCC Quiescent VCC supply current — 80 180 VIN = 0 V or VDD
µA
IQDD Quiescent VDD supply current — 2.0 30
IIN+ Logic “1” input bias current — 20 40 VIN = VDD
IIN- Logic “0” input bias current — — 1.0 VIN = 0 V
VBS supply undervoltage positive going
VBSUV+ 7.4 8.5 9.6
threshold
VBS supply undervoltage negative going
VBSUV- 7.0 8.1 9.2
threshold V
VCC supply undervoltage positive going
VCCUV+ 7.6 8.6 9.6
threshold
VCC supply undervoltage negative going
VCCUV- 7.2 8.2 9.2
threshold
VO = 0 V, VIN = VDD
IO+ Output high short circuit pulsed current 200 290 —
PW ≤ 10 µs
mA
VO = 15 V, VIN = 0 V
IO- Output low short circuit pulsed current 420 600 —
PW ≤ 10 µs

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 IRS2112(-1,-2,S)PbF

Functional Block Diagram

VB
UV
VDD DETECT
R Q
HV
LEVEL PULSE R HO
R Q SHIFT
S VDD /VCC FILTER S
HIN LEVEL
SHIFT PULSE VS
GEN

SD
VCC
UV
DETECT
VDD /VCC
LIN LEVEL LO
S SHIFT
R Q DELAY

VSS COM

Lead Definitions
Symbol Description
VDD Logic supply
HIN Logic input for high-side gate driver output (HO), in phase
SD Logic input for shutdown
LIN Logic input for low-side gate driver output (LO), in phase
VSS Logic ground
VB High-side floating supply
HO High-side gate drive output
VS High-side floating supply return
VCC Low-side supply
LO Low-side gate drive output
COM Low-side return

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 IRS2112(-1,-2,S)PbF

Lead Assignments

14 Lead PDIP 16 Lead SOIC (Wide Body)

IRS2112 IRS2112S

14 Lead PDIP w/o lead 4 16 Lead PDIP w/o leads 4 & 5

IRS2112-1 IRS2112-2

Part Number

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 IRS2112(-1,-2,S)PbF

VCC = 15 V
HV = 10 V to 600 V

10 k F6
10 0.1
HIN 200 100
µF µF 0.1 10 k
LIN µH µF
µF F6
9 3 6
10 5
SD 7
11 HO
dVs
1
10 k F6
12 ct
OUTPUT
HO MONITOR
LO
13 2
IRF820

Figure 1. Input/Output Timing Diagram Figure 2. Floating Supply Voltage Transient Test
Circuit
VCC = 15 V
HV = 10 V to 600 V

10 0.1 VB
µF µF 0.1 10 +
HIN 50% 50%
µF µF 15 V
9 3 6
- VS
LIN
10 5
CL (0 V to 600 V)
HIN 7 ton tr toff tf
11 HO 10
SD 1 µF
90% 90%
12 LO
LIN
CL HO
LO 10% 10%
13 2

Figure 3. Switching Time Test Circuit Figure 4. Switching Time Waveform Definition

HIN 50% 50%

LIN
50%
SD LO HO
tsd
10%
HO 90%
MT MT
LO
90%

LO HO

Figure 5. Shutdown Waveform Definitions Figure 6. Delay Matching Waveform Definitions

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 IRS2112(-1,-2,S)PbF

250 250
Tu rn- On Delay Tim e ( ns) .

Tu rn- On Delay Tim e ( ns ) .

M ax

200 200
M ax.
150 150
T yp.

100 100
Typ.

50 50

0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20

Temperature(oC) V CC / V BS Supply V oltage (V )

Figure 7A. Turn-On Propagation Delay Time Figure 7B. Turn-On Propagation Delay Time
vs. Temperature vs. VCC/VBS Supply Voltage
400
250
Tur n-O n Delay Tim e ( ns) .

M ax.
Turn- Off Time (ns )

300 200

150
M ax.
200
Typ.
100
Typ .
100
50

0 0
0 2 4 6 8 10 12 14 16 18 20 - 50 -25 0 25 50 75 100 125

V DD Supply V oltage (V ) Temperature(oC)

Figure 8A. Turn-Off Propagation Delay Time

Figure 7C. Turn-On Propagation Delay Time
vs. Temperature
vs. VDD Supply Voltage

250 400
Tur n-O ff Delay Tim e ( ns )

M ax.
200 M ax .
Tu rn- O ff T im e (ns )

300

150
Typ.
200
100
T yp.
100
50

0 0
10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20

V CC/V BS Supply V oltage (V ) V DD Supply V oltage (V )

Figure 8B. Turn-Off Propagation Delay Time Figure 8C. Turn-Off Propagation Delay Time
vs. VCC/VBS Supply Voltage vs. VDD Supply Voltage

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 IRS2112(-1,-2,S)PbF

250 250
Shutdow n D elay Time (ns)

Sh utd ow n D ela y T ime ( n s )

M ax.
200 200

150 150
M ax.
Typ.
100 100
Typ .

50 50

0 0
- 50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature(oC) V C C /V BS Supply V oltage (V )
Figure 9A. Shutdown Delay Time Figure 9B. Shutdown Delay Time
vs. Temperature vs. VCC/VBS Supply Voltage
400 250
Shutdown De lay Time (ns )

Tur n-O n Ris e T ime (ns) .

M ax .
300 200

150
200 M ax.

T yp.
100
100
50
T yp.

0 0
0 2 4 6 8 10 12 14 16 18 20 -5 0 -25 0 25 50 75 100 125
V DD Supply V oltage (V ) o
Temperature ( C)

Figure 9C. Shutdown Time vs. VDD Supply Voltage Figure 10A. Turn-On Rise Time vs. Temperature

250 125
Tur n-O n Ris e Time (ns) .

Tur n- O ff Fal l T im e ( ns )

200 100
M ax

150 75
M ax.
100 50
Typ
50 25 Typ.

0 0
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
o
V BIAS Supply V oltage (V ) Temper ature ( C)

Figure 10B. Turn-On Rise Time vs. Voltage Figure 11A. Turn-Off Fall Time vs. Temperature

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 IRS2112(-1,-2,S)PbF

125 15

Logic "1" Input Threshold (V)

Tur n- O ff Fal l Tim e ( ns)

100 12
M ax Min.
75 9

50 6

Typ 3
25

0
0
-50 -25 0 25 50 75 100 125
10 12 14 16 18 20
V BIAS Supply Voltage (V ) Temperature (°C)
Figure 11B. Turn-Off Fall Time vs. Supply Voltage Figure 12A. Logic “I” Input Threshold
vs. Temperature
15

15
Logic " 1 " Input Treshold (V)

Logic "0" Input Threshold (V)

12

12

9
9

Min. Max.
6
6
3

3
0

0
2.5 5 7.5 10 12.5 15 17.5 20 -5 0 -2 5 0 25 50 75 100 125

V DD Logic Supply Voltage (V) Temperature (°C)

Figure 12B. Logic “I” Input Threshold Figure 13A. Logic “0” Input Threshold
vs. Voltage vs. Temperature
15

1.0
Logic " 0 " Input Treshold (V)

High Lev el O utput Voltag e ( V)

12

0.8

0.6
9

0.4
6

Max. M ax.
0.2
3

0.0
0

2.5 5 7.5 10 12.5 15 17.5 20 -50 - 25 0 25 50 75 100 125

V DD Logic Supply Voltage (V) Temperature ( oC)

Figure 13B. Logic “0” Input Threshold Figure 14A. High Level Output Voltage
vs. Voltage vs. Temperature (Io = 2 mA)

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 IRS2112(-1,-2,S)PbF

1.0 1.0

Low L ev el O utput Vo ltage ( V)

Hig h Level O utput Voltage (V)

0.8 0.8

0.6 0.6

0.4 0.4

M ax
0.2 0.2
M ax

0.0 0.0
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
o
Temperature ( C)
V BAIS Supply V oltage (V )

Figure 14B. High Level Output Voltage Figure 15A. Low Level Output Voltage
vs. Supply Voltage (Io = 2 mA) vs. Temperature (Io = 2 mA)

1.0 200
Low Level Output Voltage (V)

VBS Supply Current (µA)

0.8
150
0.6
100
0.4 M ax.

0.2 50
M ax Typ.

0.0 0
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
V BAIS Supply Volt age (V) Temperature ( C) o

Figure 15B. Low Level Output Voltage vs.

Supply Voltage (Io = 2 mA) Figure 16A. VBS Supply Current vs. Temperatur e

200 100
VBS Supply Current (µA)
VBS Supply Current (µA)

150 80

60
100 Max.
M ax.
40
50
Typ. 20

0
Typ.
0
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
V BS Supply Voltage (V) Tem perature (°C )

Figure 16B. V BS Supply Current vs. Figure 17A. VBS Supply Current vs. Temperature
Voltage

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 IRS2112(-1,-2,S)PbF

100 300

VCC Supply Current (µA)

VBS Supply Current (µA)

250
80
M ax.
200
60
Max.
150
40 Ty p.
100
20
50
Typ.
0 0
10 12 14 16 18 20 -5 0 -2 5 0 25 50 75 100 125
Temperature (°C)
V B S Floating S upply Voltage (V )

Figure 17B. VBS Supply Current vs. Voltage Figure 18A. VCC Supply Current vs. Temperature

300 12

250 10
Vcc Supply Current (µA)

VDD Supply Current (µA)

Max.
200 8
Max.
150 6
Typ.
100 4
Typ.
50 2

0 0
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
Temperature (°C)
V cc Fixed Supply Voltage (V)

Figure 18B. VCC Supply Current vs. Voltage Figure 19A. VDD Supply Current vs. Temperature

12 100
Logic "1 " Input Bias Current (µA)
V DD S u p p ly C u rre n t (µA)

10 80

8
60
Max.
6 Max.
40
4

2 20
Typ. Typ.
0 0
0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VDD Logic Supply Voltage (V) Temperature (°C)

Figure 19B. VDD Supply Current vs. VDD Voltage Figure 20A. Logic “I” Input Current vs. Temperature

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 IRS2112(-1,-2,S)PbF

100 6
Logic "1" Input Bias Current (uA)

Logic "0" Input Bias Current (µA)

5 Max
80
4
60
Max.
3
40
2
20
Typ. 1

0 0
0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VDD Logic Supply Voltage (V)
Temperature (°C)

Figure 20B. Logic “1” Input Current vs. V DD Voltage Figure 21A. Logic "0" Input Bias Current
vs. Temperature
6
Logic "0" Input Bias Current (µA)

VBS Undervoltage Lockout +(V) 11

5 Max
10
Max.
4
9
3 Typ.
8
2 Min.
1 7

0 6
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
Supply Voltage (V) Temperature (°C)
Figure 21B. Logic "0" Input Bias Current Figure 22. VBS Undervoltage (+) vs. Temperature
vs. Voltage
11 11
VBS Undervoltage Lockout -(V)

VCC Undervoltage Lockout +(V)

10 10
Max.
Max.
9 9
Typ.
Typ.
8 8
Min.
Min.
7 7

6 6
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (oC )

Figure 23. VBS Undervoltage (-) vs. Temperature Figure 24. VCC Undervoltage (-) vs. Temperature

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 IRS2112(-1,-2,S)PbF
VCC Undervoltage Lockout - (V)

11 500

Ou tpu t S our c e Cu r r e nt ( mA )
10 400
T yp.
Max.
9 300
Typ.
8 200 M in.

Min. 100
7

0
6
-50 -25 0 25 50 75 100 125 - 50 - 25 0 25 50 75 100 125
Temperature (°C) o
Temperature ( C)

Figure 25. VCC Undervoltage (-) vs. Temperature Figure 26A. Output Source Current vs.
Temperature
500 750
O u tp u t So u r c e C u r r e n t ( m A )

T yp.
Ou tpu t S ink Cu rre nt ( mA )

400 600
M in.
300 450

200 300
Typ .

100 150
M in.

0 0
10 12 14 16 18 20 - 50 - 25 0 25 50 75 100 12 5

V BIA S Supply Voltage ( V) Temperatu re ( oC)

Figure 26B. Output Source Current Figure 27A. Output Sink Current
vs. Supply Voltage vs. Temperature

750
Ou tpu t Sink Cur ren t (m A )

600

450
Typ.

300
M in.
150

0
10 12 14 16 18 20
V BIA S Supply V oltage (V )

Figure 27B. Output Sink Current vs. Supply Voltage

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 IRS2112(-1,-2,S)PbF

150 150
320 V
Junction Temperature (°C)

Junction Temperature (°C)

125 320 V 125

100 100 140 V

75 75
140 V
50 10 V 50 10 V

25 25

0 0
1E+2 1E+3 1E+4 1E+5 1E+6 1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz) Frequency (Hz)
Figure 28. IRS2112 TJ vs. Frequency (IRFBC20) Figure 29. IRS2112 TJ vs. Frequency (IRFBC30)
RGATE = 33 Ω , VCC = 15 V RGATE = 22 Ω , VCC = 15 V
320 V 320 V 140 V 10 V
150 150
Junction Temperature (°C)

Junction Temperature (°C)

125 125
140 V
100 100
10 V

75 75

50 50

25 25

0 0
1E+2 1E+3 1E+4 1E+5 1E+6 1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz) Frequency (Hz)
Figure 30. IRS2112 TJ vs. Frequency (IRFBC40) Figure 31. IRS2112 TJ vs. Frequency (IRFPE50)
RGATE = 15 Ω , VCC = 15 V RGATE = 10 Ω , VCC = 15 V
320 V 140 V
150 320 V 150
Junction Temperature (°C)

Junction Temperature (°C)

125 125

100 100
140 V

75 10 V 75
10 V

50 50

25 25

0 0
1E+2 1E+3 1E+4 1E+5 1E+6 1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz) Frequency (Hz)
Figure 32. IRS2112S TJ vs. Frequency (IRFBC20) Figure 33. IRS2112S TJ vs. Frequency (IRFBC30)
RGATE = 33 Ω , VCC = 15 V RGATE = 22 Ω , VCC = 15 V

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 IRS2112(-1,-2,S)PbF

320 V 320 V 140 V 10 V

150 150
140 V
Junction Temperature (°C)

Junction Temperature (°C)

125 10 V 125

100 100

75 75

50 50

25 25

0 0
1E+2 1E+3 1E+4 1E+5 1E+6 1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz) Frequency (Hz)
Figure 34. IRS2112S TJ vs. Frequency (IRFBC40) Figure 35. IRS2112S TJ vs. Frequency (IRFPE50)
RGATE = 15 Ω , VCC = 15 V RGATE = 10 Ω , VCC = 15 V

0.0 20.0
VS Offset Supply Voltage (V)

VSS Logic Supply Offset Voltage (V)

-3.0 16.0
Typ.

-6.0 12.0

-9.0 8.0 Typ.

-12.0 4.0

-15.0 0.0
10 12 14 16 18 20 10 12 14 16 18 20
VBS Floating Supply Voltage (V) VCC Fixed Supply Voltage (V)
Figure 36. Maximum VS Negative Offset vs. Figure 37. Maximum VSS Positive Offset vs.
VBS Supply Voltage VCC Supply Voltage

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 IRS2112(-1,-2,S)PbF

Case outline

01-6010
14-Lead PDIP 01-3002 03 (MS-001AC)

01-6010
14-Lead PDIP w/o Lead 4 01-3008 02 (MS-001AC)

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 IRS2112(-1,-2,S)PbF

16 Lead PDIP w/o Leads 4 & 5 01-6015

01-3010 02

01 6015
16-Lead SOIC (wide body) 01-3014 03 (MS-013AA)

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 IRS2112(-1,-2,S)PbF

Tape & Reel LOAD ED TA PE FEED DIRECTION

16-Lead SOIC B A
H

F C

N OT E : CO NTROLLING
D IMENSION IN MM E

C A R R I E R T A P E D IM E N S I O N F O R 1 6 S O IC W
M etr ic Im p eria l
Code M in M ax M in M ax
A 1 1 .9 0 1 2. 1 0 0. 4 6 8 0 .4 76
B 3 .9 0 4.1 0 0. 1 5 3 0 .1 61
C 1 5 .7 0 1 6. 3 0 0. 6 1 8 0 .6 41
D 7 .4 0 7.6 0 0. 2 9 1 0 .2 99
E 1 0 .8 0 1 1. 0 0 0. 4 2 5 0 .4 33
F 1 0 .6 0 1 0. 8 0 0. 4 1 7 0 .4 25
G 1 .5 0 n/ a 0. 0 5 9 n/ a
H 1 .5 0 1.6 0 0. 0 5 9 0 .0 62

B
C
A
E

R E E L D IM E N S I O N S F O R 1 6 SO IC W
M etr ic Im p eria l
Code M in M ax M in M ax
A 32 9. 60 3 30 .2 5 1 2 .9 76 1 3 .0 0 1
B 2 0 .9 5 2 1. 4 5 0. 8 2 4 0 .8 44
C 1 2 .8 0 1 3. 2 0 0. 5 0 3 0 .5 19
D 1 .9 5 2.4 5 0. 7 6 7 0 .0 96
E 9 8 .0 0 1 02 .0 0 3. 8 5 8 4 .0 15
F n /a 2 2. 4 0 n /a 0 .8 81
G 1 8 .5 0 2 1. 1 0 0. 7 2 8 0 .8 30
H 1 6 .4 0 1 8. 4 0 0. 6 4 5 0 .7 24

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 IRS2112(-1,-2,S)PbF

LEADFREE PART MARKING INFORMATION

Part number IRSxxxx

Date code YWW? IR logo

Pin 1 ?XXXX
Identifier
Lot Code
? MARKING CODE (Prod mode - 4 digit SPN code)
P Lead Free Released
Non-Lead Free
Released
Assembly site code
Per SCOP 200-002

ORDER INFORMATION
14-Lead PDIP IRS2112PbF
14-Lead PDIP IRS2112-1PbF
16-Lead PDIP IRS2112-2PbF
16-Lead SOIC IRS2112SPbF
16-Lead SOIC Tape & Reel IRS2112STRPbF

The SOIC-16 is MSL3 qualified.

This product has been designed and qualified for the industrial level.
Qualification standards can be found at www.irf.com
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 11/27/2006

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