Optimized LNA for analog RF front-end circuit in brain-machine interface
Haizheng Guo Bo Wang, Bangli Liang, Tad Kwasniewski,
Department of Electronics
Carleton University
Ottawa, ON Canada KlS 5B6
Email: hguol@doe.carleton.ca
Abstract-Advances
and low-power
in
wireless
hardware technology,
network have led to widely usage of implantable wireless
transceivers. One
and
micro-systems. These applications demand for small, low-cost,
of
the
important blocks in wireless receivers is the
amplifier (LNA). This paper presents a biasing optimized LNA
for analog front-end circuit in brain-machine interface. An
optimized biasing technique is thoroughly analyzed first in this
paper, and a LNA circuit is designed based on this technique.
Keywords-BMI; front-end circuit; implants; RFID; LNA
I. INTRODUCTION
The availability of wireless technology for diagnosis,
detection or monitoring physiological or biomedical signals
inside human bodies has been researched for a long time [ 1].
However, recently the interest in wireless systems for
medical applications has been rapidly increasing.
Applications range from monitoring high risk patients for
heart and respiratory activity, to sensing and decoding the
signals from a human brain.
Brain Machine Interface (BMI) system is one of the most
successful applications in recent research which aims to
control machines by interpreting human thoughts. A typical
BMI system may consist of brain waves scanner, capable of
detecting brain wave signals, a digital signal processor
(DSP), and a front-end circuit for communications between
the in-body devices and external machine. Usually it can be
separated into two groups: the invasive BMIs and non­
invasive BMIs.
In invasive BMI applications, the systems are implanted
directly into the grey matter of the brain. Hence, the invasive
devices could produce high quality signals, however with a
high risk of scar-tissue build-up, causing the signal to
become weaker or even lost as the body reacts to a foreign
object in the brain.
Non-invasive implant devices receive brainwaves from a
number of electrodes outside the brain. Therefore they are
easy to wear, however they produce poor signal resolution,
since the skull dampens the signals.
A typical, non-invasive Brain Machine Interface (BMI) is
shown in Fig. 1, which consists of Electroencephalography
(EEG) scanner, DSP and analog front-end circuit.
978-1-4244-5849-3/10/$26.00 ©2010 IEEE
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Robert Sobor
Department of Electronics, Department of ECE2
Carleton University, UW02
Ottawa, ON Canada KlS 5B6, London ON2
Email: {bwang.bliang.tak}@doe.carleton.ca
rsobot@uwo.ca2
wireless
most
«C9!..H�P" )('L@}�q�r
low-noise
«c �3'))((� � r::> =-
¢l ,-"Itlt r::!' :
. n.u ,
(k.. ¢:I
��
r::>:J� 1'..:::' :::
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.
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Fig. I. Simplified block diagrams of brain to machine interface (top) and
brain to brain interface (bottom).
An important part of future systems is a wireless link
between the EEG scanner and a machine. One of most
important parts of this kind of system is the low noise
amplifier. In analog circuit design, the biasing point not only
decides the circuits' operation speed, but also has a strong
effect on gain, noise figure, input matching, and efficiency.
In this work, an optimized biased LNA for analog front-end
circuit in BMI is analyzed and presented. The LNA works at
the Medical Implant Communication Service (MICS)
frequency band.
An overview of the paper follows. In Section II, the
features of CMOS technology and its impact on biasing point
of integrated circuits are reviewed. Section III presents the
structure of LNA circuit. In Section IV, the influence of the
gate overdrive biasing voltage on the performance of LNA,
such as gain, noise figure, speed and efficiency, is presented,
and the simulation results of a low power LNA are shown.
Concluding remarks and future work are in Section V.
II. ADVANCED CMOS NANOTECHNOLOGY
The design of a power-efficient LNA in CMOS IS
particularly challenging due to the following reasons:
• Trade-off between gain and bandwidth.
•Trade-off between minimal noise figure and low power
consumption.
• Linearity of the LNA is yet another important concern.
• Trade-off between large gain requirement and son
input impedance matching requirement.
147
 Recently, there are several papers published on transistor fT (Hz) vs Vgs (V) at Vds, [nfet 4,SulO.12u, n1=2, m=1]
1,40E+11
biasing for high-performance [2][3][4]. In these papers, the I I I I I I I I I I I I I I I I I I I I I I I I
+
� T""j -I-r 1111-1-1-1 T --'!' ±:J�t:=::=:::Ett
I I 1 I I I I I I I r I I I 1
gate overdrive voltage, transconductance efficiency g,rlh, 1,20E+11 f

t:
I I I I I I I I I I I
and current density are used for transistor optimal biasing, L 1 J _1_ L L LL.I-I
1,00811
I I I I I I I I
respectively. is
J. -I -I-I- I-.l- �-)"o_
"",,-=
t:
I I I I I I I I
l-

A.
..
" S,00E+10
I I I I I I I
Transition Frequency, fr a-
e I I I I I I I
... 6,00810
t:
The circuit speed is mainly depended on the transit o

frequency (fr), which can be regarded as a small-signal, high :� 4.00E+10

l!
t: 1
� + � - :- :- � -+-fT at Vds=O.3V :
1 1

frequency figure of merit for transistors. At the operating I- 2,00E+10 - ��

frequency 1= IT, a transistor is defined to have unity current 1 1 1 1 1 1 1 ___ fT at Vds=0.2V 1 1 1
LL__-=:.l-LL...LLl...Ll.-_____...u-L..LI
O,OOE+OO
gain in a common source configuration with shorted drain.
Gate to source voltage, Vgs (V)
0.200 D.400 0,600 O,SOO 1,000 1,200
Therefore,
_1 ---=g""m,----­ (a)
27r Cg, + Cgd
-
fT -

( 1) IT (Hz) vs. Jc (Alum) at V ds, [nfet 4.8uI0, 12u, nf=2, m=1]

where gm is the device's transconductance and Cgs and 1,40E+11

Cgd are its gate-source and gate-drain capacitances, N

;'1,20E+11
__ IT at Vds=1,OV

respectively. Assuming in saturation, IT is related to device I;:

....... IT at Vds=0,6V 1 1 1111

__ IT at Vds=0,3V
parameters by � 1 ,00E+ 11
§ ...... IT at Vds=0,2V
=�oc f.'", (VGS -VJ(I+A-VDs)
8,00E+10
iT �
21lC 2n:L-
". I11 1 1111
gg £ 6,00E+10 _Ll..I UWI__U1UIIlI_ L LI.1W
(2) <:
1 1 1 111111 1 1 1 111111 11111111

where f.1n is the channel mobility. The equation (2) shows

1 11111111 1 1 1 111111 1111111
,g 4,00E+10 --
'OJ
' 'l nml- -nTrTI
1 1 1 111111 I II
that the transit frequency IT is a function of override voltage � 2,00E+10 -I-I-II-I�I- -I-

� ..III�lu!!!..!...
1 11111111
and drain source voltage VDS. O,OOE+OO .!!!!I!
!L .!..!.!!.!!!!L!..!.l�:=....t...!.!
IT = I(VGS'VDS) (3)
1.00E-07 1.00E-06 1.00E-05
NFET drain current density, IdsIW, Jc (Alum)
1,00E-04 1,00E-03 1.00E-02

Fig. 2(a) shows simulation data of NMOS (0. 12f.Lm (b)

technology) transit frequency for minimum length devices
in different VDS versus gate voltage VGS, and (b) shows the
transit frequency versus density IDs!W, which is also a
function of VGsand VDS.
The Fig. 2 shows that the transition frequency IT is
dependent on the gate overdrive voltage as well as drain
source voltage VDS when in saturation region. The peak
transition frequency occurs at the edge between saturation
region and triode region. A higher transition frequency can
be gotten by choosing larger override voltage and VDS or
higher biased current density, however at the cost of the
reduction in the available signal swing.
Fig. 2 NMOS transit frequency versus (a) VGS (V) at different VDS (V); (b)
current density IDsiW.
Fig. 2 the speed in this region is the lowest due to the low
bias voltage or current.
Since there is a tradeoff between transit frequency and
transconductor efficiency, it is interesting to plot the product
of transconductor efficiency and transit frequency. To some
degree, this quantity captures the fundamental tradeoff
between speed and power and helps to identify reasonable
operating regions for analog transistors.
gm lJd (11'1) vs. Vg. (V) at Vd.
25.00

Vds=1.0V
I I I I I I I I I I I I I I I I I I I
B. Transconductor efficiency
: : : ....: : : ...-.-gm/ld at : :
The transconductor efficiency gn/ID quantifies the 4 -1-1- + -1- -r-gm/ld at Vds=O.6V I-I-

at Vds=0,3V
20.00
I I I I I I I
available device transconductance per current invested. For a __ gmlJd
at Vds=0,2V
1 1

square law transistor model, Rn/ID is given by

2
� 15.00
I I
___ gmlJd

I I I I I I I I I I
:_ �
17=&=__ !<
I I I I I I I I I I I I

ID Vov
I I I I I I I I I I I J
(4) � 10.00
I I I I I
---
IT , , ,
I
I
I
T
I I
- -
I ,
I
,
-
I I I I I
--
IT, , I
I I I I I I I I I I I I I I
I I
: : : :
.
Strong i n ve rSion
where Vov is the override voltage VGs-VTH. For very 5 00 r- t or triode region 1- r
small gate overdrive Vov « 50mV), the device enters a
1 1 1
region close to bipolar operation. For large gate overdrive, 1 1 1

velocity saturation and mobility degradation cause g,rlID to 0.200 0.400 0,600 0,800 1.000 1,200
be about 10-20% below the square law estimate. Fig. 3 Gate to source voltage, Vg. (V)
shows the transconductor efficiency of the 0. 12f.Lm
technology versus VGs• Fig. 3 NMOS transconductor efficiency versus VGS (V) at different VDS (V).
The figure shows that the MOSFET (metal-oxide­
semiconductor field-effect transistor) working in the sub­
threshold region can achieve the highest efficiency, but from

148

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 �D
(gmfl d )'fT VL VOl (V) at Vds. (nfeI4.8uJO.12u. nf:!t2.. m-1]

1i-:-:-;-iii:ii����C:::
� � : � .' � _:_ � � � -+- (gmlld)'fT a
:::::::::'�:J
1.00E+12

9.00E+11 _ _
l Vd p. 1.0

B.OOE+11
. :_ � � � -.-(gmndtfT at VdpO.6
, I -+- (gmnd)'fT al Vds=O.3
RF.
I
7.00E+11 � .. -t ___ (gmlld)'fT at Vds:=O. 2
I I ":--:-....;----:.
;.. __....� ..;. L,
J
l;;-
I::

i
6,ooE+11 _

S
5,ooE+11

4.00E+11
R"' ' ��Tr-' l "�M'
3.00E+11

2.ooE+11

c.!....:.....:.--.JL!..L2.�!...L!...!.--.J--'--!..!...J--.!..l
1,OOE+11

O,ooE+oo
0.300 0.500 0.700 0,900 1.100 j�
Gale to source voltage, VgI (V)
(a) (b)
Fig. 4 Product g,,/ID1r versus gate-source voltage VGS at different drain­ Figure 5: A narrow-band LNA topologies: (a) Common-source LNA
source voltage VDS• topology; (b) Cascaded LNA topology.

Fig. 4 shows a plot for the technologies under
consider�tion. For most technologies, the optimal biasing,
the maXImum of g,,/IDiT occurs close to a gate overdrive
voltage of around 100mV (VaS= O.SV).
In sum, the MOSFET working in the sub-threshold
region can achieve the highest efficiency, but higher biasing
current can get higher speed. As a result, for speed and
efficiency consideration, the moderate inversion region
would be the best biasing point. For high-speed purpose, part
of the efficiency can be scarified for speed. The overdrive
vo�tage of 0.3�0.4V can be selected as the optimized biasing
pomt. For larger intrinsic gain propose, the subthreshold
region is the optimized biasing point. The overdrive voltage
of 0. 1�0.2V can be selected as the optimized biasing point.
In addition, to get more intrinsic gain gmro. a larger drain
source voltage can be chosen. However it consumes larger
headroom.
III. LNA CIRCUITS
A low noise amplifier (LNA) serves as the first receiving
. tage reqUlred
. to the power consumption. It is useful to determine
gam � to sufficiently amplifY a small incoming
RF SIgnal for further signal processing. Also, it must meet
several specifications at the same time. The essential
requirement of a LNA is to amplify the signal without
adding additional amount of noise and distortion while at the
same time it should consume a minimal amount of power.
The circuit topology of an LNA is very important,
because It. determines the essential performance of the LNA,
such as the introduced noise figure, linearity, gain and power
�onsuI?ption. There are two main advantages of using
mductlve source degeneration topology in this work to
realize the input impedance matching. First, it does not
int�oduce additional noise as in the case of a shunt input
reSIstor used to match the signal source. Second, it does not
restrict the value of gm like in the case of the common-gate
configuration [5]. The proposed LNA circuit and simulated
NF are shown in the Fig. 5.
In the common-source configuration, as shown in
Fig.S(a), the signal is applied to the gate and the output is
taken from the drain. Due to the gate-to-drain parasitic
capacitance Cgd the isolation between the input and output
terminals is poor, which influences the high frequency
performance and stability of the LNA. In addition, as CMOS
technology scales, the MOSFET output resistance ro
decreases, causing reduced output impedance and lower gain
of the LNA. A possible solution is to increase the gate length
L, which then results in a degradation of noise figure NF.
To alleviate the shortcomings of the common-source
topology, the cascode topology can be used. The cascode
amplifier is a common-gate amplifier stacked on top of a
common-source amplifier, Fig. S(b).
IV. EXPERIMENTAL RESULTS
�he �hoice of biasing point for the transistors has strong
l. �ph�atlons on LNA performance such as gain, noise, and
lmeanty.
When gate length L increases, the output impedance
increases and thus improves the gain of LNA. However, a
non-minimum L is often not a good choice in designing
LNAs as it degrades the noise performance, implying a
trade-off between gain and noise performance. When gate
length L is kept to its minimum, gate-source voltage Vas and
gate width Ware key design parameters which directly link
dependence of linearity, gain and NF with respect to the Vas
and W.
According to the section II, the bias voltage Vas has two
main effects on the performance of a LNA. First, when Vas
increases, the transistor cut-off frequency iT increases.
However, if the operating frequency is sufficiently low
�ompared to the maximum iT of the technology, then
mcrease of the iT does not contribute much to the
performance of the LNA. As a result, the use of iT as a design
parameter may have less influence in the design of LNA.
Second, as the gate-source voltage VGS increases, drain
current IDS increases as well, which reduces the overall
output impedance of the cascode structure. Since the gain is
a product of the output impedance and transconductance, the
reduction of output impedance partially counteracts the
effects of increasing gml on the overall gain. Therefore, the
biasing voltage Vas could be kept relatively small to limit the
power consumption.
Noise figure (NF) is another important specification
when designing a LNA, which also dependent on Vas and W.
Depe�dence graph of NF versus operating frequency, Fig.
.
6(a), mdlcates that the gate-source voltage Vas of O . 4Vis

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 0.4V-
18 14 r-r-
----r---,---.--,
work demonstrates a competitive gam and nOlse figure
IS amongst low-power LNAs.
O.
14 O.W

COMPARISON OF CMOS LOW-POWER LNAs

O.N
12
10
TABLE!.
iii iii
:!!. :!!. - -
... ...
z
8
z Parameters This work [6] [7]
(Simulated)
.�:•.::::.:::::.:==."'"'.::.::.:.: ..
4 •••.•.•
2 .�

Gain (dB) 1 7 .3 13.6 12

420 440 420
O�---L--���-L�
360 360 400 360 360 400 440
frequency [MHz] frequency [MHz] NF (dB) :3.1 4.6 1.8
(a) (b) SII (dB) -18.7 -5 -18
Figure 6: Noise figure versus operating frequency: (a) gate-source voltage
VGS as a parameter; (b) gate width W as a parameter. IIP3 (dBm) -0.5 7.2 -3
4.8 ...,---,---,--,---,-, 18 ,-;r-----r---,--,--,---, 1dB point (clBm) -15 -0.2 -
NF - 17 e gain -
16 Pdc point (mlV) 0.565 0.26 0.9
15
� 14 fe (GHz) 0.404 1 2.4
�
�
13
.. o

z 12
11 V. CONCLUSION
10
9 The optimized biasing technique for LNA circuit design
8 �__-L__��__-LJ
is proposed in this paper. The optimized overdrive voltage of
frequency ]MHz] frequency ]MHz)
360 380 400 420 440 360 380 400 420 440

the transistor is approximately IOO-mV, which has been

(a)
Figure 7: Simulated characteristics of LNA: (a) noise figure with non-ideal
inductors (b) voltage gain with non-ideal inductors.
too small to operate well for a low noise application.
According to the Fig. 6(a), as well as DC simulation results,
when gate-source voltage VGS changes from 0.5V to 0. 7V ,
NF is reduced by 0.45dB at the expense of a 14 times
increase in the power consumption. Also, Fig. 6(b) shows
dependence graph of NF versus operating frequency as the
widths of both transistors are changed simultaneously from
40,um to 80,um (VGS O.5V). The simulation result from Fig.
=
6(b) and DC simulation results show a O.8dB NF
improvement at the expense of 2 times the power
consumption. This result suggests that given the same
current, increase of the width W can result in smaller NF than
increase of the gate-source voltage VGs. Hence, increasing
gate width W is a more effective method for reducing NF.
As a conclusion, in order to keep low power consumption
of the LNA, the bias voltage VGS should be pulled down into
the subthreshold region and wide transistor should be used to
maintain relatively small NF.
Simulation results of LNA noise figure and voltage gain,
Fig. 7(a,b) show that LNA noise figure and voltage gain with
non-ideal inductors are 17.3dB and 3.IdB respectively.
A performance comparison between the proposed LNA
designs is summarized in Table 1, with the recently
published LNA, several aspects which should be noted in
this comparison.
First, the results of this work are at circuit level. Second,
not all the LNAs compared operate at the same frequency.
Typically, more power is required to provide gain at a higher
frequency, while low quality factor on-chip inductors limited
the overall performance of LNA at lower frequency. From
the Table 1, it can be seen that the LNA designed in this
(b) concluded from analysis of the trade-off among the gain,
noise figure, speed and efficiency. LNS designed with the
proposed technique and show good performance. More
information about the systematic consideration and
experiment setup please refer to [8].
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