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Objectives
• To simulate the dynamic behavior of a CMOS inverter
• To describe the dynamic characteristics of a CMOS inverter using delay-time parameters
• To understand how the inverter delay-time parameters change as the transistor sizes
and the load properties are varied
• To be acquainted with the icon view in Electric
Introduction
The dynamic (time-domain) behavior of the inverter provides an indication of its switching
characteristics. The switching speed of logic gates is among the most important
specifications that must be taken into account by any IC designer because it determines the
overall transient performance of digital systems.
Procedure
1. Load Electric.
3. Create new facet inverter_sch with schematic as the facet view. Make sure that the
library indicated is Exercise.
4. Draw the schematic shown in Figure 2-a. Make sure that the current technology is
schematic, analog.
6. Create an icon for the inverter_sch{sch}. Follow the instructions in the Schematic
section of the Training Manual. Save the icon facet. Close the inverter_sch{ic} and
the inverter_sch{sch} design windows.
7. Create new facet inverter_sch_tst with schematic as the facet view. Make sure that
the library indicated is Exercise.
8. Create the inverter instance by clicking on Edit → New Facet Instance. Choose library
Exercise. Select inverter_sch{ic} from this library. Press OK. Click on the design
window.
9. Export all the pins by clicking on Export → Re-Export Everything. Add other
necessary components for simulation. Please refer to Figure 2-b.
Figure 2-b. Schematic diagram for the transient analysis of a CMOS inverter.
10. For the analysis, choose Transient Analysis from the Spice list instead of a DC
Analysis. Specify the required SPICE card by following the instructions given in the
Schematic section of the Training Manual.
Note: SPICE card for transient analysis→ 5p 500n 0 5p
13. Complete the table below by varying the width of the PMOS transistor. Round off your
answers to two decimal places.
Note: To view and edit the inverter schematic while in the inverter_sch_tst schematic, select the inverter
icon instance in the design window and press Ctrl-D. To go back to the inverter_sch_tst schematic window,
simply press Ctrl-U.
14. Repeat the above procedures for loadcap = 500fF. Complete the table below. Round
off your answers to two decimal places.
Delay-Time Definitions
VIN Idealized
step input
VOH
V50%
VOL
t
VOH
V50%
VOL
t
t 0 t1 t 2 t3
V10%
t
tA tB t C tD
τPHL (High-to-low propagation delay time): The time delay between the V50%-transition of the rising
input voltage and the V50%-transition of the falling input voltage.
τPLH (Low-to-high propagation delay time): The time delay between the V50%-transition of the falling
input voltage and the V50%-transition of the rising input voltage.
τfall (Output voltage fall time): The time required for the output voltage to drop from the
V90% level to V10% level.
τrise (Output voltage rise time): The time required for the output voltage to rise from the
V10% level to V90% level.
τP (Average propagation delay): The average time required for the input signal to propagate
through the inverter.
V50% = ½ (VOL + VOH)
V10% = VOL + 0.1(VOH - VOL)
V90% = VOL + 0.9(VOH - VOL)
τP = ½ (τPHL + τPLH)
Open your *.cir file in WinSpice. The corresponding graph appears. Determine the
name of the vectors from the graph.
Example: Input voltage is vector v(Vin) and output voltage is vector v(Vout).