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RC CIRCUITS 7. Calculate the phase angle in the given 12. What is the total current in the given
circuit. circuit?
1. In a 20 Vac series RC circuit, if 20 V is
read across the resistor and 40 V is
measured across the capacitor, the
applied voltage is
A. 45 Vac
B. 50 Vac A. 0° A. 0.28 A
C. 60 Vac B. 90° B. 0.399 A
D. 65 Vac C. 22.52° C. 909 A
D. 67.48° D. 0.2 A
2.Which of the following is the reference
vector for parallel RC circuits? 8. What is the phase angle for a parallel 13. Which statement about a series RC
A. R circuit consisting of a 500 kHz, 5 Vac circuit is true?
B. V source with a 47 pF capacitor, and a 4.7 A. The capacitor's voltage drop is
C. I kΩ resistor in parallel? in phase with the resistor's
D. XC A. 55.3° voltage drop.
B. –55.3° B. The current leads the source
3. What is the voltage drop across R1 in
C. 34.8° voltage.
the given circuit?
D. –34.8° C. The current lags the source
voltage.
9.
D. The resistor voltage lags the
current.
14. If the frequency increases in the
A. 10 V given circuit, how would the total
B. 4.80 V current change?
C. 4.00 V
D. 5.80 V
Which circuit is represented by the
4. Power that is measured in volt- frequency response curve in the given
amperes is called figure?
A. impedance power A. High-pass filter A. The total current would
B. reactive power B. Low-pass filter increase.
C. true power C. Band-pass filter B. The total current would
D. apparent power D. Band-stop filter decrease.
C. The total current would remain
5. As frequency increases 10. What is the phase angle in the given the same.
A. both series and parallel RC circuit? D. More information is needed in
impedance decrease
order to predict how the total
B. series RC impedance decreases
current would change.
and parallel RC impedance
increases 15. What is the effect of increasing the
C. series RC impedance increases resistance in a series RC circuit?
and parallel RC impedance A. 14.95° A. There will be no effect at all.
decreases B. 36.88° B. The current will increase.
D. both series and parallel RC C. 0° C. The phase shift will decrease.
impedance increase D. 90° D. The input voltage will increase.
6. Calculate the magnitude of the 11. What is the current through XC1 in
impedance in the given circuit. the given circuit?
RL CIRCUITS
1. As frequency increases
A. both series and parallel RL
impedance decrease
A. 24.1 MΩ A. 32.2 mA B. series RL impedance decreases
B. 10 MΩ B. 16 mA and parallel RL impedance
C. 26.1 MΩ C. 12 ma increases
D. 0Ω D. 48 mA
τµΩ INDIABIX ELECTRONICS PART 2
C. series RL impedance increases 7. What is the magnitude of the phase A. An increase in frequency
and parallel RL impedance angle of a 24 Vac parallel RL circuit when causes an increase in phase
decreases R = 45 Ω and XL = 1100 Ω? lag.
D. both series and parallel RL A. 0.001° B. An increase in frequency causes
impedance increase B. 2.3° an increase in the magnitude of
C. 87.6° the output voltage.
2. Calculate the voltage dropped across
D. 89.9° C. A decrease in frequency causes
R1 in the given circuit.
an increase in phase lag.
8. Which of the following statements is
D. A decrease in frequency causes
true if the frequency decreases in the
a decrease in the magnitude of
circuit in the given circuit?
the output voltage.
A. 14 V TRANSFORMERS
B. 26.8 V
C. 28 V 1. When does maximum power transfer
D. 0V A. The phase angle decreases.
happen from the source to the load?
B. VR decreases.
3. What is the true power of a 24 Vac A. When the source resistance is
C. IT decreases.
parallel RL circuit when R = 45 Ω and XL greater than the load resistance
D. VS decreases.
= 1100 Ω? B. When the source resistance is
A. 313.45 W 9. What is the magnitude of the phase less than the load resistance
B. 12.8 W angle between the source voltage and C. When there is negligible source
C. 44.96 W current when a 100 mH inductor with an resistance
D. 22.3 W inductive reactance of 6 kΩ and a 1 kΩ D. When the source resistance
resistor are in series with a source? equals the load resistance
4. If XL= 100 Ωand R = 100Ω, then A. 0.1°
impedance will be 2. A transformer is plugged into a 120 V
B. 9.0°
A. 141.4 Ω rms source and has a primary current of
C. 61.0°
B. 14.14 Ω 300 mA rms. The secondary is providing
D. 81.0°
C. 100 Ω 18 V across a 10 Ω load. What is the
D. 200 Ω 10. Which of the following statements is efficiency of the transformer?
true if R1 opens in the circuit in the given A. 88%
5. Which of the following statements is circuit? B. 90%
true if the inductor shorts out in the C. 92%
circuit in the given circuit? D. 95%
3. The coefficient of coupling between
two coils is 0.45. The first coil has an
inductance of 75 mH and the second coil
A. IL2 increases. has an inductance of 105 mH. What is
B. ZT decreases. the mutual inductance between the
A. Each component drops 5 V. C. VS increases. coils?
B. The impedance equals 0 Ω. D. VL1 equals 0 V. A. 3.54 mH
C. The power factor equals 1.
11. Which of the following statements is B. 7.88 mH
D. The phase angle equals 90°.
true if R = 100 Ω and XL = 100 Ωin the C. 39.9 mH
6. Calculate the voltage dropped across circuit in the given circuit? D. 189.3 mH
L2 in the given circuit.
4. Increasing the number of turns of wire
on the secondary of a transformer will
A. increase the secondary current
B. decrease the secondary
current
A. Each component drops 5 V. C. have no effect on the secondary
A. 18 V B. The impedance equals 200 Ω. current
B. 6V C. The power factor equals 1. D. increase the primary current
C. 13.5 V D. The phase angle equals 45°.
5. What is the turns ratio of the
D. 0V
12. Which of the following statements is transformer needed to match a 1 kΩ
true about a lag network? source resistance to a 160 Ω load?
τµΩ INDIABIX ELECTRONICS PART 2
A. 2.5:1 11. A special transformer used to convert B. 4.3 V
B. 0.4:1 unbalanced signals to balanced signals is C. 4.75 V
C. 6.25:1 the D. 4.9 V
D. 16:1 A. balun 2. If a periodic pulse waveform is applied
B. autotransformer to an RC differentiating circuit, which
6. What is the secondary voltage in the
C. center-tapped transformer two conditions are possible?
given circuit?
D. step-across transformer A. tw ≥ 5τ or tw > 5τ
B. tw = 5τ or tw > 5τ
12. If the load doubled in value in the
C. tw ≤ 5τ or tw < 5τ
given circuit, what reflected resistance
D. tw ≥ 5τ or tw < 5τ
would the source see?
A. 13.3 V rms in phase with the 3. An RL integrator and an RC
primary differentiator can act as what types of
B. 120 V rms in phase with the filters, respectively?
primary A. low-pass, low-pass
C. 13.3 V rms out of phase with B. low-pass, high-pass
A. 80 Ω
the primary C. high-pass, high-pass
B. 400 Ω
D. 120 V rms out of phase with the D. high-pass, low-pass
C. 2 kΩ
primary D. 10 kΩ 4. In a repetitive-pulse RC integrator
7. The transformer turns ratio circuit, what would the steady-state
13. If the primary power of an ideal
determines voltage equal at the end of the fifth
transformer having a 2:1 voltage ratio is
A. the ratio of primary and pulse? Assume a Vin of 20 V.
100 W, the secondary power is
secondary voltages A. 1.46 V
A. 100 W
B. the ratio of primary and B. 14.62 V
B. 50 W
secondary currents C. 20 V
C. 75 W
C. the reflected impedance D. 0V
D. 200 W
D. all of the above 5. What is a circuit that produces short-
14. A transformer has
8. Mutual induction is dependent on duration spikes?
A. primary and secondary
A. winding ratios A. A trigger pulse generator
windings, both of which are
B. output polarities B. An RL integrator
considered inputs
C. dc voltage levels C. A timing circuit
B. primary and secondary
D. current changes D. A pulse waveform-to-dc
windings, both of which are
converter
9. What is the current through the load considered outputs
in the given circuit? C. a primary winding used as an
output and a secondary winding
used as an input
D. a primary winding used as an
input and a secondary winding
A. 500 µA used as an output 6.
B. 10 mA In the given circuit, what must the pulse
C. 250 mA width and time between pulses be to
D. 1.25 A TIME RESPONSE OF allow the capacitor to completely charge
REACTIVE CIRCUITS by the end of each pulse and to
10. What is the power dissipated in the completely discharge between each
primary of the transformer in the given 1. pulse?
circuit? A. 940 µs
B. 2.82 ms
C. 3.76 ms
D. 4.7 ms
A. 25 mW
B. 500 mW
C. 12.5 W
What voltage will the capacitor charge
D. 62.5 W
up to in the given circuit for the single
input pulse shown?
A. 3.15 V 7.
τµΩ INDIABIX ELECTRONICS PART 2
The given circuit is an What is the voltage across the inductor
A. RL integrator in the given circuit on the falling edge of
A.
B. RC differentiator the first input pulse?
B. Av = IC × RC
C. RL differentiator A. –0.2 V
D. RC integrator B. 0.2 V
C. –9.8 V C.
8. Which of the following is true for a
D. 9.8 V
capacitor?
A. A capacitor acts like a short to D.
instantaneous changes in 7. In a class B push-pull amplifier, the
current. TRANSISTORS AND transistors are biased slightly above
B. A capacitor's voltage cannot APPLICATIONS cutoff to avoid
change instantaneously. A. crossover distortion
C. A capacitor acts like an open to 1. The primary function of the bias circuit B. unusually high efficiency
dc. is to C. negative feedback
D. All of the above A. hold the circuit stable at VCC D. a low input impedance
9. If the capacitor in an RC integrator B. hold the circuit stable at vin
8. The depletion-mode MOSFET
shorts, the output C. ensure proper gain is achieved
A. can operate with only positive
A. is at ground D. hold the circuit stable at the
gate voltages
B. would measure the same as the designed Q-point
B. can operate with only negative
input 2. A JFET gate voltages
C. would measure zero volts A. is a current-controlled device C. cannot operate in the ohmic
D. None of the above B. has a low input resistance region
10. C. is a voltage-controlled device D. can operate with positive as
D. is always forward-biased well as negative gate voltages
3. A source follower has a voltage gain 9. Three different points are
(Av) of shown on a dc load line. The upper point
A. AV = gmRd represents the
B. AV = gmRs A. minimum current gain
B. quiescent point
What has the voltage across the resistor C. saturation point
C. D. cutoff point
decayed to by the end of the pulse in the
given circuit?
10. Which of the following conditions are
A. 0V
D. needed to properly bias an npn
B. 0.75 V
transistor amplifier?
C. 5.55 V 4. The capacitor that produces an ac
A. Forward bias the base/emitter
D. 14.25 V ground is called a(n)
junction and reverse bias the
A. coupling capacitor
11. How long will it take the capacitor in base/collector junction.
B. dc open
the given circuit to discharge? B. Forward bias the collector/base
C. bypass capacitor
junction and reverse bias the
D. ac open
emitter/base junction.
5. The formula used to calculate the C. Apply a positive voltage on the
approximate ac resistance of the base- n-type material and a negative
emitter diode (re) is voltage on the p-type material.
D. Apply a large voltage on the
A. 16.4 µs base.
B. 32.8 µs A.
C. 65.6 µs B. re almostequal.jpg 25 mV × IC 11. Often a common-collector will be the
D. 82 µs last stage before the load; the main
function of this stage is to
12. C. A. provide voltage gain
B. buffer the voltage amplifiers
from the low-resistance load
D. C. provide phase inversion
6. The signal voltage gain of an D. provide a high-frequency path
amplifier, Av, is defined as: to improve the frequency
response
τµΩ INDIABIX ELECTRONICS PART 2
B. the inverted sum of the 13. A two-pole high-pass active filter
12. In order for feedback oscillators to
individual inputs would have a roll-off rate of
have any practical value, the gain has to
C. the sum of the individual inputs A. 40 dB/decade
be
D. the inverted average of the B. –40 dB/decade
A. <1
individual inputs C. 20 dB/decade
B. self-adjusting
D. –20 dB/decade
C. stabilized 6. If the input to a comparator is a sine
D. nonlinear wave, the output is a
A. ramp voltage
13. To get a negative gate-source SPECIAL PURPOSE OP-
B. sine wave
voltage in a self-biased JFET circuit, you
must use a
C. rectangular wave AMP CIRCUITS
D. sawtooth wave
A. voltage divider
B. source resistor 7. A basic series regulator has
C. ground A. an error detector
D. negative gate supply voltage B. a load
C. a reference voltage
D. both an error detector and a 1.
BASIC OP-AMP CIRCUITS reference voltage
8. A comparator is an example of a(n)
1. The center frequency of a band-pass
A. active filter
filter is always equal to the
B. current source
A. bandwidth
C. linear circuit
B. –3 dB frequency
D. nonlinear circuit
C. bandwidth divided by Q
D. geometric average of the
9. Initially, the closed-loop gain (Acl) of a
critical frequencies
Wien-bridge oscillator should be
A. Acl < 3 Which circuit is known as a current-to-
B. Acl > 3 voltage converter?
2. The formula shows that
C. 0 A. a
for a given capacitor, if the voltage
changes at a constant rate with respect D. Acl 1 B. b
to time, the current will 10. In an averaging amplifier, the input C. c
A. increase resistances are D. d
B. decrease A. equal to the feedback 2. When using an OTA in a Schmitt-
C. be constant resistance trigger configuration, the trigger points
D. decrease logarithmically B. less than the feedback are controlled by
3. A zero-level detector is a resistance A. the Iout
A. comparator with a sine-wave C. greater than the feedback B. the Ibias
output resistance C. the Vout
B. comparator with a trip point D. unequal D. both Iout and Ibias
referenced to zero 11. A triangular-wave oscillator can
C. peak detector consist of an op-amp comparator,
D. limiter followed by a(n)
4. A digital-to-analog converter is an A. differentiator
application of the B. amplifier 3.
A. scaling adder C. integrator
B. voltage-to-current converter D. multivibrator
C. noninverting amplifier 12. The ramp voltage at the output
D. adjustable bandwidth circuit of an op-amp integrator
5. If the value of resistor Rf in an A. increases or decreases at a
averaging amplifier circuit is equal to the linear rate
value of one input resistor divided by the B. increases or decreases
number of inputs, the output will be exponentially
equal to C. is always increasing and never
A. the average of the individual decreasing
D. is constant Refer the given circuits. Which circuit is
inputs known as an OTA?
τµΩ INDIABIX ELECTRONICS PART 2
A. a 8. An instrumentation amplifier has a 2. Which of the following characterizes
B. b high an analog quantity?
C. c A. output impedance A. Discrete levels represent
D. d B. power gain changes in a quantity.
C. CMRR B. Its values follow a logarithmic
4. This circuit is a setup for
D. supply voltage response curve.
C. It can be described with a finite
9. This circuit is a setup for
number of steps.
D. It has a continuous set of
values over a given range.
3. ASCII stands for:
A. an antilog amplifier A. American Serial
B. a constant-current source Communication Interface
C. an instrumentation amplifier B. Additive Signal Coupling
D. an isolation amplifier Interface
C. American Standard Code for
A. an antilog amplifier Information Interchange
B. a constant-current source D. none of the above
C. an instrumentation amplifier
D. an isolation amplifier 4. Which type of signal is represented by
discrete values?
5. 10. Circuits that shift the dc level of a A. noisy signal
signal are called B. nonlinear
A. limiters C. analog
B. clampers D. digital
C. peak detectors
D. dc converters 5. A data conversion system may be
used to interface a digital computer
11. The voltage gain of an OTA can be system to:
calculated using the formula A. an analog output device
B. a digital output device
A. C. an analog input device
Which circuit is known as a voltage-to- D. a digital printer
B.
current converter?
A. a
B. b C. NUMBER SYSTEMS AND
C. c CODES
D. d D.
6. The primary function of the oscillator 12. In the classic three-op-amp 1. Base 10 refers to which number
in an isolation amplifier is to instrumentation amplifier, the system?
A. convert dc to high-frequency differential voltage gain is usually A. binary coded decimal
ac produced by the B. decimal
B. convert dc to low-frequency ac A. first stage C. octal
C. rectify high-frequency ac to dc B. second stage D. hexadecimal
D. produce dual-polarity dc C. mismatched resistors 2. Convert the decimal number 151.75 to
voltages for the input to the D. output op-amp binary.
demodulator
A. 10000111.11
7. Refer to Figure 20-2. This circuit is a B. 11010011.01
setup for
ANALOG TO DIGITAL C. 00111100.00
D. 10010111.11
1. The two basic types of signals are
analog and: 3. Convert the binary number 1011010 to
A. digilog hexadecimal.
B. digital A. 5B
A. an antilog amplifier
C. vetilog B. 5F
B. a constant-current source
D. sine wave C. 5A
C. an instrumentation amplifier
D. 5C
D. an isolation amplifier
τµΩ INDIABIX ELECTRONICS PART 2
4. The number of bits used to store a B. 00110101 6. Exclusive-OR (XOR) logic gates can be
BCD digit is: C. 00110010 constructed from what other logic
A. 8 D. 00110001 gates?
B. 4 A. OR gates only
12. 3428 is the decimal value for which of
C. 1 B. AND gates and NOT gates
the following binary coded decimal
D. 2 C. AND gates, OR gates, and
(BCD) groupings?
NOT gates
5. Sample-and-hold circuits in ADCs are A. 11010001001000
D. OR gates and NOT gates
designed to: B. 11010000101000
A. sample and hold the output of C. 011010010000010 7. How many truth table entries are
the binary counter during the D. 110100001101010 necessary for a four-input circuit?
conversion process A. 4
13. What is the result when a decimal
B. stabilize the ADCs threshold B. 8
5238 is converted to base 16?
voltage during the conversion C. 12
A. 327.375
process D. 16
B. 12166
C. stabilize the input analog
C. 1388 8. A NAND gate has:
signal during the conversion
D. 1476 A. LOW inputs and a LOW output
process
B. HIGH inputs and a HIGH output
D. sample and hold the ADC
C. LOW inputs and a HIGH
staircase waveform during the LOGIC GATES output
conversion process
D. None of these
6. The weight of the LSB as a binary 1. The output will be a LOW for any case
when one or more inputs are zero in 9. The basic logic gate whose output is
number is:
a(n): the complement of the input is the:
A. 1
A. OR gate A. OR gate
B. 2
B. NOT gate B. AND gate
C. 3
C. AND gate C. INVERTER gate
D. 4
D. NAND gate D. comparator
7. What is the difference between binary
2. If a signal passing through a gate is 10. What input values will cause an AND
coding and binary coded decimal?
inhibited by sending a low into one of logic gate to produce a HIGH output?
A. Binary coding is pure binary.
the inputs, and the output is HIGH, the A. At least one input is HIGH.
B. BCD is pure binary.
gate is a(n): B. At least one input is LOW.
C. Binary coding has a decimal
A. AND C. All inputs are HIGH.
format.
B. NAND D. All inputs are LOW.
D. BCD has no decimal format.
C. NOR
8. Convert the binary number 1001.0010 D. OR
to decimal. LOGIC CIRCUIT
A. 125 3. A single transistor can be used to build SIMPLIFICATION
B. 12.5 which of the following digital logic
C. 90.125 gates? 1. Which statement below best describes
D. 9.125 A. AND gates a Karnaugh map?
B. OR gates A. It is simply a rearranged truth
9. Convert 110010012 (binary) to C. NOT gates
decimal. table.
D. NAND gates B. The Karnaugh map eliminates
A. 201
B. 2001 4. The logic gate that will have HIGH or the need for using NAND and
C. 20 "1" at its output when any one of its NOR gates.
D. 210 inputs is HIGH is a(n): C. Variable complements can be
A. OR gate eliminated by using Karnaugh
10. What is the decimal value of the B. AND gate maps.
hexadecimal number 777? C. NOR gate D. A Karnaugh map can be used to
A. 191 D. NOT gate replace Boolean rules.
B. 1911
C. 19 5. How many NAND circuits are 2. Which of the examples below
D. 19111 contained in a 7400 NAND IC? expresses the commutative law of
A. 1 multiplication?
11. What is the resultant binary of the B. 2 A. A+B=B+A
decimal problem 49 + 1 =? C. 4 B. A•B=B+A
A. 01010101 D. 8 C. A • (B • C) = (A • B) • C
τµΩ INDIABIX ELECTRONICS PART 2
D. A•B=B•A means that logically there is no A. 0.0 V to 0.4 V
3.The Boolean expression is difference between: B. 0.4 V to 0.8 V
logically equivalent to what single gate? A. a NAND gate and an AND gate C. 0.4 V to 1.8 V
A. NAND with a bubbled output D. 0.4 V to 2.4 V
B. NOR B. a NOR gate and an AND gate
4. When an IC has two rows of parallel
C. AND with a bubbled output
connecting pins, the device is referred to
D. OR C. a NOR gate and a NAND gate
as:
with a bubbled output
4. The observation that a bubbled input A. a QFP
D. a NAND gate and an OR gate
OR gate is interchangeable with a B. a DIP
with a bubbled output
bubbled output AND gate is referred to C. a phase splitter
as: 10. The commutative law of addition and D. CMOS
A. a Karnaugh map multiplication indicates that:
5. Which digital IC package type makes
B. DeMorgan's second theorem A. the way we OR or AND two
the most efficient use of printed circuit
C. the commutative law of variables is unimportant
board space?
addition because the result is the same
A. SMT
D. the associative law of B. we can group variables in an
B. TO can
multiplication AND or in an OR any way we
C. flat pack
want
5. The systematic reduction of logic D. DIP
C. an expression can be expanded
circuits is accomplished by: by multiplying term by term 6. The problem of interfacing IC logic
A. symbolic reduction just the same as in ordinary families that have different supply
B. TTL logic algebra voltages (VCCs) can be solved by using
C. using Boolean algebra D. the factoring of Boolean a:
D. using a truth table expressions requires the A. level-shifter
6. Logically, the output of a NOR gate multiplication of product terms B. tri-state shifter
would have the same Boolean that contain like variables C. translator
expression as a(n): D. level-shifter or translator
11. Which of the following expressions is
A. NAND gate immediately in the sum-of-products (SOP) form? 7. Ten TTL loads per TTL driver is known
followed by an INVERTER A. Y = (A + B)(C + D) as:
B. OR gate immediately followed B. Y = AB(CD) A. noise immunity
by an INVERTER B. power dissipation
C. AND gate immediately C. C. fanout
followed by an INVERTER D. propagation delay
D. NOR gate immediately D.
followed by an INVERTER 8. Which of the following summarizes
STANDARD LOGIC the important features of emitter-
7. Which of the examples below coupled logic (ECL)?
expresses the distributive law of Boolean
DEVICES (SLD) A. negative voltage operation,
algebra? high speed, and high power
A. A • (B • C) = (A • B) + C 1. A digital logic device used as a buffer consumption
B. A + (B + C) = (A • B) + (A • C) should have what input/output B. good noise immunity, negative
C. A • (B + C) = (A • B) + (A • C) characteristics? logic, high frequency capability,
D. (A + B) + C = A + (B + C) A. high input impedance and high low power dissipation, and
output impedance short propagation time
8. Which output expression might B. low input impedance and high C. slow propagation time, high
indicate a product-of-sums circuit output impedance frequency response, low power
construction? C. low input impedance and low consumption, and high output
output impedance voltage swings
A. D. high input impedance and low D. poor noise immunity, positive
output impedance supply voltage operation, good
B.
2. What is the standard TTL noise low-frequency operation, and
C. margin? low power
A. 5.0 V 9. What quantities must be compatible
D.
B. 0.2 V when interfacing two different logic
9. One of DeMorgan's theorems states C. 0.8 V families?
that . Simply stated, this D. 0.4 V A. only the currents
3. The range of a valid LOW input is:
τµΩ INDIABIX ELECTRONICS PART 2
B. both the voltages and the A. it cannot be reprogrammed. 3. A logic probe is placed on the output
currents B. its outputs are only active of a gate and the display indicator is dim.
C. only the voltages HIGHs A logic pulser is used on each of the
D. both the power dissipation and C. its outputs are only active input terminals, but the output
the impedance LOWs indication does not change. What is
D. its logic capacity is lost wrong?
10. CMOS logic is probably the best all-
A. The dim indication on the logic
around circuitry because of its: 4. The complex programmable logic
probe indicates that the supply
A. packing density device (CPLD) contains several PLD
voltage is probably low.
B. low power consumption blocks and:
B. The output of the gate
C. very high noise immunity A. field-programmable switches
appears to be open.
D. low power consumption and B. AND/OR arrays
C. The LOW indication is the result
very high noise immunity C. a global interconnection
of a bad ground connection on
matrix
11. Low power consumption achieved by the logic probe.
D. a language compiler
CMOS circuits is due to which D. The gate is a tri-state device.
construction characteristic? 5. PLAs, CPLDs, and FPGAs are all which
4. A +5 V PCB power source that has
A. complementary pairs type of device?
been "pulled down" to a +3.4 V level may
B. connecting pads A. SLD
be due to:
C. DIP packages B. PLD
A. a circuit open
D. small-scale integration C. EPROM
B. a faulty regulator
D. SRAM
12. A TTL totem pole circuit is designed C. the half-split method
so that the output transistors are: 6. The difference between a PLA and a D. a circuit short
A. always on together PAL is:
5. Measurement of pulse width should
B. providing phase splitting A. the PLA has a programmable
be taken at a 50% mean of the:
C. providing voltage regulation OR plane and a programmable
A. overshoot and undershoot
D. never on together AND plane, while the PAL
B. rise and fall
only has a programmable
13. The time needed for an output to C. damping and ringing
AND plane
change as the result of an input change D. leading and trailing amplitude
B. the PAL has a programmable
is known as:
OR plane and a programmable 6. Which test equipment best allows a
A. noise immunity
AND plane, while the PLA only comparison between input and output
B. fanout
has a programmable AND plane signals?
C. propagation delay
C. the PAL has more possible A. an oscilloscope
D. rise time
product terms than the PLA B. a logic probe
D. PALs and PLAs are the same C. a spectrum analyzer
thing. D. a multitrace oscilloscope
PROGRAMMABLE LOGIC
7. The duty cycle of a pulse is
DEVICES (PLD) determined by which formula?
TESTING AND
1. Which type of PLD should be used to TROUBLESHOOTING A. Duty Cycle =
program basic logic functions?
A. PLA 1. A series of gradually decreasing sine B. Duty Cycle =
B. PAL wave oscillations is called:
C. CPLD A. ringing C. Duty Cycle =
D. SLD B. slew
D. Duty Cycle =
C. overshooting
2. The content of a simple
D. undershooting 8. What is the next step after discovering
programmable logic device (PLD)
a faulty gate within an IC?
consists of: 2. The determination of a digital signal's
A. repair the gate
A. fuse-link arrays frequency and waveshape is best
B. resolder the tracks
B. thousands of basic logic gates accomplished with which test
C. replace the IC involved
C. advanced sequential logic equipment?
D. recheck the power source
functions A. an oscilloscope
D. thousands of basic logic gates B. a multimeter 9. The use of a multimeter with digital
and advanced sequential logic C. a spectrum analyzer circuits allows the measurement of:
functions D. a frequency generator A. pulse width
3. Once a PAL has been programmed:
τµΩ INDIABIX ELECTRONICS PART 2
B. voltage or resistance that occur during the 11. A basic multiplexer principle can be
C. current transmission of codes from one demonstrated through the use of a:
D. pulse trains location to another. A. single-pole relay
10. The use of triggered sweep when C. Parity checking is not suitable B. DPDT switch
using an oscilloscope provides more for detecting single-bit errors in C. rotary switch
accuracy in which area? transmitted codes. D. linear stepper
A. frequency D. Parity checking is capable of
12. In a BCD-to-seven-segment
B. amplitude detecting and correcting errors
converter, why must a code converter be
C. graticule activity in transmitted codes.
utilized?
D. timing
5. A multiplexed display: A. No conversion is necessary.
11. The time needed for a pulse to A. accepts data inputs from one B. to convert the 4-bit BCD into
increase from 10% to 90% of its line and passes this data to gray code
amplitude defines: multiple output lines C. to convert the 4-bit BCD into
A. pulse width B. uses one display to present 10-bit code
B. propagation delay two or more pieces of D. to convert the 4-bit BCD into
C. rise time information 7-bit code
D. duty cycle C. accepts data inputs from
multiple lines and passes this
12. Which device would best aid in FLIP FLOPS AND TIMERS
data to multiple output lines
shorted track detection?
D. accepts data inputs from
A. multimeter
several lines and multiplexes 1. Which of the following is correct for a
B. current tracer
this input data to four BCD lines gated D-type flip-flop?
C. logic pulser
D. oscilloscope 6. When two or more inputs are active A. The Q output is either SET or
simultaneously, the process is called: RESET as soon as the D input
A. first-in, first-out processing goes HIGH or LOW.
COMBINATIONAL LOGIC B. priority encoding B. The output complement follows
the input when enabled.
CIRCUITS C. ripple blanking
D. priority decoding C. Only one of the inputs can be
HIGH at a time.
1. How many inputs are required for a 1- 7. Which type of decoder will select one D. The output toggles if one of the
of-10 BCD decoder? of sixteen outputs, depending on the 4- inputs is held HIGH.
A. 4 bit binary input value?
B. 8 A. hexadecimal 2. When both inputs of a J-K flip-flop
C. 10 B. dual octal outputs cycle, the output will:
D. 1 C. binary-to-hexadecimal A. be invalid
D. hexadecimal-to-binary B. not change
2. Most demultiplexers facilitate which
C. change
of the following? 8. A magnitude comparator determines: D. toggle
A. decimal to hexadecimal A. A ≠ B and if A α B or A >> B
B. single input, multiple outputs B. A ≈ B and if A > B or A < b 3. Latches constructed with NOR and
C. ac to dc C. A = B and if A > B or A < b NAND gates tend to remain in the
D. odd parity to even parity D. A B and if A < b or a > B latched condition due to which
configuration feature?
3. One application of a digital 9. A circuit that responds to a specific set A. asynchronous operation
multiplexer is to facilitate: of signals to produce a related digital B. low input voltages
A. code conversion signal output is called a(n): C. gate impedance
B. parity checking A. BCD matrix D. cross coupling
C. parallel-to-serial data B. display driver
conversion C. encoder 4. The 555 timer can be used in which of
D. data generation D. decoder the following configurations?
A. astable, monostable
4. Select one of the following 10. Which digital system translates B. monostable, bistable
statements that best describes the coded characters into a more intelligible C. astable, toggled
parity method of error detection: form? D. bistable, tristable
A. Parity checking is best suited A. encoder
for detecting single-bit errors B. display 5. A basic S-R flip-flop can be
in transmitted codes. C. counter constructed by cross-coupling which
B. Parity checking is best suited D. decoder basic logic gates?
for detecting double-bit errors A. AND or OR gates
τµΩ INDIABIX ELECTRONICS PART 2
B. XOR or XNOR gates A. There is no known significance A. PIPO
C. NOR or NAND gates in their designations. B. SISO
D. AND or NOR gates B. The J represents "jump," which C. SIPO
is how the Q output reacts D. PISO
6. One example of the use of an S-R flip- whenever the clock goes HIGH
4. Synchronous counters eliminate the
flop is as a(n): and the J input is also HIGH.
delay problems encountered with
A. transition pulse generator C. The letters represent the initials
asynchronous (ripple) counters because
B. astable oscillator of Johnson and King, the co-
the:
C. racer inventors of the J-K flip-flop.
A. input clock pulses are applied
D. switch debouncer D. All of the other letters of the
only to the first and last
alphabet are already in use.
7. If both inputs of an S-R NAND latch stages
are LOW, what will happen to the 13. Which of the following describes the B. input clock pulses are applied
output? operation of a positive edge-triggered only to the last stage
A. The output would become D-type flip-flop? C. input clock pulses are not used
unpredictable. A. If both inputs are HIGH, the to activate any of the
B. The output will toggle. output will toggle. counter stages
C. The output will reset. B. The output will follow the D. input clock pulses are
D. No change will occur in the input on the leading edge of applied simultaneously to
output. the clock. each stage
C. When both inputs are LOW, an
8. The equation for the output frequency 5. One of the major drawbacks to the
invalid state exists.
of a 555 timer operating in the astable use of asynchronous counters is that:
D. The input is toggled into the
A. low-frequency applications
flip-flop on the leading edge of
mode is: are limited because of
the clock and is passed to the
What value of C1 will be required if R1 = 1 internal propagation delays
output on the trailing edge of
kΩ , R2 = 1 kΩ, and f = 1 kHz? B. high-frequency applications
the clock.
A. 0.33 µF are limited because of
B. 0.48 µF 14. What is one disadvantage of an S-R internal propagation delays
C. 480 µF flip-flop? C. Asynchronous counters do
D. 33 nF A. It has no Enable input. not have major
B. It has a RACE condition. drawbacks and are
9. An astable multivibrator is a circuit
C. It has no clock input. suitable for use in high- and
that:
D. It has only a single output. low-frequency counting
A. has two stable states
applications.
B. is free-running
D. Asynchronous counters do
C. produces a continuous output SEQUENTIAL LOGIC not have propagation
signal
D. is free-running and produces a CIRCUITS delays, which limits their use
in high- frequency
continuous output signal
applications.
10. What is another name for a one- 1. A ripple counter's speed is limited by
the propagation delay of: 6. Which type of device may be used to
shot?
A. each flip-flop interface a parallel data format with
A. monostable
B. all flip-flops and gates external equipment's serial format?
B. bistable
C. the flip-flops only with gates A. key matrix
C. astable
D. only circuit gates B. UART
D. tristable
C. memory chip
11. The truth table for an S-R flip-flop 2. To operate correctly, starting a ring D. serial-in, parallel-out
has how many VALID entries? counter requires:
A. clearing all the flip-flops 7. When the output of a tri-state shift
A. 3
B. presetting one flip-flop and register is disabled, the output level is
B. 1
clearing all the others placed in a:
C. 4
C. clearing one flip-flop and A. float state
D. 2
presetting all the others B. LOW state
12. What is the significance of the J and D. presetting all the flip-flops C. high impedance state
K terminals on the J-K flip-flop? D. float state and a high
3. What type of register would shift a impedance state
complete binary number in one bit at a
time and shift all the stored bits out one 8. A comparison between ring and
bit at a time? johnson counters indicates that:
τµΩ INDIABIX ELECTRONICS PART 2
A. a ring counter has fewer flip- OPERATIONS AND 8. Use the two's complement system to
flops but requires more add the signed numbers 11110010 and
decoding circuitry CIRCUITS 11110011. Determine, in decimal, the
B. a ring counter has an inverted sign and value of each number and their
feedback path 1. When 1100010 is divided by 0101, sum.
C. a johnson counter has more what will be the decimal remainder? A. –14 and –13; –27
flip-flops but less decoding A. 2 B. –113 and –114; 227
circuitry B. 3 C. –27 and –13; 40
D. a johnson counter has an C. 4 D. –11 and –16; –27
inverted feedback path D. 6
9. The selector inputs to an arithmetic-
9. A sequence of equally spaced timing 2. What are the two types of basic adder logic unit (ALU) determine the:
pulses may be easily generated by which circuits? A. selection of the IC
type of counter circuit? A. half adder and full adder B. arithmetic or logic function
A. shift register sequencer B. half adder and parallel adder C. data word selection
B. clock C. asynchronous and D. clock frequency to be used
C. johnson synchronous
D. one's complement and two's 10. Adding in binary, the decimal values
D. binary
complement 26 + 27 will produce a sum of:
10. What is meant by parallel-loading A. 111010
the register? 3. Adding the two's complement of –11 B. 110110
A. Shifting the data in all flip- + (–2) will yield which two's complement C. 110101
flops simultaneously answer? D. 101011
B. Loading data in two of the A. 1110 1101
B. 1111 1001 11. Binary subtraction of a decimal 15
flip-flops from 43 will utilize which two's
C. Loading data in all four flip- C. 1111 0011
D. 1110 1001 complement?
flops at the same time A. 101011
D. Momentarily disabling the 4. The two's complement system is to B. 110000
synchronous SET and RESET be used to add the signed numbers C. 011100
inputs 11110010 and 11110011. Determine, in D. 110001
11. What is a shift register that will decimal, the sign and value of each
number and their sum. 12. When multiplying in binary the
accept a parallel input and can shift data decimal values 13 × 11, what is the third
left or right called? A. –14 and –13; –27
B. –113 and –114; 227 partial product?
A. tri-state A. 100000
B. end around C. –27 and –13; 40
D. –11 and –16; –27 B. 100001
C. bidirectional universal C. 0000
D. conversion 5. The fast carry or look-ahead carry D. 1011
12. What happens to the parallel output circuits found in most 4-bit parallel-
adder circuits: 13. The range of an 8-bit two's
word in an asynchronous binary down complement word is from:
counter whenever a clock pulse occurs? A. increase ripple delay
B. add a 1 to complemented A. +12810 to –12810
A. The output word decreases B. –12810 to +12710
by 1. inputs
C. reduce propagation delay C. +12810 to –12710
B. The output word decreases by D. +12710 to –12710
2. D. determine sign and magnitude
C. The output word increases by 6. How many basic binary subtraction
1. operations are possible? SEMICONDUCTOR
D. The output word increases by A. 4 MEMORY
2. B. 3
13. Mod-6 and mod-12 counters are C. 2
1. A computerized self-diagnostic for a
most commonly used in: D. 1
ROM test uses:
A. frequency counters 7. How many basic binary subtraction A. the check-sum method
B. multiplexed displays combinations are possible? B. a ROM listing
C. digital clocks A. 4 C. ROM comparisons
D. power consumption B. 3 D. a checkerboard test
C. 2 2. How many storage locations are
ARITHMETIC D. 1 available when a memory device has
twelve address lines?
τµΩ INDIABIX ELECTRONICS PART 2
A. 144 D. the EEPROM can erase and A. reduced memory access time
B. 512 reprogram individual words B. reduced requirement for
C. 2048 without removal from the constant refreshing of the
D. 4096 circuit memory contents
C. reduced pin count and
3. Which of the following memories uses 8. Which of the following RAM timing
decrease in package size
a MOSFET and a capacitor as its parameters determine(s) its operating
D. no requirement for a chip-
memory cell? speed?
select input line, thereby
A. SRAM A. tacc
reducing the pin count
B. DRAM B. taa and tacs
C. ROM C. t1 and t3
D. DROM D. trc and twc ANALOG AND DIGITAL
4. Which of the following best describes 9. Memory that loses its contents when CONVERTERS
nonvolatile memory? power is lost is:
A. memory that retains stored A. nonvolatile
information when electrical B. volatile 1. Which of the following is a type of
power is removed C. random error associated with digital-to-analog
B. memory that loses stored D. static converters (DACs)?
information when electrical A. nonmonotonic error
10. Select the best description of the B. incorrect output codes
power is removed
fusible-link PROM. C. offset error
C. magnetic memory
A. user programmable, one- D. nonmonotonic and offset
D. nonmagnetic memory
time programmable error
5. The access time (tacc) of a memory IC B. manufacturer programmable,
is governed by the IC's: one-time programmable 2. A 4-bit R/2R digital-to-analog (DAC)
A. internal address buffer C. user programmable, converter has a reference of 5 volts.
B. internal address decoder reprogrammable What is the analog output for the input
C. volatility D. manufacturer programmable, code 0101.
D. internal address decoder and reprogrammable A. 0.3125 V
volatility B. 3.125 V
11. A nonvolatile type of memory that C. 0.78125 V
6. Select the best description of read- can be programmed and erased in D. –3.125 V
only memory (ROM). sectors, rather than one byte at a time is:
A. nonvolatile, used to store A. flash memory 3. A binary-weighted digital-to-analog
information that changes B. EPROM converter has an input resistor of 100
during system operation C. EEPROM . If the resistor is connected to a 5 V
B. nonvolatile, used to store D. MPROM source, the current through the resistor
information that does not is:
12. Which of the following best
change during system A. 50 A
describes static memory devices?
operation B. 5 mA
A. memory devices that are
C. volatile, used to store C. 500 A
magnetic in nature and do not
information that changes D. 50 mA
require constant refreshing
during system operation
B. semiconductor memory 4. What is the resolution of a digital-to-
D. volatile, used to store
devices in which stored data analog converter (DAC)?
information that does not
is retained as long as power A. It is the comparison between
change during system
is applied the actual output of the
operation
C. memory devices that are converter and its expected
7. Advantage(s) of an EEPROM over an magnetic in nature and output.
EPROM is (are): require constant refreshing B. It is the deviation between the
A. the EPROM can be erased D. semiconductor memory ideal straight-line output and
with ultraviolet light in much devices in which stored data the actual output of the
less time than an EEPROM will not be retained with the converter.
B. the EEPROM can be erased power applied unless C. It is the smallest analog
and reprogrammed without constantly refreshed output change that can occur
removal from the circuit as a result of an increment in
13. What is the principal advantage of
C. the EEPROM has the ability to the digital input.
using address multiplexing with DRAM
erase and reprogram D. It is its ability to resolve
memory?
individual words between forward and reverse
τµΩ INDIABIX ELECTRONICS PART 2
steps when sequenced over its 10. The resolution of a 0–5 V 6-bit mnemonic codes are in
entire range. digital-to-analog converter (DAC) is: shorthand English.
A. 63% C. Machine codes are in
5. The practical use of binary-weighted
B. 64% shorthand English, mnemonic
digital-to-analog converters is limited
C. 1.56% codes are in binary.
to:
D. 15.6% D. Machine codes are in
A. R/2R ladder D/A converters
shorthand English, mnemonic
B. 4-bit D/A converters 11. In a flash analog-to-digital converter,
codes are a high-level
C. 8-bit D/A converters the output of each comparator is
language.
D. op-amp comparators educing connected to an input of a:
the pin count A. decoder 3. Which bus is bidirectional?
B. priority encoder A. data bus
6. The difference between analog
C. multiplexer B. control bus
voltage represented by two adjacent
D. demultiplexer C. address bus
digital codes, or the analog step size, is
D. multiplexed bus
the: 12. Which is not an analog-to-digital
A. quantization (ADC) conversion error? 4. The software used to drive
B. accuracy A. differential nonlinearity microprocessor-based systems is called:
C. resolution B. missing code A. assembly language
D. monotonicity C. incorrect code programs
D. offset B. firmware
7. The primary disadvantage of the flash
C. BASIC interpreter instructions
analog-to digital converter (ADC) is that: 13. Sample-and-hold circuits in analog-
D. flowchart instructions
A. it requires the input voltage to to digital converters (ADCs) are
be applied to the inputs designed to: 5. A microprocessor unit, a memory
simultaneously A. sample and hold the output of unit, and an input/output unit form a:
B. a long conversion time is the binary counter during the A. CPU
required conversion process B. compiler
C. a large number of output lines B. stabilize the comparator's C. microcomputer
is required to simultaneously threshold voltage during the D. ALU
decode the input voltage conversion process
6. How many buses are connected as
D. a large number of C. stabilize the input analog
part of the 8085 microprocessor?
comparators is required to signal during the conversion
A. 2
represent a reasonable process
B. 3
sized binary number D. sample and hold the D/A
C. 5
converter staircase waveform
8. A binary-weighted digital-to-analog D. 8
during the conversion process
converter has a feedback resistor, Rf, of
12 k . If 50 A of current is through 7. Which of the following is not a
the resistor, the voltage out of the circuit computer bus?
is:
COMPUTER HARDWARE A. data bus
A. 0.6 V AND SOFTWARE B. timer bus
B. –0.6 V C. control bus
C. 0.1 V D. address bus
1. When referring to instruction words, a
D. –0.1 V mnemonic is: 8. The technique of assigning a memory
9. What is the major advantage of the A. a short abbreviation for the address to each I/O device in the SAM
R/2R ladder digital-to-analog (DAC), as operand address system is called:
compared to a binary-weighted digital- B. a short abbreviation for the A. wired I/O
to-analog DAC converter? operation to be performed B. I/O mapping
A. It only uses two different C. a short abbreviation for the C. dedicated I/O
resistor values. data word stored at the D. memory-mapped I/O
B. It has fewer parts for the same operand address
9. How many bits are used in the data
number of inputs. D. shorthand for machine
bus?
C. Its operation is much easier to language
A. 7
analyze. 2. What is the difference between B. 8
D. The virtual ground is mnemonic codes and machine codes? C. 9
eliminated and the circuit is A. There is no difference. D. 16
therefore easier to understand B. Machine codes are in binary,
and troubleshoot. 10. A port can be:
τµΩ INDIABIX ELECTRONICS PART 2
A. strictly for input 4. The generic array logic (GAL) device is B. several digital signals are sent
B. strictly for output ________. on each conductor.
C. bidirectional A. one-time programmable C. both binary and hexadecimal
D. all the above B. reprogrammable can be used.
C. a CMOS device D. no clock is needed.
11. Which of the following is not a basic
D. reprogrammable and a CMOS
element within the microprocessor? 12. A decoder converts ________.
device
A. microcontroller A. noncoded information into
B. arithmetic-logic unit (ALU) 5. The range of voltages between VL(max) coded form
C. temporary register and VH(min) are ________. B. coded information into
D. accumulator A. unknown noncoded form
B. unnecessary C. HIGHs to LOWs
12. How many bits are used in the
C. unacceptable D. LOWs to HIGHs
address bus?
D. between 2 V and 5 V
A. 7 13. A DAC changes ________.
B. 8 6. What is a digital-to-analog converter? A. an analog signal into digital
C. 9 A. It takes the digital data
D. 16 information from an B. digital data into an analog
audio CD and converts it to signal
13. Exceptions to the 8085
a usable form. C. digital data into an amplified
microprocessor normal operation are
B. It allows the use of cheaper signal
called:
analog techniques, which are D. none of the above
A. jump instructions
always simpler.
B. decoding 14. The output of a NOT gate is HIGH
C. It stores digital data on a hard
C. interrupts when ________.
drive.
D. jump instructions or A. the input is LOW
D. It converts direct current to
interrupts B. the input is HIGH
alternating current.
C. the input changes from LOW to
7. What are the symbols used to
HIGH
DIGITAL CONCEPTS represent digits in the binary number
D. voltage is removed from the
system?
gate
A. 0,1
1. Any number with an exponent of zero B. 0,1,2 15. The output of an OR gate is LOW
is equal to: C. 0 through 8 when ________.
A. zero D. 1,2
B. one A. all inputs are LOW
C. that number 8. A full subtracter circuit requires____.
B. any input is LOW
D. ten A. two inputs and two outputs
C. any input is HIGH
B. two inputs and three outputs
2. In the decimal numbering system, D. all inputs are HIGH
C. three inputs and one output
what is the MSD? D. three inputs and two 16. Which of the following is not an
A. The middle digit of a stream of outputs analog device?
numbers A. Thermocouple
B. The digit to the right of the 9. The output of an AND gate is LOW
B. Current flow in a circuit
decimal point _____.
C. Light switch
C. The last digit on the right A. all the time
D. Audio microphone
D. The digit with the most B. when any input is LOW
weight C. when any input is HIGH 17. A demultiplexer has ________.
D. when all inputs are HIGH A. one data input and a number
3. Which of the following statements of selection inputs, and they
does NOT describe an advantage of 10. Give the decimal value of binary
have several outputs
digital technology? 10010.
B. one input and one output
A. The values may vary over a A. 610
C. several inputs and several
continuous range. B. 910
outputs
B. The circuits are less affected C. 1810
D. several inputs and one output
by noise. D. 2010
C. The operation can be 18. A flip-flop has ________.
11. Parallel format means that:
programmed. A. one stable state
A. each digital signal has its
D. Information storage is easy. B. no stable states
own conductor.
C. two stable states
D. none of the above
τµΩ INDIABIX ELECTRONICS PART 2
receiver as there are data C. It allows the use of digital
19. Digital signals transmitted on a
bits. signals in everyday life.
single conductor (and a ground) must be
D. is less expensive than the serial D. It stores information on a CD.
transmitted in:
method of data transmission.
A. slow speed. 33. A multiplexer has ________.
B. parallel. 26. Convert the fractional decimal A. one input and several outputs
C. analog. number 6.75 to binary.O B. one input and one output
D. serial. A. 0111.1100 C. several inputs and several
B. 0110.1010 outputs
20. In a certain digital waveform, the
C. 0110.1100 D. several inputs and one
period is four times the pulse width. The
D. 0110.0110 output
duty cycle is ________.
3
A. 0% 27. What is one relative disadvantage of 34. What is the decimal value of 2 ?
B. 25% serial transfer? A. 2
C. 50% A. It requires too many B. 4
D. 100% conductors. C. 6
B. Its interconnect system is D. 8
21. In positive logic, ________.
complex.
A. a HIGH = 1, a LOW = 0 35. An encoder converts ________.
C. It is slow.
B. a LOW = 1, a HIGH = 0 A. noncoded information into
D. It can only be used over very
C. only HIGHs are present coded form
short distances.
D. only LOWs are present B. coded information into
28. Which format requires fewer noncoded form
22. Convert the fractional binary number
conductors? C. HIGHs to LOWs
0000.1010 to decimal.
A. Parallel D. LOWs to HIGHs
A. 0.625
B. Serial
B. 0.50 36. What kind of logic device or circuit is
C. Both are the same
C. 0.55 used to store information?
D. Cannot tell
D. 0.10 A. Counter
B. Register
23. Digital representations of numerical 29. A pulse has a period of 15 ms. Its
C. Inverter
values of quantities may BEST be frequency is ________.
D. Buffer
described as having characteristics: A. 6.66 Hz
A. that are difficult to interpret B. 66.66 Hz 37. PLCC packages have leads on ____.
because they are continuously C. 666.66 Hz A. one side
changing. D. 15 Hz B. two sides
B. that vary constantly over a C. three sides
30. Give the decimal value of binary
continuous range of values. D. four sides
10000110.
C. that vary in constant and direct
A. 13410 38. What is the typical invalid voltage for
proportion to the
B. 14410 a binary signal?
values they represent.
C. 11010 A. 0.7–2.8 volts
D. that vary in discrete steps in
D. 12610 B. 0.8–3 volts
proportion to the values they
C. 0.8–2 volts
represent. 31. The rise time is the time it takes a
D. 0.7–2.5 volts
pulse to go from ________.
24. A common instrument used in
A. the base line to the maximum 39. Convert the fractional binary number
troubleshooting a digital circuit is a(n)
HIGH voltage 0001.0010 to decimal.
_____.
B. 10% of the pulse amplitude to A. 1.40
A. logic probe
the maximum HIGH voltage B. 1.125
B. oscilloscope
C. the base line to 90% of the C. 1.20
C. pulser
pulse amplitude D. 1.80
D. all of the above
D. 10% of the pulse amplitude
40. Convert the fractional binary number
25. The parallel transmission of digital to 90% of the pulse
10010.0100 to decimal.
data: amplitude
A. 24.50
A. is much slower than the serial
32. What is an analog-to-digital B. 18.25
transmission of data.
converter? C. 18.40
B. requires only one signal line
A. It makes digital signals. D. 16.25
between sender and receiver.
B. It takes analog signals and
C. requires as many signal lines 41. How many binary bits are necessary
puts them in digital format.
between sender and to represent 748 different numbers?
τµΩ INDIABIX ELECTRONICS PART 2
A. 9 49. A type of digital circuit technology transmission of codes from one
B. 7 that uses bipolar junction transistors is location to another.
C. 10 ________. B. Parity checking is not suitable
D. 8 A. TTL for detecting single-bit errors in
B. CMOS transmitted codes.
42. A periodic digital waveform has a
C. LSI C. Parity checking is best suited
pulse width (tw) of 6 ms and a period (T)
D. NMOS for detecting single-bit errors
of 18 ms. The duty cycle is ______.
in transmitted codes.
A. 3.3% 50. How many unique symbols are used
D. Parity checking is capable of
B. 33.3% in the decimal number system?
detecting and correcting errors
C. 6% A. One
in transmitted codes.
D. 18% B. Nine
C. Ten 2. A logic circuit that provides a HIGH
43. Any number with an exponent of one
D. Unlimited output for both inputs HIGH or both
is equal to:
inputs LOW is a(n):
A. zero. 51. A classification of ICs with
A. Ex-NOR gate
B. one. complexities of 12 to 100 equivalent
B. OR gate
C. two. gates on a chip is known as ________.
C. Ex-OR gate
D. that number. A. SSI
D. NAND gate
B. MSI
44. Serial format means digital signals
C. LSI 3. A logic circuit that provides a HIGH
are:
D. VLSI output if one input or the other input,
A. sent over many conductors
but not both, is HIGH, is a(n):
simultaneously. 52. Which of the following is a
A. Ex-NOR gate
B. sent over one conductor semiconductor memory?
B. OR gate
sequentially. A. RAM
C. Ex-OR gate
C. sent in groups of eight signals. B. MAR
D. NAND gate
D. sent in binary coded decimal. C. CD-ROM
–1 D. CD 4. Identify the type of gate below from
45. What is the decimal value of 2 ?
A. 0.5 53. The holes through a PC board are the equation
B. 0.25 ________. A. Ex-NOR gate
C. 0.05 A. smaller with SMT than with B. OR gate
D. 0.1 through-hole mounting C. Ex-OR gate
B. larger with SMT than with D. NAND gate
46. Which format can send several bits
through-hole mounting 5. How is odd parity generated
of information faster?
C. the same size as with differently from even parity?
A. Parallel
through-hole mounting A. The first output is inverted.
B. Serial
D. usually unnecessary B. The last output is inverted.
C. Both are the same
D. Cannot tell 54. A classification of ICs with 6. Parity systems are defined as
complexities of 100 to 10,000 equivalent either________ or ________ and will add
47. The frequency of a pulse train is 2
gates per chip is known as ______. an extra ________ to the digital
kHz. The pulse period is ________.
A. SSI information being transmitted.
A. 5 ms
B. MSI A. positive, negative, byte
B. 50 ms
C. LSI B. odd, even, bit
C. 500 s
D. VLSI C. upper, lower, digit
D. 2 s
D. on, off, decimal
48. What has happened to the advances
in digital technologies over the past EX-OR AND EX-NOR 7. Which type of gate can be used to add
three decades? two bits?
GATES A. Ex-OR
A. Slowed down considerably
B. Continued to increase, but at a B. Ex-NOR
decreasing rate 1. Select the statement that best C. Ex-NAND
C. Made excellent progress describes the parity method of error D. NOR
D. Nothing short of detection: 8. Why is an exclusive-NOR gate also
phenomenal A. Parity checking is best suited called an equality gate?
for detecting double-bit errors A. The output is false if the inputs
that occur during the are equal.
τµΩ INDIABIX ELECTRONICS PART 2
B. The output is true if the inputs B. OR operation. C. c
are opposite. C. NOT operation. D. d
C. The output is true if the inputs D. AND operation.
8. In VHDL, the mode of a port does not
are equal.
4. For a three-input OR gate, with the define:
9. Show from the truth table how an input waveforms as shown below, which A. an input.
exclusive-OR gate can be used to invert output waveform is correct? B. an output.
the data on one input if the other input is C. both an input and an output.
a special control function. D. the TYPE of the bit.
A. Using A as the control, when A
9. Which of the following equations
= 0, X is the same as B. When A
would accurately describe a 4-input OR
= 1, X is the same as B.
gate when A = 1, B = 1, C = 0, and D = 0?
B. Using A as the control, when A
A. 1+1+0+0=1
= 0, X is the same as B. When
A. a B. 1 + 1 + 0 + 0 = 01
A = 1, X is the inverse of B.
B. b C. 1+1+0+0=0
C. Using A as the control, when A
C. c D. 1 + 1 + 0 + 0 = 00
= 0, X is the inverse of B. When
A = 1, X is the same as B. D. d 10. Which of the examples below
D. Using A as the control, when A 5. Which of the figures given expresses the distributive law?
= 0, X is the inverse of B. When below represents a NOR gate? A. (A + B) + C = A + (B + C)
A = 1, X is the inverse of B. B. A(B + C) = AB + AC
C. A + (B + C) = AB + AC
10. Determine odd parity for each of the
D. A(BC) = (AB) + C
following data words:
A. a
1011101 11110111 1001101 11. Which of the examples below
B. b
A. P = 1, P = 1, P = 0 expresses the associative law of
C. c
B. P = 0, P = 0, P = 0 addition:
D. d
C. P = 1, P = 1, P = 1 A. A + (B + C) = (A + B) + C
D. P = 0, P = 0, P = 1 6. Which of the figures (a to d) is the B. A + (B + C) = A + (BC)
DeMorgan equivalent of Figure (e)? C. A(BC) = (AB) + C
11. The Ex-NOR is sometimes
D. ABC = A + B + C
called the ________.
A. parity gate 12. How are the statements between
B. equality gate A. a BEGIN and END not evaluated in VHDL?
C. inverted OR B. b A. Constantly
D. parity gate or the equality gate C. c B. Simultaneously
D. d C. Concurrently
D. Sequentially
7. Which of the figures in figure (a to d) is
DESCRIBING LOGIC equivalent to figure (e)? 13. Which logic gate does this truth table
CIRCUITS describe?
BOOLEAN AND LOGIC 6. One of De Morgan's theorems states 13. A truth table for the SOP expression
has how many input
SIMPLIFICATION that . Simply stated, this
combinations?
means that logically there is no
difference between: A. 1
A. a NOR and an AND gate with B. 2
1. Convert the following SOP expression
inverted inputs C. 4
to an equivalent POS expression.
B. a NAND and an OR gate with D. 8
39. Applying DeMorgan's theorem to the 45. The commutative law of addition
expression , we get and multiplication indicates that:
________. A. we can group variables in an
AND or in an OR any way we
A. want
B. B. an expression can be
expanded by multiplying term
C. by term just the same as in
D. ordinary algebra
C. the way we OR or AND two
40. Which of the following is an variables is unimportant
important feature of the sum-of- because the result is the same
products (SOP) form of expression? D. the factoring of Boolean
A. All logic circuits are reduced expressions requires the
to nothing more than multiplication of product
simple AND and OR terms that contain like
gates. variables
B. The delay times are greatly
reduced over other forms. 46. Which of the following combinations
C. No signal must pass through cannot be combined into K-map groups?
more than two gates, not A. corners in the same row
A. (A) including inverters. B. corners in the same column
B. (B) D. The maximum number of gates C. diagonal
C. (C) that any signal must pass D. overlapping combinations
D. (D) through is reduced by a factor
36. Which statement below best of two.
COMBINATIONAL LOGIC
describes a Karnaugh map? 41. An OR gate with schematic "bubbles"
A. A Karnaugh map can be used on its inputs performs the same
ANALYSIS
to replace Boolean rules. functions as a(n)________ gate.
B. The Karnaugh map eliminates A. NOR 1. Referring to the GAL diagram, which
the need for using NAND and B. OR is the correct logic function?
NOR gates. C. NOT
C. Variable complements can be D. NAND
eliminated by using Karnaugh 42. Which of the examples below
maps. expresses the commutative law of
D. Karnaugh maps provide a multiplication?
cookbook approach to A. A+B=B+A
τµΩ INDIABIX ELECTRONICS PART 2
D. None of these