ARTICLE IN PRESS

INTEGRATION, the VLSI journal 42 (2009) 137– 148

Contents lists available at ScienceDirect

INTEGRATION, the VLSI journal

journal homepage: www.elsevier.com/locate/vlsi

Analog circuit optimization system based on hybrid evolutionary algorithms

Bo Liu a, Yan Wang a,, Zhiping Yu a, Leibo Liu a, Miao Li a, Zheng Wang a,
Jing Lu a, Francisco V. Fernández b
a
Institute of Microelectronics, Tsinghua University, China
b
IMSE, CSIC and University of Seville, Spain

a r t i c l e in fo abstract

Article history: This paper investigates a hybrid evolutionary-based design system for automated sizing of analog
Received 29 July 2007 integrated circuits (ICs). A new algorithm, called competitive co-evolutionary differential evolution
Received in revised form (CODE), is proposed to design analog ICs with practical user-defined specifications. On the basis of the
28 January 2008
combination of HSPICE and MATLAB, the system links circuit performances, evaluated through electrical
Accepted 10 April 2008
simulation, to the optimization system in the MATLAB environment, once a circuit topology is selected.
The system has been tested by typical and hard-to-design cases, such as complex analog blocks with
Keywords: stringent design requirements. The results show that the design specifications are closely met, even in
Analog circuit synthesis
highly-constrained situations. Comparisons with available methods like genetic algorithms and
Analog circuit optimization
differential evolution, which use static penalty functions to handle design constraints, have also been
Differential evolution (DE)
Co-evolutionary differential evolution carried out, showing that the proposed algorithm offers important advantages in terms of optimization
(CODE) quality and robustness. Moreover, the algorithm is shown to be efficient.
Analog circuit sizing & 2008 Elsevier B.V. All rights reserved.

1. Introduction optimum results are significant objectives of the proposed system.

Nowadays, VLSI technology progresses towards the integration
of mixed analog–digital circuits as a complete system-on-a-chip.
Though the analog part is a small fraction of the entire circuit, it is
much more difficult to design due to the complex and knowledge-
intensive nature of analog circuits. Without an automated
synthesis methodology, analog circuit design suffers from long
design time, high complexity, high cost and requires highly
skilled designers. Consequently, automated synthesis methodol-
ogies for analog circuits have received much attention. The analog
design procedure consists of topological-level design and para-
meter-level design (also called circuit sizing) [1,2]. This paper
concentrates on the latter, aiming at parameter selection and
optimization to improve the performances for a given circuit
topology.
There are two main purposes of a synthesis system: first,
replace tedious and ad-hoc manual trade-offs by automatic design
of parameters; second, solve problems that are hard to design by
hand. Accuracy, ease of use, generality, robustness, and reasonable
run-time are necessary for a circuit synthesis solution to gain
acceptance [3]. Other than those requirements, ability to deal with
large-scale problems, closely meet the designer’s requirements,
even for highly-constrained problems, and ability to achieve
Many parameter-level design strategies, methods, and tools have
been published in recent years [1–23], and some have even
reached commercialization [24].
Most analog circuit sizing problems can be naturally expressed
as the minimization of an objective1 (e.g., power consumption),
usually subject to some constraints (e.g., DC gain larger than a
certain value). They can be formulated as follows:
min f ðxÞ
x
gðxÞX0
subject to hðxÞ ¼ 0
X L oxoX H (1)
In this equation, the objective function f(x) is the performance
function to be minimized and h(x) are the equality constraints. In
analog circuit design, the equality constraints mainly refer to
Kirchhoff’s current law (KCL) and Kirchhoff’s voltage law (KVL)
equations. Vector x corresponds to the design variables, and XL
and XH are their lower and upper bounds, respectively. The vector
g(x)X0 corresponds to user-defined constraints.
The proposed system uses the formulation of the analog circuit
design problem in Eq. (1) as a constrained optimization problem
and, then, solves it by evolutionary algorithms. A new algorithm,

 Corresponding author. 1
The maximization of a design objective can easily be transformed into a
E-mail address: wangy46@tsinghua.edu.cn (Y. Wang). minimization problem by just inverting its sign.

0167-9260/$ - see front matter & 2008 Elsevier B.V. All rights reserved.
doi:10.1016/j.vlsi.2008.04.003
 ARTICLE IN PRESS
138 B. Liu et al. / INTEGRATION, the VLSI journal 42 (2009) 137–148
called competitive co-evolutionary differential evolution (CODE)
algorithm, is proposed to deal with this constrained opti-
mization problem. The algorithm has several novel features,
which enable it to deal with large-scale and highly-con-
strained problems in an acceptable computation time with high
robustness.
The evolutionary algorithm has been implemented in MATLAB
[25]. Evaluation of the objective function and constraints (values
of f(x) and g(x) in Eq. (1)) is performed by using an electrical
simulator, HSPICE [26], for which an appropriate link with
MATLAB has been implemented.
The structure of the paper is as follows. Section 2 reviews
related work and motivates the strategy of our optimization
approach. The evolutionary algorithm used in this approach,
differential evolution, and its implementation, are discussed in
Section 3. Section 4 formulates the competitive co-evolution
approach to handle constraints in the differential evolution
algorithm. Section 5 provides practical examples and benchmark
tests to show the efficiency, effectiveness and advantages
of the proposed approach. Comparisons with other common
methods are also carried out. Finally, some concluding remarks
are given.
2. Related work
Synthesis can be carried out by the following two different
approaches: knowledge- and optimization-based. The basic
idea of knowledge-based synthesis is to formulate design
equations in such a way that given the performance character-
istics, the design parameters can be calculated [4–6]. In these
tools, the quality of the solutions in terms of both accuracy and
robustness is not acceptable since the very concept of knowledge-
based sizing forces the design equations to be simple. Other
drawbacks are the large preparatory time/effort required to
develop design plans or equations, the difficulty in using them
in a different technology, and the limitation to a fixed set of
circuits.
In optimization-based synthesis, the problem is translated into
function minimization problems that can be solved through
numerical methods. Essentially, they are based on the introduc-
tion of a performance evaluator within an iterative optimization
loop. The system is called equation-based when the performance
evaluator is based on equations capturing the behavior of a circuit
topology [7–11]. However, creating the equations often consumes
much more time than manually designing the circuit. In addition,
the simplifications required in the closed form analytical
equations cause low accuracy and incompleteness. On the
contrary, simulation-based methods do not rely on analytical
equations but on SPICE-like simulations to evaluate the circuit
performances in the optimization process, which result in super-
ior accuracy, generality, and ease of use [12–15]. Therefore, our
system is simulation-based. Through the link between HSPICE and
MATLAB, the candidate parameters are transmitted from the
optimization system to the simulation engine, and the circuit
performances obtained by the electrical simulator are returned to
the optimization system. The penalty to pay is a relatively long
computation time (compared to other methods), although, as the
experimental results in Section 5 demonstrate, it can be kept
within acceptable limits.
Techniques for analog circuit optimization that appeared in
literature can be broadly classified into two main categories:
deterministic optimization algorithms and stochastic search
algorithms (evolutionary computation algorithms, simulated
annealing, etc.). The traditional deterministic optimization meth-
ods mainly include steepest-descent algorithm and downhill
algorithm. These techniques are available in some commercial
electrical simulators [26]. The drawbacks of deterministic opti-
mization algorithms are mainly in the following three aspects: (1)
they require a good starting point, (2) an unsatisfactory local
minimum may be reached in many cases, and (3) they often
require continuity and differentiability of the objective function.
Some researchers have tried to address these difficulties, such as
in Ref. [16], where a method to determine the initial point is
presented. Another approach is the application of geometric
programming methods, which guarantee the convergence to a
global minimum [11]. However, they require a special formulation
of design equations, which make them share many of the
disadvantages of equation-based systems. Research efforts on
stochastic search algorithms, especially evolutionary computation
(EC) algorithms (genetic algorithms, differential evolution, genetic
programming, etc.) have begun to appear in literature in recent
years [1,17–23]. Due to the ability and efficiency to find a
satisfactory solution, genetic algorithms (GA) have been employed
as optimization routines for analog circuits in both, industry
and academia. For problems with practical design specifications,
most reported approaches use the penalty function method to
handle constraints. Though these works have made a significant
progress, the optimization algorithms for analog circuit design
automation remain an active research area because of the
following reasons:
(1) GA is the most popular evolutionary algorithm, but its search
ability and convergence rate have been criticized. It has also
been proved that canonical GA cannot converge to the global
optimum [27]. GA with elitism converges to the global
optimum theoretically, but it is not always the case in
practice. On the other hand, some other population-based
metaheuristics (PBMH) methods, such as swarm intelligence
[28] and differential evolution [29] are attracting much
attention in the community of operations research because
of their advantages over GAs. Their potentials in analog circuit
design automation still need to be exploited.
(2) The constraint handling problem is very important in analog
circuit design, especially for high performance circuits, which
are always highly constrained. Most reported synthesis
methods use penalty functions to handle constraints, and
few of them investigated solution algorithms for high
performance design problems. In these methods, the con-
strained optimization problem is transformed into an un-
constrained one by minimizing the following function:
0
X
n
f ðxÞ ¼ f ðxÞ þ wi hg i ðxÞi, (2)
i¼1
where the parameters wi are the penalty coefficients and
/gi(x)S returns the absolute value of gi(x) if it is negative, and
zero otherwise. The results of the methods based on penalty
functions are very sensitive to the penalty coefficients, and
may not meet the designer’s specifications in many cases.
Small values of penalty coefficients drive the search outside
the feasible region and often produce infeasible solutions,
while imposing very severe penalties make it difficult to drive
the population to the optimum solution. Usually, exact
solutions are hard to find without tuning the penalty
coefficients for many times. Although several penalty strate-
gies have been developed [30,31], there has been no general
rule for designing penalty coefficients till now.
(3) Ability to handle large-scale design problems is still under
investigation. Most of the available methods can deal with
about 10–20 variables simultaneously, but analog circuits
with 30 or more unknown variables are common.

B. Liu et al. / INTEGRATION, the VLSI journal 42 (2009) 137–148
3. Differential evolution and its implementation
The differential evolution (DE) algorithm and its implementa-
tion are introduced briefly in this section. The DE algorithm is
suitable for unconstrained problems, and it is also a basic
component in CODE.
Differential evolution is a population-based evolutionary
computation technique, which uses a simple differential operator
to create new candidate solutions, and a one-to-one competition
scheme to greedily select new candidates. Recently, DE has
attracted much attention in various technical fields [32,33].
The flow diagram of the DE algorithm is summarized in Fig. 1. The
DE algorithm starts with the random initialization of a population of
individuals in the search space and works on the cooperative
behaviors of the individuals in the population. At each generation,
the mutation and crossover operators are applied to the individuals,
and a new population arises. Then, selection takes place, and the
corresponding individuals from both populations compete to build
the next generation. The algorithm tries to find the globally optimal
solution by utilizing the distribution of solutions in the search space
and differences between pairs of solutions as search directions.
However, the searching behavior of each individual in the search
space is adjusted by dynamically altering the direction and step
length in which the search is performed.
The ith individual in the d-dimensional search space at
generation t can be represented as
XðtÞ ¼ ½xi;1 ; xi;2 ; . . . ; xi;d ; i ¼ 1; 2; . . . ; NP,
where NP denotes the size of the population.
For each target individual i, according to the mutation operator,
a mutant vector:
V i ðt þ 1Þ ¼ ½vi;1 ðt þ 1Þ; . . . ; vi;d ðt þ 1Þ
is generated by adding the weighted difference between a pair of
individuals, randomly selected from the population at generation
t, to another individual, as described by the following equation:
V i ðtÞ ¼ X r0 ðtÞ þ FðX r1 ðtÞ  X r2 ðtÞÞ,
Set Ranges
Initialization
Select Base
Vector
No
Reach Maximum
Generations?
Yes
Output
Fig. 1. Flow diagram of the DE algorithm.
ARTICLE IN PRESS
139
where indices r1 and r2 (r1, r2A{1, 2, y, NP}) are randomly chosen
and mutually different, and also different from the current index i.
The scaling factor F (FA(0, 1+)) controls the amplification of the
differential variation (Xr1(t)Xr2(t)). Although F has not an upper
limit, FA(0, 2] is commonly used. The population size NP must be
at least 4, so that the mutation operator can be applied. Vector
Xr0(t) is the base vector to be perturbed. There is a variety of
mechanisms to select this base vector.
After the mutation phase, the crossover operator is applied to
increase the diversity of the population. Thus, for each target
individual, a trial vector Ui(t) ¼ [ui,1(t), y, ui,d(t)] is generated as
follows:
(
vi;j ðtÞ if ðrandðjÞpCRÞ or j ¼ randnðiÞ;
ui;j ðtÞ ¼ (6)
xi;j ðtÞ otherwise;
where rand(j) is a random number uniformly distributed in the
range [0,1]. The index randn(i) is randomly chosen from the set {1,
2, y, d}, and prevents the trial vector from being identical to the
target vector. The parameter CRA[0,1] is a constant called
crossover parameter that controls the diversity of the population.
Following the crossover operation, the selection arises to decide
whether the trial vector Ui(t) will be a member of the population of
the next generation t+1. For a minimization problem, Ui(t) is
compared to the initial target individual Xi(t) by the following
one-to-one based greedy selection criterion:
(3)
(
U i ðtÞ if f ðU i ðtÞÞof ðX i ðtÞÞ;
X i ðt þ 1Þ ¼ (7)
X i ðtÞ otherwise;
where Xi(t+1) is the new individual of the population of the next
(4)
generation, and f(x) is the objective function.
The procedure described above is considered as the standard
version of DE. Several strategies of DE have been proposed,
depending on the selection of the base vector to be perturbed, the
number and selection of the trial vectors and the type of crossover
(5)
operators [32,33]. In our implementation, the base vector Xr0(t) is
selected to be the best member of the current population to share
its information among the individuals of the population and bias
DE Mutation solutions towards better vectors.
Special care has been taken for handling boundaries of the
parameters of the search space. Two classes of boundaries are
distinguished: hard and weak. Hard boundaries are those that
DE Crossover cannot be exceeded (e.g., a passive resistance cannot be negative
or the transistor gate length cannot be below the minimum value
allowed in the technological process), even if there are mathe-
DE Selection matically better solutions beyond those points. During the
execution of the DE algorithm, the overstepped individuals are
set to the nearest bounds. Weak boundaries are those roughly
Update estimated to reasonably limit the search space. Although all
Parameters individuals in the initial population are selected within these
bounds, mutations during the evolution of the population may
yield individuals beyond those limits if better solutions are found.
Unlike GA and particle swarm optimization (PSO), DE can deal
with this problem. DE is also more effective as the accuracy of
local search is better than that of GA and PSO [29].
For some parameters it is also interesting to use logarithmic
scales to favor lower values of the parameters with large spans,
e.g., if a bias current spans over several decades, high values,
hence high power consumption, will be favored if a linear scale is
used. Other parameters must be discretized, e.g., device sizes can
only change according to a given grid. In our implementation,
mutant vectors are allowed to vary continuously, to promote
diversity. However, the parameters are set to the nearest grid
value when evaluating the fitness of the individual.
 ARTICLE IN PRESS
140 B. Liu et al. / INTEGRATION, the VLSI journal 42 (2009) 137–148
4. Constrained analog circuit optimization problem
Though DE is very effective and efficient, it is not enough
for the sizing of analog circuits. All EC algorithms them-
selves lack a mechanism to deal with the constraints of a
problem, which remains an open research area. However,
there exist user-defined specifications for most analog circuit
design problems, and these constraints must be appropriately
handled.
The use of penalty functions is the most common method, but
it is very sensitive to penalty coefficients and can hardly get
satisfactory results without proper penalty coefficients. Though
several penalty strategies [30,31] have been developed to improve
static penalty coefficients, there is no general rule to determine
proper penalty coefficients till now. Michalewicz describes
the difficulties in each available penalty strategy in [34]. More-
over, Michalewicz and Schoenauer [35] concluded that the
static penalty function method without any sophistication
is more robust, as one such sophisticated method may work
well on some problems but may not work well on another
problem.
In this paper, constraints are handled by using the augmented
Lagrangian method, which transforms the constrained optimiza-
tion problem into a problem amenable to the DE algorithm
described in Section 3. Penalty parameters in the augmented
Lagrangian formulation are automatically updated during execu-
tion of the algorithm to reach the optimum point, hence avoiding
the problems related to inappropriate settings of the penalty
parameters. Parameters are updated based on a co-evolution
methodology.
In recent years, co-evolution methodologies, including co-
operative and competitive mode, have attracted much attention.
Methods based on cooperative mode mainly aim at unconstrained
optimization problem [36,37]. Cooperative co-evolution for con-
strained optimization problems has been proposed in Ref. [38]. In
this paper, the competitive co-evolution concept [39–41] and the
modified DE algorithm based on the augmented Lagrangian
method are combined to formulate a hybrid algorithm, CODE,
for constrained optimization problems in analog IC synthesis. We
will begin by introducing augmented Lagrangians, and then
discuss the combination of augmented Lagrangians with compe-
titive co-evolution methodology.
4.1. Augmented Lagrangians
A constrained non-linear optimization problem can be ex-
pressed as
minimize f ðxÞ
g i ðxÞp0; i ¼ 1; . . . ; m
subject to
g j ðxÞ ¼ 0; j ¼ m þ 1; . . . ; n.
These functions can be combined into a single transformation
function U, called the augmented Lagrangians [42]:
1X m
1 X n
Fðx; r; hÞ ¼ f ðxÞ þ r i ððg i þ yi Þ2  y2i Þ þ r ððg þ yj Þ2  y2j Þ.
2 i¼1 2 j¼mþ1 j j
In analog circuit design, equality constraints are limited to current
and voltage relationships imposed by Kirchhoff’s laws: KCL and
KVL. Kirchhoff’s laws are automatically included in the circuit
equations in electrical simulators, so only the inequality con-
straints defined by design specifications have to be taken into
account in the optimization process. Therefore, the augmented
Lagrangian formulation is reduced to:
1X m
Fðx; r; hÞ ¼ f ðxÞ þ r ððg þ yi Þ2  y2i Þ. (10)
2 i¼1 i i
Here, x is the vector of decision variables, r is the vector of penalty
parameters, and mi ¼ riyi is the Lagrangian multiplier associated
with the ith constraint. This process is repeated until convergence.
The optimization objective is to find the saddle point (x0 , l0 ), such
that:
Fðx0 ; l0 ÞpFðx0 ; l0 ÞpFðx0 ; l0 Þ. (11)
In the Lagrangian dual method, there is not such a saddle point
for non-convex problems. However, augmented Lagrangians
addresses the problem by convexifying the objective function
with quadratic penalty terms associated with the constraints [43].
For most practical problems, a saddle point always exists, and x0 is
the optimal solution of the optimization problem.
4.2. Combination of co-evolutionary methodology and augmented
Lagrangians
The main problem of the augmented Lagrangian method is
how to update the Lagrange multipliers so that it converges to the
saddle point to avoid local optimization. A predetermined
updating scheme may work well on some problems but may not
work well on another problem. Co-evolution methodology, relying
on the current evolution result of decision variables, solves this
problem.
Competitive co-evolution method was inspired by observing
predator–prey relationship, where organisms adapt to each other
in a dynamic environment. Groups are rewarded if they defeat
individuals that compete with them. Competitive co-evolution
strategy can be viewed as arm races of two groups [39,40]. To
arouse competition, two populations, whose values of fitness
functions are opposite to each other, must be generated.
In order to find the saddle point in augmented Lagrangians, the
problem can be formulated as
1X m
minx maxm Fðx; r; hÞ ¼ f ðxÞ þ r ððg þ yi Þ2  y2i Þ, (12)
2 i¼1 i i
where x is vector of design variables, and l is the vector of
Lagrangian multipliers. The purpose of the first population is to
minimize F(x, r, h) with individuals in this population encoding
values of x and using a fixed l generated from the second
population. The evolution of this population tries to satisfy the
following property of the saddle point: F(x0 , l0 )pF(x, l0 ) in
Eq. (11). The second population aims to maximize F(x, r, h) with
its individuals encoding values of l and using a fixed x generated
from the first population. The reason of this operation is F(x0 ,
l)pF(x0 , l0 ) in Eq. (11). This process establishes arm races of the
(8) two populations. Once the first population achieves a solution x
with a previous value of l, the second population gets a better l
based on x to defeat it. Then the first population generates a better
x to defeat the second population. At last, the saddle point in
Eq. (11) can be reached, which is the optimal point of x. Values of r
and h are initialized at the beginning of the optimization process,
and are updated at the end of each cycle of DE-based optimiza-
(9)
tion. The penalty coefficients should increase as ri+1 ¼ ri  a after
each cycle, where r0 and a should be initialized first. The flow
diagram of CODE is summarized in Fig. 2.
In the first iteration of the DE-based optimization cycle, an
individual is randomly selected from the second population. Its
purpose is that the first population needs a fixed Lagrangian
multiplier from the second population in the first generation, but
 ARTICLE IN PRESS
B. Liu et al. / INTEGRATION, the VLSI journal 42 (2009) 137–148
Initialize
population A
Start
DE operations
No
Reach generation A?
Yes
Design
variable
Update parameters
Fig. 2. Flow diagram of CODE.
the second population does not start its evolution operations at
the same time.
It can be seen that the CODE algorithm fully inherits the
advantages of the augmented Lagrangian method. The exact
solution can be achieved by augmented Lagrangian method,
whereas this is not true for the static penalty function method
[43]. In addition, the advantages of the differential evolution
algorithm, as described in Section 3, are also inherited. As any
other stochastic optimization algorithm, it cannot be guaranteed
that the global optimum solution is found for every problem, but
the experimental results demonstrate that better solutions than
previous methods are obtained in all cases.
5. Experimental results
In this section, the developed algorithm will be applied to three
practical analog circuit sizing problems and four mathematical
benchmark problems. The three circuit sizing problems corre-
spond to three amplifiers of increasing complexity. The purpose of
these examples is to test the ability of CODE to handle highly-
constrained optimization problems, the ability to handle large
search spaces (large number of design parameters), its compar-
ison to other optimization algorithms and its low sensitivity to the
initial values of the optimization parameters. Finally, benchmark
tests of the evolutionary computation field for constrained
optimization are shown.
In all the examples, the DE step size F is 0.8 and the crossover
probability CR is 0.8. The inner generations of population
encoding values of x is 80 for problems with less than 20
variables, and 100 for other problems, and the generations of
population encoding values of l is 80. The above parameters are
commonly used in DE based algorithms. We used r0 ¼ 1 and
141
Initialize
population B
DE operations
No
Reach generation B?
Yes
Multiplier
No Convergence?
Yes
Best result
a ¼ 1.5 for all the problems, except in the specific experiments
which demonstrate the low sensitivity of the results to these
parameter values. The design parameter search space is quite
wide in all cases. Transistor lengths were allowed to vary between
the minimum value allowed by the technological process to
10 mm. Transistor widths were changed between the minimum
technology value to several hundreds of micrometers. Capacitor
values and bias currents and voltages also had broad (yet
reasonable) ranges.
The inputs to the system are a SPICE net list file containing the
structure, and user defined specifications. All the examples are
run on a 2.4 GHz PC with 1 GB RAM, in the MATLAB environment.
Reported computation times include processing time in MATLAB,
the communication time between HSPICE and MATLAB, and the
simulation time of HSPICE.
5.1. Example 1: Design of a two-stage amplifier
The main purpose of this example is to test the capability of
CODE to handle constraints. A typical Miller-compensated two-
stage amplifier, shown in Fig. 3, is chosen first to test the
algorithm. The technology used is a 0.25 mm CMOS process and
the load capacitance CL is 30 pF. The design parameters are:
transistor widths and lengths, compensation capacitor and bias
currents.
The first experiment tries to achieve the design objectives and
constraints shown in Table 1. Appropriate matching constraints
were established and appropriate operating region was ensured
by imposing constraints like VDS/(VGSVTH)41 for NMOS transis-
tors. The same experiment was tried with the standard genetic
and differential evolution algorithms and using the static penalty
function method to handle constraints (denoted GA+PF and
DE+PF, respectively). We tried to manually improve the penalty
 ARTICLE IN PRESS

142 B. Liu et al. / INTEGRATION, the VLSI journal 42 (2009) 137–148

Table 2
Specifications and results of CODE, GA+PF and DE+PF

Specifications Constraints CODE GA+PF DE+PF

DC gain (dB) X85 86.1 78.436 85.92

GBW (MHz) X2.5 2.5052 6.6431 2.7684
Phase margin (1) X55 57.746 54.958 54.785
Output swing (V) X2 2.0965 2.2274 2.0446
CMRR (dB) X80 80.452 77.553 75.667
PSRR (dB) X85 86.13 78.641 81.02
pffiffiffiffiffiffi
Noise ðnV= HzÞ p20 18.537 7.979 12.575
Slow rate (V/ms) X1.8 1.9709 1.9249 1.8629
Power (mW) Minimize 1.0143 2.4344 2.1298

Total run time (s) 11206 10533 11037

Table 3
Parameters of the two-stage amplifier

W1 (mm) 10.3 W3 (mm) 99.48 W5 (mm) 99.48

W6 (mm) 85.66 W7 (mm) 46.27 L1 (mm) 4.34
L3 (mm) 0.7 L5 (mm) 4.77 L6 (mm) 0.59
L7 (mm) 3.88 Cc (pF) 40.023 Ib (mA) 0.2173

Fig. 3. The Miller-compensated two-stage amplifier.

Table 4
Table 1
Experiments with different initial values of r0 and a
Specifications and results of CODE, GA+PF and DE+PF
Specifications Constraints r0 ¼ 2, a ¼ 2 r0 ¼ 1, a ¼ 3
Specifications Constraints CODE GA+PF DE+PF
DC gain (dB) X85 93.603 86.117
DC gain (dB) X70 76.48 72.601 80.659
GBW (MHz) X2.5 2.5072 3.3719
GBW (MHz) X2 2.068 4.523 2.0406
Phase margin (1) X55 59.708 57.402
Phase margin (1) X50 55.946 49.876 55.641
Output swing (V) X2 2.029 2.07
Output swing (V) X2 2.2017 2.1256 1.9182
CMRR (dB) X80 82.9 80.873
CMRR (dB) X70 90.01 70.99 70.018
PSRR (dB) X85 93.622 86.154
PSRR (dB) X70 76.571 74.658 80.802 pffiffiffiffiffiffi
pffiffiffiffiffiffi Noise ðnV= HzÞ p20 16.204 10.088
Input noise ðnV= HzÞ p60 53.653 50.302 57.004
Slow rate (V/ms) X1.8 1.9555 2.0359
Slow rate (V/ms) X1.5 1.5209 1.649 1.503
Power (mW) Minimize 1.0535 1.0217
Power (mW) Minimize 0.73118 2.215 1.1164
Total run time (s) 10957 11031
Total run time (s) 10097 10126 9865

design parameters obtained by CODE for this case are shown in

coefficients through five runs of the GA+PF and DE+PF algorithms.
At each new run, the penalty coefficients were updated trying to
increase the relative importance of the constraints not met in the
previous run. Table 1 shows the best result from these five runs. It
can be seen that the GA+PF algorithm slightly violates the phase
margin specification and gets a considerably higher power
consumption. Both, the DE+PF and CODE algorithms, meet the
design specifications but CODE achieves a significantly lower
power consumption. Notice that CODE was run only once as no
manual adjustment of penalty parameters is needed.
Table 1 also shows the execution time of the algorithms. This
time includes the communication between MATLAB and SPICE.
Approximately, half of this time is spent in the electrical
simulator. The total CPU time can, hence, be very significantly
reduced by implementing the optimizer in a compiled language
and improving the efficiency of the communication between the
optimizer and the electrical simulator.
To test the ability to handle tighter specifications let us
consider now the specifications in Table 2. It can be observed that
CODE is still able to meet the specifications. However, neither the
GA+PF algorithm nor the DE+PF algorithm are able to, even though
five different sets of penalty coefficients were tried. The
Table 3.
An important advantage of CODE is that the algorithm has a
low sensitivity to the initial settings of the penalty parameters. To
illustrate this, Table 4 shows the results of the application of the
CODE algorithm when different initial values of the optimization
parameters are used. By comparing this table with Table 2, it can
be checked that all constraints are met independently of the initial
values of the optimization parameters. Moreover, variations in the
final value of the objective function keep below 3%.
From these experiments, we can conclude that for low
requirements, CODE and the static penalty methods work
relatively well (the latter usually needs several sets of penalty
coefficients before an acceptable value is found). However, for
problems with many and restrictive constraints, such as the case
above, the drawbacks of both algorithms based on static penalty
methods, GA+PF and DE+PF, become obvious, whereas CODE
consistently performs well.
5.2. Example 2: Design of a TCFC amplifier
The second example will use an amplifier based on the
transconductance with capacitance feedback compensation
 ARTICLE IN PRESS

B. Liu et al. / INTEGRATION, the VLSI journal 42 (2009) 137–148 143

Fig. 4. The TCFC amplifier.

Table 5 Table 7
Specifications and results of the CODE algorithm for the TCFC amplifier Results of the DE+PF algorithm (same specifications than Table 5)

Specifications Constraints Result Specifications PF1 PF2 PF3

DC gain (dB) X80 82.3830 DC gain (dB) 80.217 76.901 81.083

GBW (MHz) X2 2.2186 GBW (MHz) 0.9242 1.8462 2.0853
Phase margin (1) X50 54.4970 Phase margin (1) 50.6 53.66 58.85
Slow rate (V/ms) X1.5 1.56 Slow rate (V/ms) 0.033218 0.8295 3.2081
Power (mW) Minimize 0.1425 Power (mW) 0.050 0.7234 1.6024

Total run time (s) 12553 Total run time (s) 12486 12891 13762

adjust the penalty parameters, still a satisfactory result cannot be

Table 6 achieved.
Results of the GA+PF algorithm (same specifications than Table 5)
We followed a similar procedure with the DE+PF algorithm.
Specifications PF1 PF2 PF3 The results are shown in Table 7. It can be seen that the
constraints are met for one set of penalty coefficients in this case.
DC gain (dB) 83.401 67.794 72.199 But the power consumption obtained is much higher than with
GBW (MHz) 0.50004 2.5645 1.5086 the CODE algorithm.
Phase margin (1) 65.336 54.98 36.5
It can be concluded that in high-performance designs, there
Slow rate (V/ms) 0.0022227 0.2096 1.41
Power (mW) 0.041669 0.15166 1.06 often exist tedious trade-offs to find proper penalty parameters.
Sometimes, a good result can be achieved with static penalty
Total run time (s) 15950 15231 15606
methods by using a proper set of penalty coefficients, but the
search of such penalty coefficients may yield a long and tedious
process.
(TCFC) technique [44]. The TCFC amplifier is shown in Fig. 4 and
the target technology is a 0.35 mm CMOS process. The optimiza-
tion problem contains 36 design parameters, hence, it is
considerably more complex than the previous example. 5.3. Example 3: Design of a gain-boosted folded-cascode amplifier
Table 5 shows the design specifications and the results of
CODE, which successfully meets the constraints. We tried to Finally, we will use the gain-boosted folded-cascode amplifier
design the same circuit using the GA+PF algorithm and using a set in Fig. 5. This is the most complex example in this paper with
of five penalty coefficients: 20, 50, 5, 50 and 100 for the design almost 50 design parameters.
constraints and objectives. The second column in Table 6 shows Table 8 shows the specifications for this amplifier, to be
the results after the execution of the GA+PF algorithm. It can be designed in a 0.25 mm CMOS process. The table also shows the
seen that GBW and SR specifications are not met. Therefore, we constraints (‘‘dm’’ parameters represent the ratio of the drain-
increased the penalties of both constraints, GBW and SR, by a source voltage over the drain–source saturation voltage) that are
factor 3  and executed the algorithm again. The results, in the used to ensure that all transistors are in the saturation region. The
third column of Table 6, show that the slew rate specification is third column shows the results of the CODE algorithm. All
not met yet, the GBW spec is met now but the DC gain and SR constraints are met. The best of five executions of the GA+PF
specs are not met. Then, we tried a third time, increasing the algorithm is shown in the fourth column. Performance specifica-
penalties of SR and DC gain by a factor 2  , resulting in the tions are marginally met but several transistors are out of the
performances shown in the fourth column, in which all the saturation region and power consumption is much higher than in
constraints are violated. Although we tried for another 10 times to the solution provided by CODE. The application of the DE+PF
 ARTICLE IN PRESS
144 B. Liu et al. / INTEGRATION, the VLSI journal 42 (2009) 137–148
Fig. 5. (a) Gain-boosted folded-cascode amplifier; (b) P amplifier and (c) N amplifier.
algorithm is not able to meet the performance specifications and
several transistors are not in the correct operating region.
As stated above, an important advantage of the CODE
algorithm, is that the competitive co-evolution adjusts the penalty
coefficients to the appropriate values. As an illustration, Table 9
shows the evolution of the Lagrange multipliers for all constraints
along several cycles of the co-evolutionary algorithm. It can be
seen that in a few cycles, the multipliers converge to the right
values to achieve a proper solution.
5.4. Benchmark problems for constrained optimization
In computer science, especially in evolutionary computation,
benchmark problems are of great importance to evaluate and
compare different algorithms. Benchmark problems are tough,
and if an algorithm works well in benchmark problems, it is often
regarded as very effective for medium-sized optimization pro-
blems. Three highly-constrained benchmark problems [45],
described in Appendix are tested first. The results for three
experiments with different number of generations are shown in
Tables 10 and 11. Best, worst and average results were extracted
from 15 runs of the algorithm. The results show that the proposed
algorithm for constrained optimization problems, CODE, is quite
effective.
To show the advantages of CODE, the same benchmark
problems were tried with the DE+PF and GA+PF algorithms.
Different penalty coefficients were used in each of the 15 runs and
the best result among them is shown in Table 12.2 The comparison
of computation times is shown in Table 13.
From the comparison, we can conclude that methods based on
penalty functions are worse than the methods based on co-
evolution methods. In particular, unlike many previous works, in
all cases, we use the same optimization parameters introduced
above, which have not undergone any specific calculation in view
2
This is the most favorable comparison for the GA+PF and DE+PF algorithms,
since bad sets of penalty coefficients tend to decrease the mean value.
 ARTICLE IN PRESS

B. Liu et al. / INTEGRATION, the VLSI journal 42 (2009) 137–148 145

Table 8 Table 11
Specifications and results of CODE, GA+PF and DE+PF Results of benchmark problems as a function of the number of generations in
CODE
Specifications Constraints CODE GA+PF DE+PF
Problem Generations
DC gain (dB) 480 112.17 79.995 69.953
GBW (MHz) 4250 256.88 253.93 250.34 500 1000 1500
Phase margin (1) 465 70.128 72.665 72.94
Gain margin o1 0.99952 0.90579 2.7761 G9
dm1a 41.2 19.162 19.269 14.627 Best 682.9565 682.8185 680.6900
dm2 41.2 5.9545 5.0727 0.54239 Average 684.4214 683.6447 682.3335
dm3a 41.2 15.856 26.476 26.554 Worst 689.3154 687.3919 686.9259
dm4a 41.2 4.8841 2.029e-6 4.6684e-8
dm5a 41.2 2.6609 2.3041 0.37412 G7
dm6a 41.2 8.6422 1.0149 2.6458 Best 25.2218 25.2109 24.8946
dm1bp 41.2 7.7727 4.9564 4.6678 Average 28.2832 26.1763 25.6317
dm3bp 41.2 2.8415 1.1078 0.23445 Worst 34.4057 28.9355 27.0023
dm5bp 41.2 18.277 4.8062 0.66502
dm6bp 41.2 5.581 2.0614 0.071441
dm8bp 41.2 12.483 0.00039371 0.96522
Table 12
dm10bp 41.2 4.263 8.2996 21.63
Results of benchmark problems
dm1bn 41.2 6.8212 1.6035 1.6045
dm3bn 41.2 6.2987 0.0082057 0.00012044
Method Problem
dm5bn 41.2 6.9101 0.0198 0.00031191
dm6bn 41.2 2.0146 0.00074711 0.035939
G1 G7 G9
dm8bn 41.2 4.5137 4.0393 4.4812
dm10bn 41.2 2.9358 0.00020514 7.5559e-5
GA+PF 13.7597 685.9112 30.9991
Power (mW) Minimize 4.004 15.508 0.87602
DE+PF 14.9583 683.0213 25.0172
Total run time (s) 5472 6124 5220 CODE 15.0000 680.6900 24.8946

Table 9 Table 13
Evolution of Lagrangian multipliers Computation time on benchmark problems

Specifications Cycle 1 Cycle 2 Cycle 3 Cycle 4 Method Problem

DC gain (dB) 3.4197 0.001318 0.00046544 0.0002567 G1 G7 G9

GBW (MHz) 2.8973 0.025275 0.01 0.01
Phase margin 3.4119 0.01 0.01 0.01 GA+PF 15.87s 79.74s 133.15s
Gain margin 5.3408 0.029214 0.01 0.01 DE+PF 16.02s 61.53s 97.86s
dm1a 7.2711 0.0043268 0.0018774 0.0015662 CODE 10.55s 43.32s 76.30s
dm2 3.0929 0.011876 0.0054239 0.0033819
dm3a 8.385 0.010797 0.0049222 0.0038691
dm4a 5.6807 0.032155 0.01 0.01
of different problems; that is, the algorithm can achieve good
dm5a 3.7041 0.01 0.01 0.01
dm6a 7.0274 0.023379 0.003503 0.0020054 result without detailed parameters studies.
dm1bp 5.4657 0.0089035 0.0048879 0.0033824 In addition, in order to test the ability of CODE to deal with
dm3bp 4.4488 0.010513 0.003444 0.0017828 active constraints in optimization problems, the benchmark
dm5bp 6.9457 0.034867 0.01466 0.01 problem in Ref. [46] was selected (Test problem 4 in Appendix)
dm6bp 6.2131 0.0078141 0.0027322 0.0019259
dm8bp 7.9482 0.052685 0.01 0.01
In this problem, both constraints are active at the optimum. The
dm10bp 9.5684 0.0095579 0.0036852 0.0024163 best results of CODE, GA+PF and DE+PF after 15 runs are 5.5080,
dm1bn 5.2259 0.0048001 0.0019227 0.0015987 5.6833 and 5.5538, respectively.
dm3bn 8.8014 0.00042661 0.00014712 8.7983e-5
dm5bn 1.7296 0.01 0.01 0.01
dm6bn 9.7975 0.051865 0.001417 0.0013897
6. Conclusions
dm8bn 2.7145 0.0037478 0.0028153 0.0016745
dm10bn 2.5233 0.0079334 0.0028515 0.0020671
This paper presents CODE: an evolutionary-based system for
parameter-level design of analog integrated circuits. The basic
elements of the system are a co-evolutionary methodology based
on a differential evolution algorithm and the use of augmented
Lagrangians to represent the constrained non-linear optimization
Table 10 problem. CODE achieves the following three novel features: (1) it
Results of benchmark problems as a function of the number of generations in avoids the tedious tuning of penalty coefficients, (2) it can closely
CODE meet the designer’s specifications even for highly-constrained
problems, and (3) it is suitable for medium or large-scale
Problem Generations
problems. Moreover, CODE is efficient.
100 300 500

G1 Acknowledgments
Best 14.9501 14.9999 15.0000
Average 13.2311 14.8068 14.8821
Worst 11.4860 13.8913 13.9021
This work has been supported by National Natural Science
Foundation of China grant no. 60676012 and Special Funds for
 ARTICLE IN PRESS

146 B. Liu et al. / INTEGRATION, the VLSI journal 42 (2009) 137–148

Major State Basic Research Projects no. 2002CB311907. We Test problem 3

acknowledge valuable discussions with Dr. Ziqiang Wang and
Dr. Xueyi Yu, Institute of Microelectronics of Tsinghua University, Minimize
China. We are grateful to Mr. Hannan Ma, Department of
Electronic Engineering, for his contribution to the program. Dr. G7 ðxÞ ¼ x21 þ x22 þ x1 x2  14x1  16x2 þ ðx3  10Þ2
F.V. Fernández thanks the support of the TEC2004-01752 and þ 4ðx4  5Þ2 þ ðx5  3Þ2 þ 2ðx6  1Þ2 þ 5x27
TEC2007-67247 Projects, funded by the Spanish Ministry of þ 7ðx8  11Þ2 þ 2ðx9  10Þ2 þ ðx10  7Þ2 þ 45
Education and Science with support from ERDF, and by the TIC-
2532 Project, funded by Consejerı́a de Innovación, Ciencia y subject to
Empresa, Junta de Andalucı́a. We also thank the reviewers for 105  4x1  5x2 þ 3x7  9x8 X0,
their comments that helped to improve the presentation of the
paper.  3ðx1  2Þ2  4ðx2  3Þ2  2x23 þ 7x4 þ 120X0,
 10x1 þ 8x2 þ 17x7  2x8 X0,
 x21  2ðx2  2Þ2 þ 2x1 x2  14x5 þ 6x6 X0,
Appendix. Description of benchmark test problems 8x1  2x2  5x9 þ 2x10 þ 12X0,
 5x21  8x2  ðx3  6Þ2 þ 2x4 þ 40X0,
Test problem 1
3x1  6x2  12ðx9  8Þ2 þ 7x10 X0,
Minimize  0:5ðx1  8Þ2  2ðx2  4Þ  3x25 þ x6 þ 30X0,

X
4 X
13 with
G1 ðxÞ ¼ 5x1 þ 5x2 þ 5x3 þ 5x4  5 x2i  xi
i¼1 i¼5
10pxi p10; i ¼ 1; . . . ; 10.

subject to: The optimum solution is

2x1 þ 2x2 þ x10 þ x11  10p0, xn ¼ ð2:171996; 2:363683; 8:773926; 5:095984,

2x1 þ 2x3 þ x10 þ x12  10p0, 0:9906548; 1:430574; 1:321644; 9:828726; 8:280092; 8:375927Þ

2x2 þ 2x3 þ x11 þ x12  10p0, and the function value is: G7 ðxn Þ ¼ 24:3062091.
 2x4  x5 þ x10 p0,
 2x6  x7 þ x11 p0, Test problem 4
 2x8  x9 þ x12 p0,
 8x1 þ x10 p0, Minimize
 8x2 þ x11 p0, G0 ðxÞ ¼ x1  x2
 8x3 þ x12 p0, subject to:
with
x2  2x41 þ 8x31  8x21  2p0
0pxi p1; i ¼ 1; . . . ; 9 x2  4x41 þ 32x31  88x21 þ 96x1  36p0
0pxi p100; i ¼ 10; 11; 12
with
0px13 p1
0px1 p3; 0px2 p4.
The optimum solution is xn ¼ ð1; 1; 11; 1; 1; 1; 1; 1; 3; 3; 3; 1Þ and the
function value is G1(x) ¼ 15. The optimum solution is:
xn ¼ ð2:32952024; 3:17849288Þ
Test problem 2 and the function value is: G0 ¼ 5:508013271.

Minimize References

G9 ðxÞ ¼ ðx1  10Þ2 þ 5ðx2  12Þ2 þ x43 þ 3ðx4  11Þ2 þ 10x65

[1] D. Nam, Y. Seo, L. Park, C. Park, B. Kim, Parameter optimization of an on-chip
þ 7x26 þ x47  4x6 x7  10x6  8x7 voltage reference circuit using evolutionary programming, IEEE Trans. Evol.
Comput. 5 (4) (2001) 414–421.
subject to [2] E. Martens, G. Gielen, Classification of analog synthesis tools based on their
architecture selection mechanisms, Integr. – VLSI J. 41 (2) (2008 Feb)
2x21 þ 3x42 þ x3 þ 4x24 þ 5x5  127p0, 238–252.
[3] M. Krasnicki, R. Phelps, J. Hellums, M. McClung, R. Rutenbar, L. Carley, ASF: a
7x1 þ 3x2 þ 10x23 þ x4  x5  282p0, practical simulation-based methodology for the synthesis of custom analog
circuits, Proc. Int. Conf. Comput. Aid. Design (2001) 350–357.
23x1 þ x22 þ 6x26  8x7  196p0, [4] M.G.R. Degrauwe, O. Nys, E. Dijkstra, J. Rijmenants, S. Bitz, B.L.A.G. Goffart,
4x21 þ x22  3x1 x2 þ 2x23 þ 5x6  11x7 p0, E.A. Vittoz, S. Cserveny, C. Meixenberger, G. van der Stappen, H.J. Oguey, IDAC:
an interactive design tool for analog CMOS circuits, IEEE J. Solid-State Circuits
with 22 (6) (1987) 1106–1116.
[5] R. Harjani, R.A. Rutenbar, L.R. Carley, OASYS: a framework for analog circuit
synthesis, IEEE Trans. Comput. Aid. Design 8 (12) (1989) 1247–1265.
10pxi p10; i ¼ 1; . . . ; 7.
[6] C.A. Makris, C. Toumazou, Analog IC design automation: Part II. Automated
The optimum solution is: circuit correction by qualitative reasoning, IEEE Trans. Comput. Aid. Design 14
(2) (1995) 239–254.
[7] E. Ochotta, R. Rutenbar, L.R. Carley, Synthesis of high-performance analog
xn ¼ ð2:330499; 1:951372; 0:4775414; 4:365726,
circuits in ASTRX/OBLX, IEEE Trans. Comput. Aid. Design 15 (1996) 273–294.
 0:6244870; 1:038131; 1:594227Þ [8] G. Gielen, H. Walsharts, W. Sansen, Analog circuit design optimization based
on symbolic simulation and simulated annealing, IEEE J. Solid-State Circuits
and the function value is: G9 ðxn Þ ¼ 680:6300573. 25 (3) (1990).
 ARTICLE IN PRESS
B. Liu et al. / INTEGRATION, the VLSI journal 42 (2009) 137–148
[9] P.C. Maulik, L.R. Carley, D.J. Allstot, Sizing of cell-level analog circuits using
constrained optimization techniques, IEEE J. Solid-State Circuits 28 (3) (1993)
233–241.
[10] S. Wang, H. Gao, Z. Wang, The research of parameter optimization design
method for analog circuit, in: Proceedings of the Instrumentation and
Management Technology Conference, 2004, pp. 1515–1518.
[11] M. Hershenson, S. Boyd, T. Lee, Optimal design of a CMOS op-amp via
geometric programming, IEEE Trans. Comput. Aid. Design of ICs 20 (1) (2001)
1–21.
[12] W. Nye, D.C. Riley, A. Sangiovanni-Vincentelli, A.L. Tits, DELIGHT. SPICE: an
optimization-based system for the design of integrated circuits, IEEE Trans.
Comput. Aid. Design 7 (4) (1988) 501–519.
[13] R. Phelps, M.J. Krasnicki, R.A. Rutenbar, L.R. Carley, J.R. Hellums, Anaconda:
simulation-based synthesis of analog circuits via stochastic pattern search,
IEEE Trans. Comput. Aid. Design 19 (6) (2000) 703–717.
[14] F. Medeiro, R. Rodrı́guez-Macı́as, F.V. Fernández, R. Domı́nguez-Castro, J.L.
Huertas, A. Rodrı́guez-Vázquez, Global design of analog cells using statistical
optimization techniques, Analog Integr. Circuits Signal Process. 6 (3) (1994)
179–195.
[15] R. Castro-López, F.V. Fernández, O. Guerra, A. Rodrı́guez, Reuse Based
Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated
Circuits, Springer, 2006.
[16] G. Stehr, M. Pronath, F. Schenkel, H. Graeb, K. Antreich, Initial sizing of analog
integrated circuits by centering within topology-given implicit specifications,
in: Proceedings of the IEEE/ACM International Conference of Computer Aided
Design, 2003, pp. 241–246.
[17] S. Balkir, G. Dundar, G. Alpaydin, Evolution based synthesis of analog
integrated circuits and systems, in: Proceedings of the NASA/DoD Conference
on Evolution Hardware, 2004.
[18] K. Takemura, T. Koide, H. Mattausch, T. Tsuji, Analog-circuit-component
optimization with genetic algorithm, in: Proceedings of the 47th IEEE
International Midwest Symposium on Circuits and Systems, 2004,
pp. 489–492.
[19] M. Barros, G. Neves, J. Guilherme, N. Horta, An evolutionary optimization
kernel with adaptive parameters applied to analog circuit design, in:
Proceedings of the International Symposium on Signals, Circuits and Systems,
2005, pp. 545–548.
[20] C. Goh, Y. Li, GA automated design and synthesis of analog circuits with
practical constraints, IEEE Cong. Evol. Comput. 1 (2001) 170–177.
[21] J. Koza, F. Bennett, D. Andre, M. Keane, F. Dunlap, Automated synthesis of
analog electrical circuits by means of genetic programming, IEEE Trans. Evol.
Comput. 1 (2) (1997) 109–128.
[22] G. Alpaydin, S. Balkir, G. Dundar, An evolutionary approach to automatic
synthesis of high performance analog integrated circuits, IEEE Trans. Evol.
Comput. 7 (3) (2003).
[23] W. Kruiskamp, D. Leenaerts, Darwin: CMOS opamp synthesis by means of a
genetic algorithm, in: Proceedings of the ACM/IEEE Design Automation
Conference, 1995, pp. 433–438.
[24] Virtuoso NeoCircuit circuit sizing and optimization. Homepage: /http://
www.cadence.com/products/custom_ic/neocircuit/index.aspxS.
[25] /http://www.mathworks.com/products/matlab/S.
[26] /http://www.synopsys.com/products/mixedsignal/hspice/hspice.htmlS.
[27] G. Rudolph, Convergence analysis of canonical genetic algorithms, IEEE Trans.
Neural Netw. 5 (1994) 96–101.
[28] J. Kennedy, R. Eberhart, Y. Shi, Swarm Intelligence, Morgan Kaufmann
Publishers, San Francisco, 2001.
[29] R. Storn, K. Price, Differential evolution—a simple and efficient heuristic for
global optimization over continuous spaces, J. Global Opt. 11 (1997) 341–359.
[30] J. Joines, C. Houck, On the use of nonstationary penalty functions to solve
nonlinear constrained optimization problems with GAs, Proc. IEEE Int. Conf.
Evol. Comput. (1994) 579–584.
[31] K. Deb, An efficient constraint handling method for genetic algorithm,
Comput. Methods Appl. Mech. Eng. 186 (2000) 311–338.
[32] K. Price, R. Storn. Differential evolution. Homepage: /http://www.ICSI.Ber-
keley.edu/storn/code.htmlS.
[33] K. Price, R. Storn, J. Lampinen, Differential Evolution. A Practical Approach to
Global Optimization, Springer, 2005.
[34] Z. Michalewicz, Genetic algorithms, numerical optimization, and constraints,
in: L. Eshelman (Ed.), Proceedings of the Sixth International Conference on
Genetic Algorithms, Morgan Kaufman, San Mateo, 1995, pp. 151–158.
[35] Z. Michalewicz, M. Schoenauer, Evolutionary algorithms for constrained
parameter optimization problems, Evol. Comput. 4 (1) (1996) 1–32.
[36] Y. Shi, H. Teng, Z. Li, Cooperative co-evolutionary differential evolution for
function optimization, ICNC (2) 2005, Lecture Notes in Computer Science,
2005, pp 1080–1088.
[37] M.A. Potter, K.A. De Jong, A cooperative co-evolutionary approach to function
optimization, in: Proceedings of the Third Parallel Problem Solving From
Nature, Jerusalem, Israel, 1994, pp. 249–257.
[38] B. Liu, H. Ma, X. Zhang, B. Liu, A memetic cooperative co-evolutionary
differential evolution algorithm for constrained optimization problems, IEEE
Cong. Evol. Comput., 2007.
[39] M. Kirley, A co-evolutionary genetic algorithm for job shop scheduling
problems, in: Proceedings of 3rd International Conference on Knowledge-
Based Intelligent Information Engineering System, Australia, 1999, pp. 84–87.
[40] J. Paredis, Steps towards co-evolutionary classification neural networks,
Artificial Life 5, MIT Press, 1994.
147
[41] H. Barbosa, A coevolutionary genetic algorithm for constrained optimization,
IEEE Cong. Evolut. Comput. (1999) 1605–1611.
[42] R.T. Rockafellar, Convex Analysis, 1972.
[43] M.S. Bazaraa, H.D. Sherali, C.M. Shetty, Nonlinear Programming: Theory and
Algorithms, second ed., Wiley, New York, 1993.
[44] X. Peng, W. Sansen, Transconductance with capacitances feedback compen-
sation for multistage amplifiers, IEEE J. Solid-State Circuits 40 (7) (2005)
1514–1520.
[45] S. Koziel, Z. Michalewicz, Evolutionary algorithms, homomorphous
mappings, and constrained parameter optimization, Evol. Comput. 7 (1)
(1999) 19–44.
[46] Z. Michalewicz, Evolutionary computation techniques for nonlinear program-
ming problems, Int. Trans. Oper. Res. 1 (2) (1994) 223–240.
Bo Liu was born in Beijing, China, on September 23,
1984. He is currently a senior undergraduate student in
Tsinghua University, Beijing, China. Since 2005, he has
been a Research Assistant at the Tsinghua National
Laboratory for Information Science and Technology,
Beijing, China. Since 2007, he has been a Research
Assistant at the CAD Laboratory, Institute of Micro-
electronics, Tsinghua University, Beijing, China. He is
also a member of Analog Design Automation Research
Group of University of Sevilla, Sevilla, Spain. His
research interests include analog integrated circuit
synthesis and evolutionary computation algorithms.
Yan Wang received the B.S. and M.S. degrees in
electrical engineering from Xi’an Jiaotong University,
Xi’an, China, in 1988 and 1991, respectively, and the
Ph.D. degree in semiconductor device and physics from
the Institute of Semiconductors, Chinese Academy of
Science, Beijing, China, in 1995. Since 1999, she has
been a Professor with the Institute of Microelectronics,
Tsinghua University, Beijing, China. Her research
focuses on semiconductor device modeling.
Zhiping Yu graduated from Tsinghua University, Beij-
ing, China, in 1967 with B.S. degree. He received his
M.S. and Ph. D degrees from Stanford University,
Stanford, CA, USA in 1980, and 1985, respectively. He
is presently the professor in the Institute of Microelec-
tronics, Tsinghua University, Beijing, China. From 1989
to 2002, he has been a senior research scientist in the
Dept. of Electrical Engineering in Stanford University,
USA, while serving as the faculty member in Tsinghua.
He returned to Tsinghua full time since September
2002 and holds Pericom Microelectronics Professor-
ship (2002-2004) established by Pericom Semiconduc-
tor Corp. in San Jose, USA. His research interests
include device simulation for nano-scale MOSFETs, quantum transport in
nanoelectronic devices, compact circuit modeling of passive and active compo-
nents in RF CMOS, and numerical analysis techniques.
Leibo Liu received the B.S. and Ph.D. degrees in
electronic engineering from Tsinghua University, Beij-
ing, China, in 1999 and 2004, respectively. He is
currently an associate professor with the Institute of
Microelectronics, Tsinghua University, Beijing, China.
His research interests include reconfigurable processor
design and design methodologies, and system-level
energy-aware design approaches for portable applica-
tions.
Miao Li received the B.S. in electronic engineering from
Tsinghua University, PR China, in 2006. He was at the
Institute of Microelectronics of Tsinghua University
from the September of 2006 to now. His research
focuses on modeling of III–V compound semiconductor
materials and devices.
 ARTICLE IN PRESS
148 B. Liu et al. / INTEGRATION, the VLSI journal 42 (2009) 137–148
Zheng Wang is an undergraduate student in electronic
engineering from Tsinghua University, Beijing, China.
Jing Lu received the B.S. in electronic engineering from
Tsinghua University, China, in 2005. She was a
graduate student at the Institute of Microelectronics
of Tsinghua University from 2005 and will receive the
master degree in 2008. Her research focuses on
modeling of III–V compound semiconductor materials
and devices.
F.V. Fernández got the Physics-Electronics degree from
the University of Seville in 1988 and his Ph.D. degree in
1992. In 1993, he worked as a postdoctoral research
fellow at Katholieke Universiteit Leuven (Belgium).
Since 1995, he is an Associate Professor at the
Department of Electronics and Electromagnetism of
University of Sevilla. He is also a researcher at CSIC-
IMSE-CNM. His research interests lie in the design and
design methodologies of analog and mixed-signal
circuits. Dr. Fernández has authored or edited three
books and has co-authored more than 100 papers in
international journals and conferences. Dr. Fernández
is currently the Editor-in-Chief of Integration, the VLSI
Journal (Elsevier). He regularly serves at the Program Committee of several
international conferences. He has also participated as researcher or main
researcher in several National and European R&D projects.