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Published in IET Circuits, Devices & Systems

Received on 13th January 2009
Revised on 16th May 2009
doi: 10.1049/iet-cds.2009.0072

ISSN 1751-858X

Quadrature oscillator using grounded

components with current and voltage outputs
S. Maheshwari
Department of Electronics Engineering, Z. H. College of Engineering and Technology, AMU, Aligarh 202 002, India
E-mail: maheshwarispm@rediffmail.com

Abstract: This study proposes new third-order quadrature oscillator that provides several voltage and current
outputs simultaneously. The circuit uses differential voltage current conveyors and grounded components,
enjoys non-interactive frequency control and can be made resistor-less by using voltage-controlled differential
voltage current conveyors. Non-ideal study and parasitic effects are also considered and their effects are
discussed. The proposed theory is verified through PSPICE by good results.

1 Introduction opamps, which were somewhat addressed by the use of

Ever since their introduction by Sedra and Smith [1], the utility
and advantages of current conveyors and their numerous
offshoots have been often highlighted in the technical
literature [2, 3]. Sinusoidal oscillators, quadrature oscillators
and multiphase oscillators form important blocks of a typical
information system, instrumentation or communication
system. A lot of attention has thus been given to oscillators
utilising the advantages and versatility of various types of
current conveyors [4–16]. The current conveyors were used
in realising oscillators long back [4, 5]. Multiphase oscillator
employing translinear conveyors was also reported [6].
Differential difference current conveyor was also used for
realising a catalogue of oscillators with single resistor control
property and employing grounded components [8]. One very
compact quadrature oscillator using current differencing
transconductance amplifier (CDTAs) was recently proposed
[10]. Another set of compact oscillators using a new and
versatile active building block were also published [11]. An
electronically tunable quadrature oscillator using only two
translinear conveyors and grounded capacitors, with voltage
and current outputs, was also published, which was based on
a new inductor [12]. One of the works presented very
compact quadrature oscillator based on a single fully
differential second generation current conveyor (FDCCII)
and grounded components with both current and voltage
outputs [13]. Several quadrature oscillators based on first-
order all-pass filter and integrator loop topology also received
attention [15, 16]. Earlier, opamps had been very effectively
utilised for the purpose with the well-known limitations of
current conveyors ([17, 18] and cited therein). Although
opamps still enjoy ready commercial availability, unlike
current conveyors that are still very few in IC form, this does
not affect their popularity amongst researchers, as is evident
from the wealth of published literature ([1–6, 8–16, 19–24]
and cited therein). Moreover, the circuits based on newer
active elements are better targeted for IC implementation
rather than for realisation using off-the-shelf ICs. Most of the
works on oscillators fell in the category of second-order
oscillators and were realised either using a generalised
network or derived from simpler bilinear blocks.
2 Existing knowledge
The differential voltage current conveyor (DVCC) was first
used for realising oscillator circuit by Gupta and Senani
[21]. Thereafter, a catalogue of 24 second-order oscillator
circuits using differential difference current conveyor
(DDCC) and grounded components were proposed by the
same authors [22]. Similarly, another catalogue of eight
second-order oscillators with both current and voltage
outputs were also reported [23]. It is interesting to note
that the useful catalogue of second-order oscillators [22,
23] benefits from using fewer active and passive elements
when compared to the third-order oscillators [9, 14]. Next,
some third-order oscillators are also available. One of these
was based on operational transconductance amplifier [7].
Another set of three circuits were proposed for third-order
quadrature oscillator, each with three current conveyors and
eight grounded passive components with the exception of

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one circuit that employed floating resistors. Each of the new

circuits provided two quadrature voltage outputs [14]. The
current-controlled current conveyor and capacitor-based
third-order quadrature oscillator was also reported, which
was realised using a new low-pass biquad and integrator
loop topology [9]. The reported third-order oscillator
employed four current controlled current conveyors
(CCCIIs) and three grounded capacitors, and provided four
current outputs, all at high impedance, suited for current-
mode analogue signal processing. Although it is not fair to
draw comparison between the second-order circuits with
third-order ones, the former ones enjoy compact realisation
[22, 23, 25, 26] and the latter ones in general show better
distortion performance [7, 9, 14]. Whereas the most
modern second-order circuits have useful applications, the
new proposed third-order one would show better accuracy
and lower distortions, in integrated form, which is
important for most practical applications.

This paper proposes a new third-order quadrature oscillator

based on three active elements as against four in the recent
relevant work [9]. When compared to the other third-order
circuits, the new circuit requires fewer resistors (three against
five), whereas provides a number of voltage as well as current
outputs unlike the available ones [7, 14]. For better clarity and
comparison with other third-order oscillators, Table 1 lists the
salient features and novelty of the new proposed circuit in Figure 1 Differential voltage current conveyor (DVCC)
light of the already reported and useful works. The new a Symbol
circuit employs all grounded components and provides high b CMOS implementation
impedance current outputs and quadrature voltage outputs.
The new active-RC circuit can also be converted to active-C
oscillator by eliminating external resistors at the X-terminal of In recent years, a lot of attention has been paid to the
the current conveyors. PSPICE simulation results to support realisation of networks for analogue signal processing using
the validity of the new proposed circuit are also given. this active element [15, 19– 24].

3 Proposed circuit The new quadrature oscillator based on DVCC uses the
The DVCC symbol and its CMOS implementation are same scheme as recently reported for third-order oscillator
[9]. It employs a new DVCC-based low-pass biquad filter
shown in Fig. 1; the same is characterised by the following
port relationship and the well-known inverting integrator, realised using
DVCC in closed loop. The resulting circuit is shown in
Fig. 2. Here, B/A realises the low-pass biquad filter function
Vx ¼ Vy1  Vy2 ; Iy1 ¼ Iy2 ¼ 0; Iz þ ¼ Ix ; Iz ¼ Ix
whereas; C/B realises the inverting integrator function.
(1) With closed loop, C ¼ A, and the system characteristic

Table 1 Comparative study of proposed circuit with other third-order oscillators

Reference Active Resistors Capacitors Current Voltage Quadrature FO control

elements sources outputs current outputs without affecting
accessible CO
[7] 3 or 4 0 or 1 3 4, floating 3 or 4 no no
[9] 4 0 3 4, 3 yes yes
grounded
[14] 3 5 or 3 3 or 5 none 3 no no
[proposed] 3 3 3 none 5 yes yes
(Fig. 2)

154 IET Circuits Devices Syst., 2009, Vol. 3, Iss. 4, pp. 153– 160
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Figure 2 Proposed third-order quadrature oscillator
equation is expressed as below
1 2 1 1
s3 þ s þ sþ ¼0
R 2 C1 R1 R2 C1 C2 R1 R2 R3 C1 C2 C3
Replacing s ¼ jv and equating real and imaginary terms, the
above equation yields the frequency of oscillation (FO) and
condition of oscillation (CO) as
1 of Fig. 3 with the present implementation of DVCC. The
FO : fo ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ; CO : R2 C1 ¼ R3 C3
2p R1 R3 C2 C3
Equation (3) shows that the FO can be maintained
independent of CO by varying R1 , if equal capacitor design
is used. Similarly, the CO is maintained independent of FO
by varying R2 . Non-interactive frequency control is a
desirable feature of an oscillator circuit. The various voltage
and current outputs are related as
V5 ¼ jk1 V4 ; V3 ¼ jk2 V2 ; V1 ¼ V3 ; I1 ¼ jk3 I2 (4)
where k1 ¼ voR1C2 k2 ¼ voR3C3 k3 ¼ voR3C1 and vo ¼
2Pfo .
It is evident from (4) that in all seven outputs are
obtained. Two quadrature voltages in the form of V4 and
V5 and three quadrature outputs with a progressive phase
shift of 908, in the form of V1 , V2 and V3 are obtained. It
is quite worth noting that the voltage outputs unlike the
available current outputs do not appear at appropriate
(low) impedance level. The two current outputs are
available at desired high impedance level and also exhibit
a quadrature relationship. The various outputs generated
have their relative amplitudes, decided by k1 – 3 . By
designing the circuits for ‘k1 – 3 ¼ 1’, all the outputs would
posses equal amplitudes.
Utilising the fact that the X terminals are terminated with
only resistors, the proposed third-order quadrature oscillator
can be made resistor-less. Recently, it was shown in the
literature that a DVCC can be made tunable by varying its
X-terminal resistance through the bias voltage [24]. The
resistor-less tunable quadrature oscillator circuit is shown in
Fig. 3, and uses voltage-controlled DVCC (VC-DVCC).
However, it must be noted that V3 and V5 will not be
IET Circuits Devices Syst., 2009, Vol. 3, Iss. 4, pp. 153– 160
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Figure 3 Electronically tunable third-order quadrature
oscillator
accessible in the resistor-less circuit. The analysis of (2) and
(3) is valid for the circuit except for the difference that the
external resistor are replaced by Rxi , (i ¼ 1 – 3). Here, Rxi is
the intrinsic X-terminal resistance of DVCC, which has
(2)
limited tunability through the bias voltage VBB [24]. The
resistor-less circuit is comparable to the available current-
controlled third-order quadrature oscillator, with the
advantage of three active elements as against four in the
available work [9]. It is needless to mention that the wide
tunability achieved in [9] is not possible in the new circuit
(3) implementation of DVCC with wide linear control of Rx is
a natural work for further investigation.
Another possible technique often used for tuning active-
RC circuit (like Fig. 2) is the resistor replacement by active
means. This requires external resistors to be replaced by
transistorised circuitry for enabling tuning. As a result, the
circuit complexity is further increased. On the other hand,
utilisation of the active element’s intrinsic resistance for
tuning purpose does not add to the complexity [24]. That
is why this technique has been quite popular in the recent
literature ([7, 9, 12] and cited therein).
4 Parasitics’ study
The effect of DVCC parasitics on the performance of new
quadrature oscillator is considered. The various ports of
DVCC are characterised by parasitic capacitances. These
can be denoted as CY1,2 , CX and CZ for various ports;
suffices referring to the respective port. In the proposed
circuit topology, external capacitors are connected at either
Y or Z terminals; moreover a number of Y and Z terminals
are connected together in many cases. Therefore the
parasitic capacitances at these ports actually merge with the
external capacitors by way of appearing in shunt with them.
The effective values of the capacitors thus become
C10 ¼ C1 þ 3CY þ CZ ; C20 ¼ C2 þ CY þ CZ ;
C30 ¼ C3 þ CY þ CZ (5)
Here, assumption is made that all Y terminal parasitic
capacitances of different DVCCs are equal; and so are the
Z terminal parasitic capacitances of all DVCCs. As the
parasitic capacitances are in range of pFs or even smaller,
155
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depending on the technology, their effects would be
negligible, as the external capacitors used in the design are
expected to be larger in comparison to the parasitic ones. It
is further to be noted that the X terminal parasitic
capacitances do affect the circuit’s performance, but is not
to be seen as a drawback as most of the current conveyors
based circuits actually are based on the use of resistors at X
terminals. Such a topology is so popular because of the
advantage of terminating X terminals with resistors. The
intrinsic X-terminal resistance (low for second-generation
current conveyors; DVCC falls in the same category)
merges with external resistors in all such topologies.
Actually, this feature is further utilised to derive active-C
networks by getting rid of resistors; these circuits benefit
from resistor-less realisation with the added advantage of
electronic tuning [7, 9, 10]. Coming back to the proposed
circuit, X-terminal resistance (Rx) merger with external
ones increases the effective value of external resistors
(R i0 ¼ Ri þ Rx; i ¼ 1 – 3). As a result of the effective
capacitances and effective resistances, a certain discrepancy
would be expected in the simulated FO from the designed
value. The discrepancy will theoretically yield the actual
FO, in deficit to the designed value. Now taking the
above-discussed parasitics, the modified expressions for FO
and CO are given as
1 Z2) deviate from unity by the current transfer errors. These
FO : fo ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ; CO : R20 C10 ¼ R30 C30
2p R10 R30 C20 C30
In (6) the effective capacitors and resistors are the ones as
given in (5) and discussed above, respectively.
It may be pointed out here that a second-generation
current conveyor (DVCC is its differential input version) is
characterised by port Y and port Z parasitic resistances, Ry
and Rz , respectively. Since, Y is the voltage input terminal,
it offers high input resistance (Ry); similarly, Z is the
output current terminal and shows high output resistance
(Rz). For the present case, where DVCC is used, Y
terminals are the gates of the MOS transistors, and hence
show an extremely high input impedance to be considered
open circuited as a good approximation. As far as
Z-terminal resistance (Rz) is concerned, it depends on the
output resistance (shunt combination) of the two MOS
transistors, forming the output stage (for instance, M8 and
M12 for Zþ stage). This in turn is bias current dependent
besides being also a function of channel length modulation
(1/l ) parameter. The inclusion of Rz , which is in order of
100s of kV, results in deviations in the characteristic
equation of the oscillator circuit. However, for real device
simulations, these effects are very much a part and parcel of
the simulated circuit. The discrepancy and errors are to be
given in the section presenting the results.
5 Non-ideal analysis
A practical DVCC like any other active element can be
characterised by non-ideal transfer gains. Thus the defining
equation for DVCC gets modified to
Vx ¼ b1 Vy1  b2 Vy2 ; Iy1 ¼ Iy2 ¼ 0; Izþ ¼ a1 Ix ;
Iz ¼ a2 Ix (7)
The voltage transfer gains b1 from Y1 to X, and b2 from Y2 to
X deviate from unity by voltage transfer errors. Similarly, the
current transfer gains a1 (from X to Zþ) and a2 (from X to
(6)
errors are expected to be quite low for an integrated DVCC,
thus making voltage and current transfer gains to approach
Table 3 Device dimensions used in simulation
Transistors L, mm W, mm
M1, M2, M3, M4 1 1.6
M5, M6 1 8
M9, M10 1 29
M7, M8, M13, M14, M15 1 20
M11, M12, M16, M17, M18 1 90

Table 2 MIETEC 0.5m parameters used

NMOS
LEVEL ¼ 3, UO ¼ 460.5, TOX ¼ 1.0  1028 TPG ¼ 1, VTO ¼ 0.62, JS ¼ 1.8  1026, XJ ¼ 0.15  1026, RS ¼ 417,
RSH ¼ 2.73, LD ¼ 0.04  1026, ETA ¼ 0, VMAX ¼ 130  103, NSUB ¼ 1.71  1017, PB ¼ 0.761, PHI ¼ 0.905,
THETA ¼ 0.129, GAMMA ¼ 0.69, KAPPA ¼ 0.1, AF ¼ 1, WD ¼ 0.11  1026, CJ ¼ 76.4  1025, MJ ¼ 0.357,
CJSW ¼ 5.68  10210, MJSW ¼ 0.302, CGSO ¼ 1.38  10210, CGDO ¼ 1.38  10210, CGBO ¼ 3.45  10210,
KF ¼ 3.07  10228, DELTA ¼ 0.42, NFS ¼ 1.2  1011
PMOS
LEVEL ¼ 3, UO ¼ 100, TOX ¼ 1.0  1028, TPG ¼ 1, VTO ¼ 20.58, JS ¼ 0.38  1026, XJ ¼ 0.1  1026, RS ¼ 866,
RSH ¼ 1.81, LD ¼ 0.03  1026, ETA ¼ 0, VMAX ¼ 113  103, NSUB ¼ 2.08  1017, PB ¼ 0.991, PHI ¼ 0.905,
THETA ¼ 0.120, GAMMA ¼ 0.76, KAPPA ¼ 2, AF ¼ 1, WD ¼ 0.14  1026, CJ ¼ 85  1025, MJ ¼ 0.429,
CJSW ¼ 4.67  10210, MJSW ¼ 0.631, CGSO ¼ 1.38  10210, CGDO ¼ 1.38  10210, CGBO ¼ 3.45  10210,
KF ¼ 1.08  10229, DELTA ¼ 0.81, NFS ¼ 0.52  1011

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unity at working frequencies. However, as frequently circuit is analysed and found to modify the characteristic
emphasised in literature these gains are frequency equation.
dependent with a first-order roll-off at high frequency. It
has been confirmed that their values remain unity up to
100 MHz for the parameters to be used in this work a12 b22 2 a11 b12 b21 a a b b b
s3 þ s þ s þ 11 13 11 12 23 ¼ 0 ð8Þ
(Tables 1 and 2). However, their effect on the proposed R2 C1 R 1 R 2 C1 C2 R1 R2 R3 C1 C2 C3

Figure 4 Voltage and current outputs of Fig. 2 at 795 kHz

Figure 5 Fourier spectrum of the outputs of Fig. 4

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The FO and CO get modified as

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1 a11 a13 b11 b12 b23
FO : fo ¼ ;
2p a12 b22 R1 R3 C2 C3 ð9Þ
CO : a13 b11 b23 R2 C1 ¼ a12 b21 b22 R3 C3

Here, a1j is the current transfer gain from X to Zþ terminal

of jth DVCC. Similarly, b1j is the voltage transfer gain from
Y1 terminal to X terminal of jth DVCC; and b2j is the
voltage transfer gain from Y2 terminal to X terminal of jth
DVCC. Equation (8) shows that the sensitivity of FO to
various transfer gains as well as to passive components is
within 0.5 in magnitude, which is a good sensitivity
figure. For simplicity, if all voltage transfer gains are Figure 6 Frequency tuning with R1
identical; and current transfer gains also same for all
DVCCs, then only three factors (one a and two b)
remain in FO’s numerator (others cancel with those
present in denominator). On the other hand, CO
expression gets rid of ‘transfer gains’, with a similar
reasoning. FO would be expected to show slight deviation
because of the presence of transfer gains, but the CO
actually is not quite adversely affected.

The sensitivity of oscillator’s FO to active and passive

elements are also analysed and given as

1   1
FO  FO  (10)
SR1,R3,C2,C3 ¼ ; Sa11,a13,a12,b11,b12,b23,b22  ¼
2 2

Equation (10) shows that the sensitivity figures are within 0.5
Figure 7 Phase error (between V1 and V2) as a function of FO
in magnitude, ensuring good sensitivity performance.

6 Simulation results
The proposed third-order quadrature oscillator was next
simulated using PSPICE, an industry standard tool for
evaluating the performance of circuits. The DVCC
implementation of Fig. 1 was used with MIETEC 0.5 m
CMOS parameters and aspect ratio as listed in Tables 2
and 3. The circuit was designed using equal capacitors of
value 100 pF, R1 ¼ R3 ¼ 2 kV and R2 ¼ 1.8 kV (to obtain
sustained oscillations). The theoretical FO using this
design was 796 kHz. The simulated FO was found to be
795 kHz, which is very close to the theoretical value and
only 0.1% in error. The results for the five voltage outputs
and two current outputs are shown in Fig. 4. The Fourier
spectrum of the outputs of Fig. 4 are shown in Fig. 5, each
output enjoying a total harmonic distortion (THD) of less
than 1%. A low THD along with good accuracy of the FO
is a justifying feature for the third-order oscillator [7]. To
further support the circuit’s practical utility, R1 was varied Figure 8 X–Y plot showing quadrature current property
so as to vary the FO. The FO tuning through R1 is shown
in Fig. 6. Both theoretical and simulated FO is found to outputs, namely, V1 and V2 was further measured through
closely match; the discrepancy (deficit) in simulated simulations (output file of Fourier analysis) and the error
frequency being the result of various parasitics discussed in calculated. The results are shown in Fig. 7, which show
Sections 4 and 5. The phase of two of the quadrature little phase error (deviation from 90º phase shift). The

158 IET Circuits Devices Syst., 2009, Vol. 3, Iss. 4, pp. 153– 160
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quadrature relationship is further verified through the X – Y
plot (circle) of the two current outputs as shown in Fig. 8.
7 Conclusion
A new third-order quadrature oscillator circuit based on
DVCC and grounded passive component is presented. The
circuit provides a number of quadrature voltages and
current outputs. Frequency of the oscillator can be varied
independent of (without affecting) the CO. Non-ideality
aspects and parasitic effects are also studied. Another new
resistor-less circuit can be derived from the proposed
oscillator, with the added advantage of limited electronic
control. The proposed circuit is verified through PSPICE
simulations with promising results. The active-C oscillator
derived from the proposed active-RC oscillator is a topic of
further investigation using voltage-controlled DVCC with
better Rx linearity.
8 Acknowledgments
The author is thankful to the anonymous reviewers for useful
comments that helped to improve the paper presentations.
The author is also grateful to the Editor, Prof. Asim Ray,
for enabling timely review and his recommendation.
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