LG KT610 Service Manual PDF

Service Manual
Internal Use Only
Service Manual
KT610
Model : KT610
Date: June, 2008 / Issue 1.0

Table Of Contents
1. INTRODUCTION .............................. 5 4.5 Checking WCDMA Block .......................95
1.1 Purpose................................................... 5 4.6 Checking GSM Block ...........................106
1.2 Regulatory Information............................ 5 4.7 Power on trouble..................................113
4.8 USB trouble..........................................115
2. PERFORMANCE...............................7 4.9 SIM detect trouble................................116
4.10 Key sense trouble ..............................117
2.1 System Overview .....................................7
4.11 Keypad backlight trouble....................119
2.2 Usable environment .................................8
4.12 Folder on/off trouble...........................121
2.3 Radio Performance ..................................9
4.13 Micro SD trouble ................................123
2.4 Current Consumption.............................16
4.14 Charging trouble ................................125
2.5 RSSI BAR ..............................................16
4.15 Audio trouble......................................127
2.6 Battery BAR ...........................................16
4.16 Camera trouble ..................................140
2.7 Sound Pressure Level............................17
4.17 Main LCD trouble ...............................146
2.8 Charging ................................................18
4.18 Bluetooth trouble................................149
3. TECHNICAL BRIEF ........................19
5. DOWNLOAD .................................151
3.1 GENERAL DESCRIPTION ....................19
5.1 COM PORT setting method when
3.2 GSM MODE ...........................................21
using USB Download ...........................151
3.3 UMTS MODE .........................................24
5.2 How to KT610 Download .....................154
3.4 GPS MODE............................................27
3.5 LO GENERATION and 6. BLOCK DIAGRAM ........................157
DISTRIBUTION CIRCUIT ......................28
3.6 OFF-CHIP RF COMPONENTS .............29
3.7 Digital Baseband
7. CIRCUIT DIAGRAM ......................165
(Stn8810 / MSM6280)............................32
3.8 Hardware Architecture ...........................34 8. BGA IC PIN CHECK......................177
3.9 Subsystem of STn8810..........................37
3.10 Hardware Peripheral system of 9. PCB LAYOUT ................................187
Stn8810................................................40
3.11 Subsystem of MSM6280......................46 10. CALIBRATION & RF AUTO TEST
3.12 External memory interface ...................48 (HOT KIMCHI) .............................195
3.13 Hardware sub system of MSM6280.....50
10.1 Usage of Hot-Kimchi ..........................195
3.14 Audio and sound ..................................62
3.15 Camera interface .................................69 11. TEST MODE ................................198
3.16 Bluetooth..............................................77
3.17 Main Features ......................................78
12. EXPLODED VIEW &
3.18 Main Component..................................79
REPLACEMENT PART LIST ......201
12.1 EXPLODED VIEW .............................201
4. TROUBLE SHOOTING ...................86
12.2 Replacement Parts
4.1 RF Component.......................................86 <Mechanic component>.....................207
4.2 SIGNAL PATH .......................................88 <Main component> ............................211
4.3 Checking TCXO Block ...........................91 12.3 Accessory ..........................................233
4.4 Checking Ant. Switch Module Block ......93
Copyright © 2008 LG Electronics. Inc. All right reserved. -3- LGE Internal Use Only
Only for training and service purposes
LGE Internal Use Only -4- Copyright © 2008 LG Electronics. Inc. All right reserved.
1. INTRODUCTION
1. INTRODUCTION
1.1 Purpose
This manual provides the information necessary to repair, calibration, description and download the
features of this model.
1.2 Regulatory Information
A. Security
Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example,
persons other than your company’s employees, agents, subcontractors, or person working on your
company’s behalf) can result in substantial additional charges for your telecommunications services.
System users are responsible for the security of own system. There are may be risks of toll fraud
associated with your telecommunications system. System users are responsible for programming and
configuring the equipment to prevent unauthorized use. The manufacturer does not warrant that this
product is immune from the above case but will prevent unauthorized use of common-carrier
telecommunication service of facilities accessed through or connected to it. The manufacturer will not
be responsible for any charges that result from such unauthorized use.
B. Incidence of Harm
If a telephone company determines that the equipment provided to customer is faulty and possibly
causing harm or interruption in service to the telephone network, it should disconnect telephone
service until repair can be done. A telephone company may temporarily disconnect service as long as
repair is not done.
C. Changes in Service
A local telephone company may make changes in its communications facilities or procedure. If these
changes could reasonably be expected to affect the use of the phones or compatibility with the net
work, the telephone company is required to give advanced written notice to the user, allowing the user
to take appropriate steps to maintain telephone service.
D. Maintenance Limitations
Maintenance limitations on the phones must be performed only by the manufacturer or its authorized
agent. The user may not make any changes and/or repairs expect as specifically noted in this manual.
Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system
and may void any remaining warranty.
1. INTRODUCTION
E. Notice of Radiated Emissions

This model complies with rules regarding radiation and radio frequency emission as defined by local
regulatory agencies. In accordance with these agencies, you may be required to provide information
such as the following to the end user.
F. Pictures
The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly
different.
G. Interference and Attenuation

A phone may interfere with sensitive laboratory equipment, medical equipment, etc. Interference from
unsuppressed engines or electric motors may cause problems.
H. Electrostatic Sensitive Devices
ATTENTION
Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the sign.
Following information is ESD handling:
• Service personnel should ground themselves by using a wrist strap when exchange system boards.
• When repairs are made to a system board, they should spread the floor with anti-static mat which is
also grounded.
• Use a suitable, grounded soldering iron.
• Keep sensitive parts in these protective packages until these are used.
• When returning system boards or parts like EEPROM to the factory, use the protective package as
described.
2. PERFORMANCE
2. PERFORMANCE
2.1 System Overview
Item Specification
Shape GSM900/1800/1900 and WCDMA Communicator Handset
Size 108.9 X 53.9 X 17.2 mm
Weight 124 g (with 950mAh Battery)
Power 3.7V normal, 950 mAh Li-Polymer
Talk Time Over 170 min (TX = 12dBm,Low Power mode)

(with 950mAh) Over 180 min (TX Level = Max)
Standby Time Over 220 hours (DRX = 1.28)

(with 950mAh) Over 290 hours (Paging Period = 5)
Antenna Internal type and Antenna
LCD TFT LCD ( Main : 2.4’, 320 x 240, Sub :1.45” 160X64 )
LCD Backlight LED Back Light (Main, Sub)
Camera Dual Camera ; 2 Mega pixel (CMOS), VGA Camera (CMOS)
Vibrator Yes (Cylinder Type)
LED Indicator No
MIC Yes
Receiver Yes
Earphone Jack Yes
Connectivity Bluetooth, USB
Volume Key Push Type (+, -)
External Memory Micro-SD
I/O Connect 18 Pin
2. PERFORMANCE
2.2 Usable environment
2.2.1 Environment
Item Specification
Voltage 3.7 V(Typ), [Shut Down : 3.22 V]
Operation Temp -20 ~ +60 °C
Storage Temp -20 ~ +70 °C
Humidity 85 % (Max)
2.2.2 Environment (Accessory)

Reference Spec. Min Typ. Max Unit
TA Power Available power 100 220 240 Vac

* CLA : 12~24V(DC).
2. PERFORMANCE
2.3 Radio Performance
2.3.1 Transmitter - GSM Mode
No Item GSM DCS & PCS
1 Conducted MS allocated 100k~1GHz -39dBm 9k ~ 1GHz -39dBm
Spurious Channel 1G~[A]MHz -33dBm
Emission 1G~12.75GHz -33dBm [A]M~[B]MHz -39dBm
[B]M~12.75GHz -33dBm
Idle Mode 100k~880MHz -60dBm 100k~880MHz -60dBm
880M~915MHz -62dBm 880M~915MHz -62dBm
915M~1GHz -60dBm 915M~1GHz -60dBm
1G~[A]MHz -50dBm 1G~[A]MHz -50dBm
[A]M~[B]MHz -56dBm [A]M~[B]MHz -56dBm
[B]M~12.5GHz -50dBm [B]M~12.5GHz -50dBm
2 Radiated MS allocated 30M ~ 1GHz -36dBm 30M~1GHz 36dBm
Spurious Channel 1G~[A]MHz -30dBm
Emission 1G ~ 4GHz -30dBm [A]M~[B]MHz -36dBm

[B]M~4GHz -30dBm
Idle Mode 30M ~ 880MHz -57dBm 30M~880MHz -57dBm
880M ~ 915MHz -59dBm 880M~915MHz -59dBm
915M~1GHz -57dBm 915M~1GHz -57dBm
1G~[A]MHz -47dBm 1G~[A]MHz -47dBm
[A]M~[B]MHz -53dBm [A]M~[B]MHz -53dBm
[B]M~4GHz -47dBm [B]M~4GHz -47dBm
* In case of DCS : [A] -> 1710, [B] -> 1785* In case of PCS : [A] -> 1850, [B] -> 1910
2. PERFORMANCE
3 Frequency Error ± 0.1ppm ± 0.1ppm
4 Phase Error ± 5(RMS) ± 5(RMS)
± 20(PEAK) ± 20(PEAK)
5 Frequency Error 3dB below reference sensitivity 3dB below reference sensitivity
Under Multipath and RA250 : ± 200Hz RA250: ± 250Hz
Interference Condition HT100 : ± 100Hz HT100: ± 250Hz
TU50 : ± 100Hz TU50: ± 150Hz
TU3 : ± 150Hz TU1.5: ± 200Hz
6 Output RF Due to 0 ~ 100kHz +0.5dB 0 ~ 100kHz +0.5dB
Spectrum modulation 200kHz -30dB 200kHz -30dB
250kHz -33dB 250kHz -33dB
400kHz -60dB 400kHz -60dB
600 ~ 1800kHz -60dB 600 ~ 1800kHz -60dB
1800 ~ 3000kHz -63dB 1800 ~ 6000kHz -65dB
3000 ~ 6000kHz -65dB ≥ 6000kHz -73dB
≥ 6000kHz -71dB
Due to 400kHz -19dB 400kHz -22dB
Switching 600kHz -21dB 600kHz -24dB
transient 1200kHz -21dB 1200kHz -24dB
1800kHz -24dB 1800kHz -27dB
7 Intermodulation attenuation - Frequency offset 800kHz
Intermodulation product should
be Less than 55dB below the
level of Wanted signal
* In case of DCS : [A] -> 1710, [B] -> 1785* In case of PCS : [A] -> 1850, [B] -> 1910
LGE Internal Use Only - 10 - Copyright © 2008 LG Electronics. Inc. All right reserved.
2. PERFORMANCE
8 Transmitter Output Power Level Power Toler. Level Power Toler.
5 33 ±3 0 30 ±3
6 31 ±3 1 28 ±3
7 29 ±3 2 26 ±3
8 27 ±3 3 24 ±3
9 25 ±3 4 22 ±3
10 23 ±3 5 20 ±3
11 21 ±3 6 18 ±3
12 19 ±3 7 16 ±3
13 17 ±3 8 14 ±3
14 15 ±3 9 12 ±4
15 13 ±3 10 10 ±4
16 11 ±5 11 8 ±4
17 9 ±5 12 6 ±4
18 7 ±5 13 4 ±4
19 5 ±5 14 2 ±5
15 0 ±5
9 Burst timing Mask IN Mask IN
Copyright © 2008 LG Electronics. Inc. All right reserved. - 11 - LGE Internal Use Only
2. PERFORMANCE
2.3.2 Transmitter - WCDMA Mode
No Item Specification
1 Maximum Output Power Class3: +24dBm(+1/-3dB)

Class 4 : +21dBm( ± 2dB)
2 Frequency Error ± 0.1ppm
3 Open Loop Power control in uplink ± 9dB@normal, ± 12dB@extreme
4 Inner Loop Power control in uplink Adjust output(TPC command)
cmd 1dB 2dB 3dB

+1 +0.5/1.5 +1/3 +1.5/4.5
0 -0.5/+0.5 -0.5/+0.5 -0.5/+0.5
-1 -0.5/-1.5 -1/-3 -1.5/-4.5
Group (10 equel command group)
+1 +8/+12 +16/+24
5 Out-band Blocking -50dBm(3.84MHz)
6 Out-of-synchronization handling of output power Qin/Qout : PCCH quality levels

Toff@DPCCH/Ior : -22 -> -28dB
Ton@DPCCH/Ior : -24 -> -18dB
7 Transmit OFF Power -56dBm(3.84MHz)
8 Transmit ON/OFF Time Mask ± 25us

PRACH,CPCH,uplinlk compressed mode
9 Change of TFC ± 25us

Power varies according to the data rate DTX :
DPCH off (minimize interference between UE)
10 Power setting in uplink compressed ± 3dB(after 14slots transmission gap)

11 Occupied Bandwidth(OBW) 5MHz(99%)
12 Spectrum emission Mask -35-15*(∆f-2.5)dBc@∆f=2.5~3.5MHz,30k

-35-1*(∆f-3.5)dBc@∆f=3.5~7.5MHz,1M -39-
10*(∆f-7.5)dBc@∆f=7.5~8.5MHz,1M
-49dBc@∆f=8.5~12.5MHz,1M
13 Adjacent Channel Leakage Ratio(ACLR) 33dB@5MHz, ACP>-50dBm

43dB@10MHz, ACP>-50dBm
2. PERFORMANCE
14 Spurious Emissions (*: additional requirement) -36dBm@f=9~150KHz, 1K BW
-36dBm@f=50KHz~30MHz, 10K BW
-36dBm@f=30MHz~1000MHz, 100K BW
-30dBm@f=1~12.5GHz, 1M BW
(*)-41dBm@f=1893.5~1919.6MHz, 300K
(*)-67dBm@f=925~935MHz, 100K BW
(*)-79dBm@f=935~960MHz, 100K BW
(*)-71dBm@f=1805~1880MHz, 100K BW
15 Transmit Intermodulation -31dBc@5MHz,Interferer -40dBc
-41dBc@10MHz, Interferer -40dBc
16 Error Vector Magnitude (EVM) 17.5%(>-20dBm)
(@12.2K, 1DPDCH+1DPCCH)
17 Transmit OFF Power -15dB@SF=4.768Kbps, Multi-code
transmission
2. PERFORMANCE
2.3.3 Receiver - GSM Mode
1 Sensitivity (TCH/FS Class II) -105dBm -105dBm
2 Co-Channel Rejection (TCH/FS C/Ic=7dB Storage -30 ~ +85
Class II, RBER, TU high/FH)
3 Adjacent 200kHz C/Ia1=-12dB C/Ia1=-12dB
Channel
Rejection 400kHz C/Ia2=-44dB C/Ia2=-44dB
4 Intermodulation Rejection Wanted Signal :-98dBm Wanted Signal :-96dBm
1st interferer :-44dBm 1st interferer :-44dBm

2nd interferer :-45dBm 2nd interferer :-44dBm
5 Blocking Response Wanted Signal :-101dBm Wanted Signal :-101dBm
(TCH/FS Class , RBER) Unwanted : Depend on Unwanted : Depend on
Frequency Frequency
2. PERFORMANCE
2.3.4 Receiver - WCDMA Mode
1 Reference Sensitivity Level -106.7 dBm(3.84 MHz)
2 Maximum Input Level -25dBm(3.84MHz)
-44dBm/3.84MHz(DPCH_Ec)
UE@+20dBm output power(Class3)
3 Adjacent Channel Selectivity (ACS) 33dB
4 In-band Blocking -56dBm/3.84MHz@10MHz
-44dBm/3.84MHz@15MHz
5 Out-band Blocking -44dBm/3.84MHz@f=2050~2095 and
2185~2230MHz
-30dBm/3.84MHz@f=2025~2050 and
2230~2255MHz
-15dBm/3.84MHz@f=1~2025 and
2255~12500MHz
6 Spurious Response -44dBm CW
7 Intermodulation Characteristic -46dBm CW@10MHz
-46dBm/3.84MHz@20MHz
8 Spurious Emissions -57dBm@f=9KHz~1GHz, 100K BW
-47dBm@f=1~12.5GHz, 1M BW
-60dBm@f=1850 MHz ≤ f ≤ 1910 MHz,
3.84M BW
-60dBm@f=824 MHz ≤ f ≤ 849 MHz, 3.84M BW
2. PERFORMANCE
2.4 Current Consumption

Stand by(BT Off condition) Voice Call VT
WCDMA Under 4.32 mA Under 335 mA Under 569mA

(DRX=1.28) (Tx=10dBm) (Tx=10dBm
-Low power) -Low power)
GSM Under 4.32 mA Under 380 mA

(Paging=5period) (Tx=Max power)
(Stand by and Voice Call Test Condition : LCD backlight Off)

(VT Test Condition : Speaker off, LCD backlight On,0dBm Tx power)
2.5 RSSI BAR

Level Change CDMA GSM
7→6 -86 ± 2dBm -82 ± 2dBm
6→5 -90 ± 2dBm -86 ± 2dBm
5→4 -94 ± 2dBm -90 ± 2dBm
4→3 -98 ± 2dBm -94 ± 2dBm
3→2 -102 ± 2dBm -98 ± 2dBm
2→1 -106 ± 2dBm -102 ± 2dBm
1→0 -110 ± 2dBm -106 ± 2dBm
2.6 Battery BAR

Indication Standby
Bar 7 3.96 ± 0.05V
Bar 7 → 6 3.95 ± 0.05V
Bar 6 → 5 3.86 ± 0.05V
Bar 5 → 4 3.78 ± 0.05V
Bar 4 → 3 3.74 ± 0.05V
Bar 3 → 2 3.69 ± 0.05V
Bar 2 → 1 3.63 ± 0.05V
Bar 1 → Empty 3.50 ± 0.05V
Low Voltage, 3.63,3.50 ± 0.05V (Stand-by) / 3.63, 3.50 ± 0.05V (Talk)
Warning message + tone Bar 2 → 1 / Bar 1 → Empty
Power Off 3.20 ± 0.05V
2. PERFORMANCE
2.7 Sound Pressure Level
No Test Item Specification

1 Sending Loudness Rating (SLR) 8 ± 3 dB
2 Receiving Loudness Rating (RLR) Nor -4 ± 3 dB
Max -15 ± 3 dB
3 Side Tone Masking Rating (STMR) Min 17 dB
4 Echo Loss (EL) Min 40 dB
MS
5 Sending Distortion (SD) Refer to Table 30.3
6 Receiving Distortion (RD) Refer to Table 30.4
7 Idle Noise-Sending (INS) Max -64 dBm0p
8 Idle Noise-Receiving (INR) Nor Under -47 dBPA
Max Under -36 dBPA
9 Sending Loudness Rating (SLR) 8 ± 3 dB
10 Receiving Loudness Rating (RLR) Nor -1 ± 3 dB
Max -12 ± 3 dB
11 Side Tone Masking Rating (STMR) Min 25 dB
12 Echo Loss (EL) Min 40 dB
Headset
13 Sending Distortion (SD) Refer to Table 30.3
14 Receiving Distortion (RD) Refer to Table 30.4
15 Idle Noise-Sending (INS) Max -55 dBm0p
16 Idle Noise-Receiving (INR) 16 Nor Under -45 dBPA
Max Under -40 dBPA
17 TDMA Noise Max -62 dBm
-. GSM : Power Level : 5
DCS/PCS : Power Level : 0
(Cell Power : -90 ~ -105 dBm) MS and
-. Acoustic (Max Vol.) Headset
MS/Headset SLR : 8 ± 3dB
MS/Headset RLR : -15 ± 3dB / -12dB
(SLR/RLR : Mid-value setting)
2. PERFORMANCE
2.8 Charging
• Charging Method : CC & CV (Constant Current & Constant Voltage)
• Maximum Charging Voltage : 4.2 V
• Maximum Charging Current : 650mA
• Normal Battery Capacity : 950 mAh
• Charger Voltage : 4.8V
• Charging Time : Max 3 h (Except time trickle charging)
• Full charging indication current (charging icon stop current) : 60mA
• Low battery POP UP : 3.48V
• Low battery alarm interval : Idle - 3 min, Dedicated - 1min
• Cut-off voltage : 3.22V
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.1 GENERAL DESCRIPTION

The KT610 supports UMTS-2100, GSM-900, GSM-1800, and GSM-1900 based
GSM/GPRS/EDGE/UMTS. All receivers and the UMTS transmitter use the radioOne 1 Zero-IF
architecture to eliminate intermediate frequencies, directly converting signals between RF and
baseband. The quad-band GSM transmitters use a baseband-to-IF upconversion followed by an offset
phase-locked loop that translates the GMSK-modulated or 8-PSK-modulated signal to RF.
[Fig. 3.1] Block diagram of RF part
A generic, high-level functional block diagram of KT610 is shown in Figure 3-1. One antenna collects
base station forward link signals and radiates handset reverse link signals. The antenna connects with
receive and transmit paths through a SKY77519(EDGE PAM+ASM). The UMTS receive paths each
include an LNA, an RF band-pass filter, and a downconverter that translate the signal directly from RF-
to-baseband using radioOne ZIF techniques.
The RFIC’s Rx analog baseband outputs, for the receive chains, connect to the MSM IC. The UMTS
and GSM Rx baseband outputs share the same inputs to the MSM IC.
1
QUALCOMM’s branded chipset that implements a Zero-IF radio architecture.
3. TECHNICAL BRIEF
For the transmit chains, the RTR6285 IC directly translates the Tx baseband signals (from the MSM
device) to an RF signal using an internal LO generated by integrated on-chip PLL and VCO. The
RTR6285 IC outputs deliver fairly high-level RF signals that are first filtered by Tx SAWs and then
amplified by their respective UMTS PAs.
In the GSM receive path, the received RF signals are applied through their bandpass filters and down-
converted directly to baseband in the RTR6285 transceiver IC.
These baseband outputs are shared with the UMTS receiver and routed to the MSM IC for further
signal processing.
The GSM/EDGE transmit path employs one stage of up-conversion and, in order to improve efficiency,
is divided into phase and amplitude components to produce an open-loop Polar topology:
1. The on-chip quadrature up-converter translates the GMSK-modulated signal or 8- PSK modulated
signal, to a constant envelope phase signal at RF;
2. The amplitude-modulated (AM) component is applied to the ramping control pin of Polar power
amplifier from a DAC within the MSM
KT610 power supply voltages are managed and regulated by the PM6658 Power Management IC.
This versatile device integrates all wireless handset power management, general housekeeping, and
user interface support functions into a single mixed signal IC. It monitors and controls the external
power source and coordinates battery recharging while maintaining the handset supply voltages using
low dropout, programmable regulators.
The device’s general housekeeping functions include an ADC and analog multiplexer circuit for
monitoring on-chip voltage sources, charging status, and current flow, as well as user-defined off-chip
variables such as temperature, RF output power, and battery ID. Various oscillator, clock, and counter
circuits support IC and higher-level handset functions. Key parameters such as under-voltage lockout
and crystal oscillator signal presence are monitored to protect against detrimental conditions.
3. TECHNICAL BRIEF
3.2 GSM MODE
3.2.1 GSM RECEIVER

The GSM-900, GSM-1800, and GSM-1900 receiver inputs of RTR6285 are connected directly to the
transceiver front-end circuits(filters and antenna switch module). GSM-900, GSM-1800, and GSM-
1900 receiver inputs use differential configurations to improve common-mode rejection and second-
order non-linearity performance as shown in Figure 3-2. The balance between the complementary
signals is critical and must be maintained from the RF filter outputs all the way into the IC pins
[Figure 3-2] GSM Receiver Inputs Topologies
3. TECHNICAL BRIEF
Since GSM-900, GSM-1800, and GSM-1900 signals are time-division duplex (the handset can only
receive or transmit at one time), switches are used to separate Rx and Tx signals in place of frequency
duplexers - this is accomplished in the switch module. The GSM-900, GSM-1800, and GSM-1900
receive signals are routed to the RTR6285 through band selection filters and matching networks that
transform singleended 50-Ω sources to differential impedances optimized for gain and noise figure.
The RTR input uses a differential configuration to improve second-order intermodulation and common
mode rejection performance. The RTR6285 input stages include MSM-controlled gain adjustments that
maximize receiver dynamic range.
The amplifier outputs drive the RF ports of the quadrature RF-to-baseband downconverters. The
downconverted baseband outputs are multiplexed and routed to lowpass filters (one I and one Q)
having passband and stopband characteristics suitable for GMSK or 8-PSK processing. These filter
circuits include DC offset corrections. The filter outputs are buffered and passed on to the MSM6280 IC
for further processing as shown in Figure 3-4.
3. TECHNICAL BRIEF
3.2.2 GSM TRANSMITTER

The RTR6285 transmitter outputs(HB_RF_OUT1 and LB_RF_OUT1) include on-chip output matching
inductors. 50ohm output impedance is achieved by adding a series capacitor at the output pins. The
capacitor value may be optimized for specific applications and PCB characteristics based on pass-band
symmetry about the band center frequency as shown in Figure 3-3.
[Figure 3-3] GSM Transmitter Outputs Topologies
The RTR6285 IC is able to support GSM 900 and GSM 1800/1900 mode transmitting.
This design guideline shows a tri-band GSM application. Both high-band and low band outputs are
followed by resistive pads to ensure that the load presented to the outputs remains close to 50ohm.
3. TECHNICAL BRIEF
3.3 UMTS MODE
3.3.1 UMTS RECEIVER

The UMTS duplexer receiver output is routed to LNA circuits within the RTR6285 device as shown in
Figure 3-4. The UMTS Rx input is provided with an on-chip LNA that amplifies the signal before a
second stage filter that provides differential downconverter as shown in Figure 3-5. This second stage
input is configured differentially to optimize second-order intermodulation and common mode rejection
performance. The gain of the UMTS frontend amplifier and the UMTS second stage differential amplifier
are adjustable, under MSM control, to extend the dynamic range of the receivers. The second stage
UMTS Rx amplifiers drive the RF ports of the quadrature RF-to-baseband downconverters. The
downconverted UMTS Rx baseband outputs are routed to lowpass filters having passband and
stopband characteristics suitable for UMTS Rx processing. These filter circuits allow DC offset
corrections, and their differential outputs are buffered to interface shared with GSM Rx to the MSM IC.
The UMTS baseband outputs are turned off when the RTR6285 is downconverting GSM signals and on
when the UMTS is operating.
[Figure 3-4] UMTS Receiver Inputs Topologies
3. TECHNICAL BRIEF
3.3.2 UMTS TRANSMITTER

The UMTS Tx path begins with differential baseband signals (I and Q) from the MSM device.
These analog input signals are amplified, filtered, and applied to the quadrature upconverter mixers.
The up-converter output is amplified by multiple variable gain stages that provide transmit AGC control.
The AGC output is filtered and applied to the driver amplifier; this output stage includes an integrated
matching inductor that simplifies the external matching network to a single series capacitor to achieve
the desired 50-Ω interface.
The RTR6285 UMTS output is routed to its power amplifier through a bandpass filter, and delivers fairly
high-level signals that are filtered and applied to the PA. Transmit power is delivered from the duplexer
to the antenna through the switch module.
The transceiver LO synthesizer is contained within the RTR6285 IC with the exception of the off-chip
loop filter components and the VC-TCXO. This provides a simplified design for multimode applications.
The PLL circuits include a reference divider, phase detector, charge pump, feedback divider, and digital
logic generator.
UMTS Tx. Using only PLL1, the LO generation and distribution circuits create the necessary LO signals
for nine different frequency converters. The UMTS transmitter also employs the ZIF architecture to
translate the signal directly from baseband to RF.
This requires FLO to equal FRF, and the RTR6285 IC design achieves this without allowing FVCO to
equal FRF.
The RTR6285 IC is able to support UMTS 2100/1900/1800/1700 and 850 mode transmitting. This
design guideline shows only UMTS 2100 applications.
3. TECHNICAL BRIEF
WCDMA_2100_TX
WCDMA_2100_RX
[Figure 3.5] RTR6285 IC Functional Block Diagram
3. TECHNICAL BRIEF
3.4 GPS MODE
3.4.1 GPS RECEIVER

The GPS receicer input employs a single-ended connection realized by this pin. The GPS input is
routed from the GPS antenna switch, through a bandpass filter and then an impedance transformer
circuit that optimally matches the impedance looking into the GPS LNA. The impedance transformer
circuit topology is shown in Figure 3-6.
[Figure 3.6] GPS Input Network Topology
3. TECHNICAL BRIEF
3.5 LO GENERATION and DISTRIBUTION CIRCUIT

The integrated LO generation and distribution circuits are driven by internal VCOs to support various
modes to yield highly flexible quadrature LO outputs that drive all GSM/EDGE, UMTS band and GPS
upconverters and downconverters; with the help of these LO generation and distribution circuits, true
zero-IF architecture is employed in all GSM and UMTS band receivers and transmitters to translate the
signal directly from RF-to-baseband and from baseband-to-RF. Two fully functional fraction-N
synthesizers, including VCOs and loop filters, are integrated within the RTR6285 IC. In addition, the
RTR6285 has a third synthesizer used for GPS operation. The first synthesizer (PLL1) in the RTR6285
creates the transceiver Los that support the UMTS transmitter, and all four GSM band receivers and
transmitters including:
GSM850, GSM900, GSM1800, and GSM1900. The second synthesizer (PLL2) in the RTR6285 IC
provides the LO for the UMTS primary receiver. For the RTR6285 IC only, the second synthesizer also
provides the LO for the secondary UMTS receiver.
The third synthesizer (PLL3), only in the RTR6285 IC, provides the LO for the GPS receiver. An
external TCXO input signal is required to provide the synthesizer frequency reference to which the PLL
is phase and frequency locked. The RTR6285 ICs integrate most of the PLL loop filter components on-
chip except for three off-chip loop filter-series capacitors, which significantly reduces off-chip
component requirement. With the integrated fractional-N PLL synthesizers, the RTR6285 ICs have the
advantage of more flexible loop bandwidth control, fast lock time, and lowintegrated phase error.
3. TECHNICAL BRIEF
3.6 OFF-CHIP RF COMPONENTS
3.6.1 ALM-1412(U603:GPS LNA)

The ALM-1412 is an LNA module, with integrated filter, designed for GPS band applications at
1.575GHz. The LNA uses AVAGO Technologies’ proprietary GaAs Enhancement-mode pHEMT
process to achieve high gain with very low noise figure and high linearity Noise figure distribution is very
tightly controlled. A CMOScompatible shutdown pin is included either for turning the LNA on/off, or for
current adjustment. The integrated filter utilizes an Avago Technologies’ leading edge FBAR filter for
exceptional rejection at Cell/PCS Band frequencies. The ALM-1412 is useable down to 1V operation. It
achieves low noise figure, high gain and linearity even at 1V, making it suitable for use in critical low-
power GPS applications or during low-battery situations.
3.6.2 SKY77519(U601:GSM FEM)

RF Front end consists of antenna, antenna switch module (SKY77519) which includes EDGE PAM.
The antenna switch module allows multiple operating bands and modes to share the same antenna. In
KT610, a common antenna connects to one of six paths: 1) UMTS-2100 Rx/Tx, 2) GSM-900 Rx, 3)
GSM-900 Tx, 4) GSM- 1800 Rx, and 5) GSM-1800, GSM-1900 Tx(High Band Tx’s share the same
path), 6) GSM-1900 Rx. UMTS operation requires simultaneous reception and transmission, so the
UMTS Rx/Tx connection is routed to a duplexer that separates receive and transmit signals. GSM-900,
GSM-1800, and GSM-1900 operation is time division duplexed, so only the receiver or transmitter is
active at any time and a frequency duplexer is not required. The active connection is MSM-selected by
three control lines (GPIO[9], GPIO[10] and GPIO[11]). These GPIOs are programmed to be ANT_SEL0
, ANT_SEL1 and ANT_SEL2 respectively.
3. TECHNICAL BRIEF
TXEN BS1 BS2
GSM 900 TX LOW LOW HIGH
GSM 1800/GSM 1900 TX LOW HIGH HIGH
GSM 900 RX HIGH HIGH LOW
GSM 1800 RX HIGH HIGH HIGH
GSM 1900 RX HIGH LOW HIGH
WCDMA LOW HIGH LOW
Table 1. Antenna Switch Module Logic
[Figure 3.5] SKY77519 Functional Block Diagram.
3. TECHNICAL BRIEF
3.6.3 W-CDMA POWER AMPLIFIER (U604: ACPM-7381)

The ACPM-7381, a Wide-band Code Division Multiple Access(WCDMA) Power Amplifier(PA), is a fully
matched 10-pin surface mount module developed for WCDMA handset applications. This power
amplifier module is developed to cover 1920- 1980MHz bandwidth. The ACPM-7381 meets the
stringent WCDMA linearity requirements for output power of up to 28dBm. The ACPM-7381 is also
developed to meet HSDPA specs.
The ACPM-7381 is designed to enhance the efficiency at low and medium output power range by using
3-mode control scheme with 2 mode control pins. This provides extended talk time. The ACPM-7381 is
self contained, incorporating 50ohm input and output matching networks.
[Figure 3.6] ACPM-7381 Functional Block Diagram.
3.6.4 W-CDMA DUPLXER (FL605: ACMD-7602)

The ACMD-7602 is a miniature duplexer designed for use in UMTS Band I handsets and enhances the
sensitivity and dynamic range of WCDMA receivers by providing more than 53dB attenuation of the
transmitted signal at the receiver input and more than 43dB rejection of transmit-generated noise in the
receiver band. The ACMD-7602 is designed with FBAR technology, which makes possible ultra-small,
high-Q filters at a fraction of their usual size. The excellent power handling capability of the FBAR bulk-
mode resonators supports the high output power levels needed in handsets while adding virtually no
distortion.
3. TECHNICAL BRIEF
3.7 Digital Baseband (Stn8810 / MSM6280)
3.7.1 General features of Stn8810 device

■ Support for Peripheral Device & multimedia function
■ Minimal support for high-level operating system such as Symbian™, Linux and WinCE® operating
systems (OSs).
■ 1-Gbit NAND Flash memory, 512-Mbit DDR mobile RAM Stacked in Package
■ Two DSP implementation for multimedia function
- Smart video accelerator : Programmable DSP (MMDSP+) for intermediate level processing,
clocked at 66 MHz,
- Smart audio accelerator : High-performance block, flexible sophisticated audio accelerator based
on the MMDSP+ programmable audio DSP, clocked at 133 MHz,
■ ARM926EJ 32-bit RISC CPU at 350MHz
- 32-Kbyte instruction cache, 16-Kbyte data cache
■ MultiMedia Card/SD Card/SDIO host controller
■ 96 general-purpose I/Os (muxed with peripheral I/Os)
■ amera interfaces
- Supports high-resolution camera modules up to 4 Mpixels
- Serial camera interface up to 416 Mbit/s (MIPI legacy CSI)
- Parallel camera CCIR-656 interface up to 66 MHz (MIPI legacy CPI)
■ Color LCD controller for STN or TFT panels or display interface for display module
- 24-bpp true color
- MIPI legacy DBI and DPI
■ Host port interface (HPI)
- 16-bit parallel data bus,
- Multiplexed and non-multiplexed address/data bus,
- Indirect host access,
- Direct host access to a segment of STn8810 memory in multiplexed mode.
- Interface to modem for data communication
■ I/O peripherals
- 3 autobaud UARTs (one with modem control signals) up to 3.692 Mbit/s
- 1 synchronous serial port (SSP) up to 24 Mbit/s
- 3 multichannel serial ports (MSP) up to 48 Mbit/s
- 2 I2C multi-master/slave interfaces
- One 8-channel, full-duplex high-speed serial interface, 108 Mbit/s
- Host port interface
- JTAG
3. TECHNICAL BRIEF
3.7.2 General features of MSM6280 device

■ Support for multimode operation - HSDPA, tri-band WCDMA (UMTS), quad GSM/ GPRS/ EDGE,
and GPS
■ Support for HSDPA downlink up to 7.2 Mbps (initial commercial release will support 3.6 Mbps
HSDPA. Later releases will have support for 7.2 Mbps HSDPA)
■ Support for WCDMA (UMTS) uplink data rate up to 384 kbps
■ High-performance ARM926EJ-S running at up to 270 MHz
■ ARM Jazelle Java hardware acceleration for faster Java-based games and other applets
■ QDSP4000 high-performance DSP cores
■ ntegrated gpsOne position location technology functionality
■ Integrated Bluetooth 1.2 baseband processor for wireless connectivity to peripherals
■ Qcamera¢‚ with 15 fps QVGA viewfinder resolution, and support for 4 MP camera sensors
■ Direct interface to digital camera module with video front end (VFE) image processing
■ True 3D graphics for advanced wireless gaming
■ SecureMSM v2.0 includes support for Open Mobile Alliance (OMA) DRM v2.0, SIM-lock and IMEI
integrity, and Q-fuse
■ Audio on par with portable music players
■ Vocoder support (AMR, FR, EFR, HR)
■ Advanced 14x14 mm, 0.5 mm pitch, 409-pin lead-free CSP packaging technology and 11x11 mm,
0.4 mm pitch, 432-pin lead free NSP technology
■ SD/SDIO hardware support
3. TECHNICAL BRIEF
3.8 Hardware Architecture
Sub LCD STn8810S12B2V1

BT
BT Bluetooth
(1.45î 160 x 64) UART 0 STLC2500C
STLC2500C (Ver.1.2, EDR)
MDIF Receiver (1107)
Main LCD
ST
ST MCP
MCP Memory
Memory Level
Level
(2.4î 320 x 240) MIC1
NAND
NAND 1GB
1GB Shifter
Shifter
SDRAM
SDRAM 512MB
512MB Audio
Audio Speaker (1812)
LCD
LCDBacklight
BacklightDriver
DriverIC
IC GPIO Codec
Codec
MSP0(I2S ) switch MAX
MAX Speaker (1812)
WM8753
WM8753 9775
9775
Camera (2M Pixel) Headset
CCIR
Camera (VGA) MIC2
ANT
MIC Mono out
Numeric Key
Keycoder
coderIC
IC EBI2
Key pad I2C(1)
(LM8333)
(LM8333) HPI
EBI1
NAND SDRAM MODEM RF
MODEM RF
MCP (TY9000A800KOGG40) (MSM6280)
(MSM6280) Chip
Chipset
set
Qwerty Key board JTAG JTAG GPS
UART 2 UART
USB AP MP
MM/SD I2C(0) OTG JTAG USB SIM
JTAGConnector
Connector
Level
Level
Camera, LCD Backlight Audio Codec.
Shifter
Shifter L/S
L/S SIM
SIM
L/S L/S PM6658
Micro Keypad
KeypadLEDLED
MicroSD
SD STw4810
Vibrator
Vibrator
Serial
Serial UART SW
Port
Port Coin cell
18pin
18pin
USB
USB MMI
MMI USB SW
Conn.
Conn. Battery
DC OVP
Power
Figure. Simplified Block Diagram
3. TECHNICAL BRIEF
3.8.1 STn8810 and supported peripherals
Figure. STn8810 and supported peripherals
3. TECHNICAL BRIEF
3.8.2 MSM6280 and supported peripherals
Figure. MSM6280 and supported peripherals
3. TECHNICAL BRIEF
3.9 Subsystem of STn8810
3.9.1 ARM926EJ processor

The STn8810 CPU is an ARM926EJ reduced instruction set computer (RISC) processor.
This 32-bit processor core supports 32-bit ARM® and 16-bit Thumb instruction sets, enabling the user
to trade off between high performance and high code density.
The cached ARM CPU features a memory management unit (MMU) and is clocked at 264 MHz.
It has a 32-Kbyte instruction cache and a 16-Kbyte data cache, and supports the Jazelle¢‚ extensions
for Java acceleration. It also includes an embedded trace module (ETM Medium+) for real-time CPU
activity tracing and debugging. It supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed
trace mode, with normal or half-rate clock.
3.9.2 Smart video accelerator (SVA)

Using leading-edge technology, this block is a low-power, high-performance video accelerator that
supports the following features:
■ MPEG-4 simple profile level 3 video encoder and decoder; real time up to VGA 30 fps encode only
or decode only)
■ H.263 profile 3 level 10 video codec; real time subQCIF or QCIF 15 fps for videoconferencing
■ H.263 profile 3 level 30 video encoder or decoder; real-time up to CIF 30 fps
■ JPEG baseline accelerated encoder or decoder, up to 4080 x 4080 pixels
■ Programmable DSP (MMDSP+) for intermediate level processing, clocked at 66 MHz
■ Picture pre-/post-processing
■ Low-power implementation
3.9.3 Smart audio accelerator (SAA)

This high-performance block is a flexible sophisticated audio accelerator based on the MMDSP+
programmable audio DSP, clocked at 133 MHz, and features:
■ 24-bit data path
■ Ultra-low power implementation
The audio accelerator features:
■ MP3, AAC, AAC+ (SBR) decoding, Midi synthesis, and more
■ Speech codecs: AMR (WB, NB), and more
■ Audio sample rates of 32 kHz, 44.1 kHz and 48 kHz
■ Noise reduction and echo cancelling
■ Stereo enhancements and surround effects
3. TECHNICAL BRIEF
3.9.4 Advanced power management unit (PMU)

The dynamic PMU optimizes power consumption of the STn8810. It delivers all the platform clocks,
and handles reset management. It also manages GPIO levels during sleep mode and emergency self-
refresh of SDRAM.
The PMU controls the external voltage regulator, in order to change its settings in different modes.
In deep-sleep mode, only GPIOs, the real-time clock (RTC), system and reset controller (SRC), PMU
and secured RAM remain in operation. The PMU also controls the embedded 1.2 V voltage switch that
switches off the logic supply after the platform has entered sleep mode.
The family of power manager ICs, STw481x companion chips, seamlessly interface with the Nomadik
STn8810 and optimize global system power consumption leveraging on the PMU.
3.9.5 Host port interface (HPI)

The host port interface features:
■ 16-bit parallel data bus
■ Multiplexed and non-multiplexed address/data bus
■ Indirect host access
■ Direct host access to a segment of STn8810 memory in multiplexed mode
3.9.6 General purpose inputs/outputs (GPIOs)

The STn8810 provides 96 programmable inputs or outputs that have switchable pull-up and pull-down
resistors and are controllable in two modes:
■ Software mode through an APB bus interface
■ Hardware mode through a hardware control interface
The GPIO interface provides the following individually programmable functions:
■ Any number of pins may be configured as interrupt sources
■ Debouncing logic can be enabled for each GPIO to filter out glitches on I/Os
■ Any GPIO may be used to wake up the device from sleep mode independent of interrupt
programming, and the input level that triggers wake-up is definable for each enabled GPIO
3. TECHNICAL BRIEF
3.9.7 Universal asynchronous receivers-transmitters (UARTs)

The STn8810 provides three autobaud UARTs, one of which offers all modem control/status signals.
They are enhanced versions of the industry-standard 16C550 UART with a high data rate up to 3.692
Mbit/s.
3.9.8 USB interface

The STn8810 USB interface is USB 2.0 compliant, with On-The-Go standard extension (rev 1.0)
compliance. The USB-OTG features:
■ Supports full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) signaling bit rate
■ Supports session request protocol (SRP) and host negotiation protocol (HNP)
■ 8 bidirectional endpoints plus control endpoint 0
■ Digital interface to external PHY
■ Fully compatible with STw4810 power manager companion chip
3.9.9 I2C bus interface

The STn8810 provides two I©˜C bus interfaces that support the following features:
■ Slave transmitter/receiver and master transmitter/receiver modes
■ Multi-master capability
■ 10-bit addressing
■ Standard (100 kHz) and fast (400 kHz) speeds
■ Compliance with I2C and DDC standards
In addition to receiving and transmitting data, the interface converts data from serial to parallel format
and vice-versa using an interrupt or polled handshake. The interrupts are enabled and disabled in
software.
3.9.10 MultiMediaCard/secure data card interface (MMC/SD/SDIO)

This interface can directly control one SD card (without encryption/decryption logic) or SDIO card, or
one MultiMediaCard. It also supports several of each card type using the GPIOs for card selection.
3. TECHNICAL BRIEF
3.10 Hardware Peripheral system of Stn8810
3.10.1 Keypad
KS10 has 75 buttons, 19 keys in Folder, 54 keys in main and 2 side keys.
KT610 use key coder IC because Stn8810 has not enough GPIO.
Key coder IC use interrupt and I2C interface for communication with STn8810.
Figure shows the Keypad circuit.
‘END’ Key is connected to PM_ON_SW_N to PM6658
AP_VDD_IO_2.7V
KEYCODER IC
R406
R407
KEY_ROW(0:7)
3.3K
3.3K
KEY_ROW(1)
KEY_ROW(0)
KEY_ROW(3)
KEY_ROW(2)
I2CSCL1
KEY_ROW(7)
KEY_ROW(6)
KEY_ROW(5)
KEY_ROW(4)
I2CSDA1
G6
G7
C7
D7
D6
C2
C1
C6
A7
B6
E7
E6
B7
F7
F5
F6
KEY_COL(3:0)
SCL_AB
SDA_AB
NC5
NC6
NC7
NC8
NC1
NC2
NC3
NC4
Wake_INP5
Wake_INP4
Wake_INP1
Wake_INP0
Wake_INP3
Wake_INP2
A6 G5 KEY_COL(3)
KEY_COL(4:7) Wake_INP6 K_Out3 KEY_COL(2)
B5 G4
KEY_COL(4) Wake_INP7 K_Out2 KEY_COL(1)
A5 F4
KEY_COL(5) K_Out4 U400 K_Out1 KEY_COL(0)
B4 G3
KEY_COL(6) K_Out5 LM8333GGR8_NOPB K_Out0
A4 F3
KEY_COL(7) K_Out6 _RESET KEYCODER_RSTN
A3 G2
K_Out7 Int_Rx
B3 G1
Gen_IO_0
Gen_IO_1
Gen_IO_2 WD_Out
Gen_In1
Gen_In0
A2 F2
CLK_In
Gen_IO_3 Int_Tx KEYCODER_INT

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
VCC1
VCC2
PWM
B2
A1
B1
TP401 D2
D1
F1
E1
E2
C3
C4
C5
D3
D4
D5
E3
E4
E5
C416 C417
68K
0.1u 0.1u
PWR_BTN
MENU_KEY
R408
AP_VDD_IO_2.7V
Figure. Schematic of key coder IC
3. TECHNICAL BRIEF
AP_VDD_IO_2.7V
2
4
6
8
2
4
6
8
RA400 100K
RA401 100K
1 2 3 4 SHIFT_L LS K MENU
SW406
1
3
5
7
1
3
5
7
SW400 SW401 SW402 SW403 SW404 SW405
R856 MENU_KEY
KEY_ROW(0)
100o h m 5 6 7 8 SHIFT_R RSK
SW407 SW408 SW409 SW410 SW411 SW412
KEY_ROW(1)
9 0 Q W CHR OK
SW413 SW414 SW415 SW416 SW417 SW418
R851
KEY_ROW(2)
100o h m E R T Y CTRL SHOT
SW419 SW420 SW421 SW422 SW423 SW424
KEY_ROW(3)
U I O P A SEND
SW425 SW426 SW427 SW428 SW429 SW430
KEY_ROW(4)
S K L G H LEFT
SW431 SW432 SW433 SW434 SW435 SW436
KEY_ROW(5)
J D F Z X BACK SPACE UP
SW437 SW438 SW439 SW440 SW441 SW442 SW443 SW444
KEY_ROW(6)
C V B N M ENTER RIGHT DOWN
KEY_ROW(7)
KEY_COL(0)
KEY_COL(1)
KEY_COL(2)
KEY_COL(3)
KEY_COL(4)
KEY_COL(5)
KEY_COL(6)
KEY_COL(7)
EVLC14S02050
EVLC14S02050
VA402
VA805
END (POWER_ON) 4
SW453 VOL_UP KEY_ROW(6)
3
KEY_COL(5)
2
VOL_DOWN KEY_ROW(7)
KEY_ON_SW_N 1
EVLC14S02050
EVLC14S02050
EVLC14S02050
CN401
ZD404 EVLC14S02050
ZD401
ZD402
ZD403
Figure. Schematic of keypad
3. TECHNICAL BRIEF
1 6 DOWN
SW101 SW102 SW103
K EY_ROW(0)
2 7 B A CK
SW104 SW105 SW106
K EY_ROW(1)
3 8 UP
SW107 SW108 SW109
K EY_ROW(2)
4 9 OK
SW110 SW111 SW112
KEY_ROW(3)
5 0 SEND
SW113 SW114 SW115
KEY_ROW(4)
* # SHOT
SW116 SW117 SW118
KEY_ROW(5)
KEY_COL(6)
KEY_COL(7)
EVLC14S02050
EVLC14S02050
EVLC14S02050
EVLC14S02050
EVLC14S02050
EVLC14S02050
EVLC14S02050
EVLC14S02050
END (POWER_ON)
SW100
VA103
VA105
VA107
VA102
VA104
VA106
VA108
VA109
K EY_ON_SW_N
ZD100 EVL C14S02050
Figure. Schematic of keypad
3. TECHNICAL BRIEF
3.10.2 Folder on/off operation

There is a magnet to detect the folder status, opened or closed.
If a magnet is close to the hall-effect switch, the voltage at pin1 of U402 goes to 0V.
This folder signal is delivered to GPIO5 of the Main CPU(U100) .
U402 BU52031NVX
1 4 AP_VDD_IO_2.7V
FOLDER_DETECT OUT VDD
PGND
2 3
GND NC
C418
0.1u
5
FOLDER_SENSE
[ FOLDER_DETECT = H : Folder Open , L : Folder Close ]
Figure. Schematic of folder on/off detection circuit
3. TECHNICAL BRIEF
3.10.3 Keypad backlight

There are 4 White LEDs on Top side of Main PCB and 2 White LEDs on Top side of Key PCB in board
backlight circuit.
Both of them are controlled by PM6658.
KEYPAD LED
+VPWR AP_+VPWR
LD400 LEWWS44-E R409 R852

KPD_MAIN_DRV_N
68 51
LD401 LEWWS44-E R410
VA416
68 EVL14S02200

68
68
Figure. Schematic of main PCB keypad backlight circuit
A P_+VPWR
L EWWS44-E
L D100 R103
100o h m
L EWWS44-E
L D101 R104
K PD_FOL DER_DRV_N
100o h m
VA 1 1 0
EVL 14S02200
Figure. Schematic of key PCB keypad backlight circuit
3. TECHNICAL BRIEF
3.10.4 Micro SD
1.8V Signal Level shifting 3.1V Signal
CPU Clock PMIC Clock

SD Socket
(ST Micro.) Command (ST Micro.) Command
Data Data
SD_INT
H8 J4
USBINTN USBINTN VBAT_MMC
G9
USBSCL
USBSDA
H9
USBSCL
USBSDA PMIC VMMC
K5
VMMC_3.1V
TP308 G2 F3
MCFBCLK
R306 100ohm
MCCLK
MCCMDDIR
TP310
H5
G3
MCCLK
MCFBCLK
MCCMDDIR
(ST Micro.) LATCHCLK
CLKOUT
G1
C317
2.2u
TP311 H1 F1
MCCMD MCCMD DATAOUT3
TP312 K2 E3
C318 MCDAT0DIR MCDAT0DIR DATAOUT2
K1 E2
120p MCDAT0 MCDATA0 DATAOUT1 SD_CLK
H4 E1
MCDAT31DIR MCDATA31DIR DATAOUT0 SD_DAT(3)
H3 F2
MCDAT1 MCDATA1 CMDOUT SD_DAT(2)
H2
MCDAT3 MCDATA3 SD_DAT(1)
TP317 K9 J5
MCDAT2DIR MCDAT2DIR GPO1 SD_DAT(0)
TP318 J1 K6
MCDAT2 MCDATA2 GPO2 SD_CMD
GND1
GND2
NC1
NC2
NC3
NC4
NC5
NC6
NC7
B1
B7
B8
C5
F8
G8
K10
B9
D3
C319
1u
VMMC_3.1V
2
4
6
8
10K
10K
SD Socket
REMOTE_PWR_ON_AP
RA100
R100
1
3
5
7
NAND_READY_AP
S100 SCHA 1B 0102

MCDAT31DIR
MCDAT0DIR
MCDAT2DIR
SD_DAT(2) DA T2_RSV
MCCMDDIR
R101 10 CD_DA T3_CS

SD_DAT(3)
MSPRXD0
MCFBCLK
MSPTXD0
R102 10
MSPTFS0
SD_CMD CMD_DI
R103 10
MCDAT3
MCDAT2
MCDAT1
MCDAT0
VDD
MCCMD
SD_INT
MCCLK
SD_CLK CL K _SCL K
R104 10 VSS
SD_DAT(0) DA T0_DO
R105 10 DA T1_RSV
SD_DAT(1)
R106 10 COMMON
DETECT
SD_INT
G24
D12
C12
D13
C13
D14
C14
D15
C15
H22
E17
E13
E14
E15
E16
F17
F24
DUMMY1
DUMMY2
MCCLK
MCFBCLK
MCCMD
MCCMDDIR
MSPTXD0
MSPTFS0
MSPRXD0
MSPSCK0
MSPTXD2_SMPCE2N
MSPTFS2_SMPCE1N
MSPTCK2_SMPIORN
MCDAT3
MCDAT2
MCDAT1
MCDAT0
MCDAT0DIR
MCDAT31DIR
RCLAMP0504P.TCT
RCLAMP0504P.TCT
R107
3
C101
C102
C103
C104
C105
IO2
NC
IO1
D100
D101
IO1
NC
IO2
C106
P_GND
P_GND
5V_NC
5V_NC
1u
IO3
IO4
IO4
IO3
DNI
DNI
DNI
DNI
DNI
DNI
4
CPU
(ST Micro.) T-FL A SH SOCK ET
3. TECHNICAL BRIEF
3.11 Subsystem of MSM6280
3.11.1 ARM Microprocessor Subsystem

The MSM6280 device uses an embedded ARM926EJ-S microprocessor. This microprocessor,
through the system software, controls most of the functionality for the MSM device, including control of
the external peripherals such as the keypad, LCD, RAM, ROM, and EEPROM devices.
Through a generic serial bus interface (SBI), the ARM926EJ-S configures and controls the
functionality of the RFR6220, RTR6250, RFR6250, and PM6650-2 devices.
For the RFCMOS platform (RTR6285 and PM6658), SSBI (single-wire SBI) will be supported.
3.11.2 UMTS/HSDPA Subsystem

The UMTS/HSDPA subsystem performs the digital release 99 June 2004 of the WCDMA FDD
standard and release 5 specifications of HSDPA signal processing. See Section 1.3.2 for more details.
■ Demodulating fingers
3.11.3 GSM/GPRS Subsystem

The GSM/GPRS/EGPRS subsystem reuses the MSM6250® GSM core. It performs the digital GSM
signal processing and PA gain controls for GPRS support. The PA output level is controlled by an
analog signal generated on the MSM device. In GSM mode, the power profile ramps up before the
burst and ramps down after the burst. In GPRS mode, at the beginning of each burst (up to Four active
transmit slots), PA must be smoothly ramped up to some desired output power level, held at that level
for the current slot, smoothly ramped down/up during the transition period and held to the new level for
the next slot until the last slot. Then it must be smoothly ramped down to near-zero level. The
MSM6280 support differential GSM PA power control output.
3.11.4 RF Interface
The RF interface communicates with the mobile station external RF circuits. Signals to these Circuits
control signal gain in the Rx and Tx signal path, control DC offset errors, and maintain the system
frequency reference.
3.11.5 HKADC
The MSM6280 device has an on-chip 8-bit analog-to-digital converter (ADC) that is available for
digitizing analog signals representing parameters such as battery voltage, temperature, and RF power
levels. These parameters support handset-level housekeeping functions - various tasks that must be
performed to keep the “house” or handset, in order. Thus the term housekeeping ADC (HKADC) is
used.
3. TECHNICAL BRIEF
3.11.6 Mode select and JTAG interfaces

The mode pins to the MSM6280 device determine the overall operating mode of the ASIC. The options
under the control of the mode inputs are native mode, which is the normal subscriber unit operation,
ETM mode, which enables the built-in trace mode, and test mode for factory testing.
The MSM6280 device meets the intent of the ANSI/IEEE 1149.1A-1993 feature list. The JTAG
interface can be used to test digital interconnects between devices within the handset during
manufacture.
3.11.7 Stereo Wideband CODEC

The MSM6280 device integrates a wideband voice/audio codec into the MSM. The codec supports two
differential microphone inputs, one differential earphone output, one single-ended earphone output,
and a differential analog auxiliary interface. The codec integrates the microphone and earphone
amplifiers into the MSM6280 device, reducing the external component count to just a few passive
components. The microphone (Tx) audio path consists of a two-stage amplifier with the gain of the
second stage set externally. The Rx/Tx paths are designed to meet the ITU-G.712 requirements for
digital transmission systems.
3.11.8 Vocoder Subsystem

The MSM6280 QDSP4000 supports AMR, FR, EFR, and HR. In addition, the QDSP4000 has modules
to support the following audio functions: DTMF tone generation, DTMF tone detection, Tx/Rx volume
controls, Tx/Rx automatic gain control (AGC), Rx automatic volume control (AVC), ear seal echo
canceller (ESEC), acoustic echo canceller (AEC), noise suppression (NS), and programmable, 13-
tap, Type-I, FIR, Tx/Rx compensation filters. The MSM6280 device’s integrated ARM926EJ-S
processor downloads the firmware into the QDSP4000 and configures the QDSP4000 to support the
desired functionality.
3.11.9 General-Purpose Input/Output Interface

The MSM6280 device has general-purpose bidirectional input/output pins. Some of the GPIO pins
have alternate functions supported on them. The alternate functions include a USB interface,
additional RAM, ROM, and general-purpose chip-selects, a parallel LCD interface, and a UART
interface. The function of these pins is documented in the various software releases.
3. TECHNICAL BRIEF
3.11.10 UART
The MSM6280 device employs three UARTs. UART1 has dedicated pins while UART2 and UART3
share multiplexed pins.
3.11.11 USB
The MSM6280 device integrates a universal serial bus (USB) controller that supports both
unidirectional and bidirectional transceiver interfaces. The USB controller acts as a USB peripheral
communicating with the USB host. MSM6280 supports the 3-wire USB functionality.
3.12 External memory interface

The MSM6280 device was designed to provide two distinct memory interfaces. EBI1is used to support
high-speed synchronous memory devices. EBI2 is used to support slower asynchronous devices such
as LCD and NAND Flash.
■ EBI1 Features
- 32-bit SDRAM (low power SDRAM)
- The MSM6280 device supports only 32-bit SDRAM. NOR/PSRAM configurations are not
supported. The reason that only 32-bit SDRAM is supported on the MSM6280 device is that when
higher speed HSDPA (7.2 Mbps) is implemented, the ARM will be clocked at 270 MHz and the bus
at 90 MHz. QUALCOMM at this time guarantees 3.6 and 7.2 Mbps HSDPA performance with this
memory configuration. HSDPA performance on the MSM6280 device with NOR/PSRAM parts
cannot be guaranteed at this time. There could also be potential MIPs issues for HSDPA with
NOR/PSRAM and 16-bit SDRAM. Therefore, we strongly recommend customers to use 32-bit
SDRAM in their designs.
■ EBI2 Features
- Support for asynchronous flash (16-bit and 8-bit). Page mode is not supported.
Programmable wait states for access, hold, and recovery for all chip-selects.
- Interface support for byte addressable 16-bit devices (UB_N and LB_N signals)
- Support for 8-bit and 16-bit wide NAND Flash
- Support of four general-purpose chip-selects. Two of these chip-selects can be configured as
NAND chip-selects.
- Support for parallel, port-mapped LCD interfaces (Intel and Motorola timing), (18- bit, 16-bit, and 8-
bit)
- Support for system word, Hword, and byte accesses to 16-bit and 8-bit wide devices on all chip-
selects (bus sizing supported for all interfaces with the exception of NAND)
- Support for memory accesses (with exception of NAND) by SYS AHB and DMA AHB bus. NAND
is accessed through a special controller
3. TECHNICAL BRIEF
- Support for any generic external peripheral whose interface timing is the same as that of
asynchronous memories
- SW controllable write protect feature (against user mode writes)
- NAND controller change to allow a software programmable command that can be issued to the
NAND device.
- Support for an EBI2 pin interface for either 1.8 V or 2.6 V pad power supply voltage
- EBI2 boot-up from a 16-bit non-multiplexed NOR interface type device with special support added
to handle the latency associated with fetching the first page from a NAND device.
■ 512Mb NAND flash memory + 512Mb SDRAM (1die)
Interface Spec
Device Part Name Maker Read Access Time Write Access Time
FLASH TYA000BC00DOGG Toshiba 35 ns/Bytes 50 ns/Bytes
SDRAM TYA000BC00DOGG Toshiba 107 ns/4Double Word 53 ns/4Double Word
Table. External memory interface for KT610
3. TECHNICAL BRIEF
3.13 Hardware sub system of MSM6280
3.13.1 RF Interface
The MSM6280 device interfaces with all MSM6280-series radioOne ICs. There will be three RF
platforms supported within the MSM6280 chipset, schedules of which are available in the software and
product release documents. The MSM6280 radioOne chipset includes
■ MSM6280 chipset with Platform 3U

- RFR6250 UMTS high-band receiver IC + GPS receiver IC
- RTR6250 WCDMA Tx/GSM/GPRS/EDGE transceiver IC
- RFR6220 UMTS low-band receiver IC
- PM6650-2 power management IC
- MSM6280 Mobile Station Modem IC
■ MSM6280 chipset with Platform B/E (RFCMOS)

- RFR6275 WCDMA RF-to-baseband receiver IC
- MSM6280 chipset with Platform D:
- RFR6500/6525 WCDMA RF-to-baseband receiver IC
■ MSM6280 chipset with Platform F

- PM6658 power management IC
■ Platform 3U Lite is Platform 3U minus the RFR6220 IC, and it is also supported by the MSM6280
device. Platform 3U Lite supports the following bands/modes
- UMTS/HSDPA 2100/1900 MHz and GSM/GPRS/EDGE 850/900/1800/1900 MHz
3. TECHNICAL BRIEF
F8
GPIO66 TP501
AA1
XMEM1_CS_N1_GPIO76 CAM_IF_PWDN BUFF_TCXO_FF
Y6
XMEM1_CS_N3_SDRAM1_CS_N1_GPIO77 EAR_SENSE_N
L25
UART3_RFR_N_GPIO87 VREG_TCXO_2.85V
H6 NC7SZ74L8X U500
UART2_DP_RX_DATA_GPIO89 C542
F18 8 1
SYNTH0_GP_PDM0_GPIO92 RTC_CONT VCC _PR 0.1u
H18
SBST1_GPIO93 EAR_MIC_LDO_EN
7 2
C545 CK _CLR
H13
TX_AGC_ADJ 33p R506
L13 6 3
TRK_LO_ADJ D Q TRK_LO_ADJ
F19
TCXO_EN_GPIO94 TCXO_EN 2K
F17 5 4
PA_ON0 PA_ON _Q GND C546
33nF
A12
Q_OUT_N TX_QM
B 12
Q_OUT TX_QP
A13
I_OUT_N TX_IM
B 13
I_OUT TX_IP
F12
DAC_REF DAC_REF
W23
Q_IM_CH1 GPS_QN
V 23
Q_IP_CH1 GPS_QP
V25
I_IM_CH1 GPS_IM
W25
I_IP_CH1 GPS_IP
AA25
Q_IM_CH0 RX_QM
Y25
Q_IP_CH0 RX_QP
AB25
I_IM_CH0 RX_IM
AC25
I_IP_CH0 RX_IP
(WCMDA PAM MODE)

D17
GP_PDM2_PA_RAN_GE1
H17
GP_PDM1_PA_RAN_GE0 PA_R0
H15
TRST_N
D16
TCK
F15
TMS
D15
T DI
A17
TD O
H16
RTCK
K19 R507 51K
AUX_PCM_CLK_GRFC14_GPIO80
N21
AUX_PCM_DIN_GRFC13_GPIO14 GPS_LNA_EN
G4
AUX_PCM_DOUT_GRFC12_GPIO103 TP502
J8
AUX_PCM_SYNC_GRFC11_GPIO102
H12
TX_ON_GRFC10 TX_ON
B4
GRFC8_GPIO11 ANT_SEL2
T23
T19
GRFX6_GPIO9 ANT_SEL0
D11
GRFC5_AUX_SBST_GPIO8
H10
GRFC4_AUX_SBCK_GPIO7
F10
GRFC3_GPIO6
D9
GRFC2_GPIO5
A8
GRFC1_AUX_SBDT_GPIO4
B8
GRFC0_GPIO3
G23 TP504
BT_CLK_GPIO25 HPIEV_IT_STATE_ETMTRIGIN
F23
BT_SBST_GPIO24 HPI_EME_APE_ETMPSTA2_XTIDAT
CAMIF_DATA2_AUX_TRST_N_GPIO54
E26
BT_SBCK_GPIO23 HPI_EME_MOD_ETMPSTA1_XTIDAT
E25
CAMIF_DATA6_AUX_TDO_GPIO58
CAMIF_DATA4_AUX_TMS_GPIO56
CAMIF_DATA3_AUX_TCK_GPIO55
BT_SBDT_GPIO22
CAMIF_DATA5_AUX_TDI_GPIO57
H21 TP505
BT_TX_RX_N_GPIO21 HPI_IT_MOD_ETMSYNCA_XTIDAT
R19 TP506
BT_DATA_GPIO20 HPI_IT_APE_ETMPSTA0_XTIDAT
CAMIF_HSYNC_GPIO15
CAMIF_VSYNC_GPIO16
A22
CAMIF_DATA9_GPIO61
CAMIF_DATA8_GPIO60
CAMIF_DATA7_GPIO59
CAMIF_DATA0_GPIO83
CAMIF_DATA1_GPIO81
CAMIF_PCLK_GPIO82
MDDIC_DATP
A23
GSM_PA_DAC_REF
MDDIC_DATN
I2C_SDA_GPIO26
B22
I2C_SCL_GPIO27
SYNTH1_GPIO41
RINGER_GPIO18
PA_POWER_CTL
MDDIC_STBP
B23
VDD_EF_USE
MDDIH_STBN
MDDIH_DATN
MDDIH_STBP
MDDIH_DATP
MDDIC_STBN
GPIO19
GPIO17
SBCK
SBDT
SBST
H26
J23
L21
K21
N16
F20
F16
D20
L15
J19
D22
C25
D21
B3
E23
K23
J25
J26
G21
K26
H23
L19
P25
AD26
A19
A20
B19
B20
R16
R508
100K
TP507
2M_RSTN
RF_SBDT
PM_SBDT
2M_PWDN
CAM_IF_POWER
GSM_PA_RAMP
GSM_PA_DAC_REF
10% Place near

C547
0.1u MSM pin AD26
(Check CAM_DATA PINOUT !!!!)
Figure. Schematic of RF Interface of MSM6280`
3. TECHNICAL BRIEF
3.13.2 MSM sub system

3.13.2.1 SIM interface
SIM interface scheme is shown in Figure.
And, there control signals are followed
■ USIM_CLK : USIM Clock
■ USIM_Reset : USIM Reset
■ USIM_Data : USIM Data T/Rx
USIM CLK VREG_USIM 2.85V
USIM Reset USIM CLK

MSM6280 PM6658 USIM
USIM Data USIM Reset
USIM Data
Figure. SIM Interface
3.13.2.2 UART interface

UART signals are connected to MSM GPIO through IO connector with 115.2kbps speed. And, used for
RF calibration and Data download.
GPIO_Map Name Note
GPIO_96 UART_RXD Data_Rx
GPIO_95 UART_TXD Data_Tx
Table. UART interface
3. TECHNICAL BRIEF
3.13.2.3 USB
The MSM6280 device contains a Universal Serial Bus (USB) interface to provide an efficient
interconnect between the mobile phone and a personal computer (PC). The USB interface of the
MSM6280 was designed to comply with the definition of a peripheral as specified in USB Specification,
Revision 2.0.
The USB 2.0 specification requires hosts such as PCs to support all three USB speeds, namely low-
speed (1.5 Mbps), full-speed (12 Mbps) and hi-speed (480 Mbps). The USB 2.0 specification allows
peripherals to support any one or more of these speeds.
KT610’s USB interface uses the PM6658 internal logic for USB Transceiver.
Name Note
USB_DAT Data to/from MSM
USB_SE0 Data to/from MSM
USB_OE_N Out-Put Enable of Transceiver
USB_VBUS USB_Power From Host(PC)
USB_D+ USB Data+ to Host
USB_D- USB Data- to Host
Table. USB signal interface
3. TECHNICAL BRIEF
USB_OE_ N USB_VBUS
USB_DAT USB_D+ MMI
MSM6280 PM6658 Connector
USB_SE0 USB_D-
Figure. USB Interface
MSM6280_USB Block PM6658_USB Block

MMC_DATA_SDCC_DAT0_GPIO32
E2
BATT_FET_N BAT_FET_N
MMC_CLK_SDCC_CLK_GPIO31
Q801 F2
UART3_DP_RX_DATA_GPIO85
UART3_DP_TX_DATA_GPIO84
USB_OVP_G
D2 D1
SI1072X J10
VCOIN
H1
USB_VBUS
S
C822
UART3_CTS_N_GPIO86
G
10K R808
USB_VBUS
D4 D3
F1
VSW_5V
G1
MMC_CMD_GPIO30
VREG_5V
K5
4.7u
USB_VBUS_IN VSW_MSMC VSW_MSMC

K4
USB_OE_TP_N
VREG_MSMC VREG_MSMC
USB_SE0_VM
K7
USB_DAT_VP
VSW_S2 VSW_S2
L8
VREG_S2 VREG_S2
K6
VSW_S3 VSW_S3
GPIO40
GPIO42
L6
VREG_S3 VREG_S3
L23
M21
M19
D6
D7
N26
N23
N25
H14
L14
M16
H2
USB_ID
J2
USB_D_P MSM_USB_D+
J1
USB_D_M MSM_USB_D-
F4
USB_OE_N USB_OE_N
G4
USB_DAT USB_DAT
H4
USB_SE0 USB_SE0
PM_INT_N
PS_HOLD
USB_OE_N
USB_SE0
USB_DAT
Figure. Schematic of USB block (MSM6280 Side & PM6658 Side)
3. TECHNICAL BRIEF
3.13.2.4 HKADC (House Keeping ADC)

The MSM6280 TS/HKADC is an 8-bit successive-approximation circuit. The resolution of the ADC is 8-
bit. The TS/HKADC block diagram is shown in Figure. The TS/HKADC contains four main subblocks: a
6- channel MUX, a sample and hold circuit, a digital-to-analog converter, and a comparator latch block.
Figure. MSM6280 HKADC Block diagram
Channel Signal Note
HKADC0 AMUX_OUT RF PAM Temperature sensing
HKADC1 VBATT_SENSE Battery voltage level sensing

HKADC2 - -
HKADC3 VBAT_TEMP Battery Temperature sensing
HKADC4 PCB_Rev_ADC PCB Revision Checking
HKADC5 - -
Table. HKADC channel table
3. TECHNICAL BRIEF
3.13.3 Power Block

3.13.3.1 General
MSM6280A, included RF, is fully covered by PM6658(Qualcomm PMIC). PM6658 cover the power of
MSM6280, MSM memory, RF block, 2M Camera, USB, USIM and TCXO.
Major power components are :
PM6658 (U801) : Phone power supply
SIA411DJ (Q800) : External charger supply switching & Main Battery charging control
3.13.3.2 PM6658
A functional block diagram for the PM6658 device is shown in Figure.
The input power management portion accepts power from common sources°™battery, external
charger, adapter, USB_VBUS, coin cell backup°™and generates all the regulated voltages needed to
power the appropriate handset electronics. It monitors and controls the power sources, detecting
which sources are applied, verifying that they are within acceptable operational limits, and coordinates
battery and coin cell recharging while maintaining the handset electronics supply voltages.
The device's general housekeeping functions include a sixteen-position analog multiplexer that Has 5
internal connections, 6 hardwired external connections, and supports an additional 12 External
connections via the multipurpose pins (MPPs). The internal connections are used to monitor on-chip
functions, such as the die temperature and bandgap reference voltage. The hardwired external
connections access input power nodes, such as VCHG, VBAT, etc. The 12 multipurpose pins can be
configured as analog inputs that are routed through switch circuits to create 5 multiplexer inputs; these
are available to monitor system parameters, such as temperatures and battery ID. The multiplexer
output signal's offset and gain is adjusted, then buffered and routed to the MSM device for analog-to-
digital conversion.
IC-level interfaces include the configurable serial bus interface (SBI) used by the MSM device to
control and status the PM6658 IC. This bus is supplemented by an interrupt manager for time- Critical
information. Another dedicated IC interface circuit monitors multiple trigger events and controls the
power-on/power-off sequences.
On-chip voltage regulators generate 19 programmable output voltages using a combination of 4
switched-mode power supplies and 15 low-dropout linear regulators, all derived from a Common
trimmed voltage reference. Two externally controlled bits allow selection of the default MSM core
voltage (VREG_MSMC = 1.200 or 1.375 V) and determine whether a buck regulator (VREG_S3) is
enabled or not upon power up.
3. TECHNICAL BRIEF
Figure. PM6658 Functional Block Diagram
3. TECHNICAL BRIEF
3.13.3.3 Charging control

The PM6658 IC provides support circuitry for charging Li-ion batteries, utilizing as many as four MSM-
enabled charging techniques: trickle, constant current, constant voltage, and pulse. Battery voltage,
external supply voltage, and total detected current measurements are available to the MSM device
through the analog multiplexer. This allows the MSM device to monitor charging parameters, make
decisions, and control the charging process.
Figure. Charging sequence for a severely depleted battery
4.2V~3.96V 3.95V ~ 3.87V 3.86V~3.79V 3.78V~3.75V 3.74V~3.70V 3.69V~3.64V 3.63V~3.51V 3.50V~3.20V
Figure. KT610 Battery Bar Display (Standby condition)
3. TECHNICAL BRIEF
Trickle charging
Trickle charging of the main battery, enabled through software and powered from VDD, is provided
by the PM6658 device. This mode is used to raise a severely depleted battery’s voltage to a level
sufficient to begin fast charging. If fast charging is enabled while the battery is below 2.55 V (the
UVLO threshold), the battery pulls VDD down and causes the phone to turn off. Even if the battery
voltage is between 2.55 and 3.10 V, fast charging is still not recommended because the regulators
can fail. Trickle charging avoids these two potential problems by getting the battery voltage to about
3.1 V or more before attempting fast charging.
The trickle charger is an on-chip programmable current source that supplies current from VDD to
the VBAT pin; pertinent performance specifications are given in Tabl. Software must terminate
trickle charging based upon battery voltage measurements at the MSM device’s HKADC (routed
through the PM analog multiplexer) and the battery type - there is no preset termination threshold.
Figure. Trickle Charging
3. TECHNICAL BRIEF
Constant current charging

The PM6658 device supports constant current charging of the main battery by closing the battery
MOSFET (connecting the battery to VDD), and closed-loop controlling the pass transistor. The
closed-loop control regulates the total current (handset electronics plus charging current) to match
the programmed value (IMAXSEL). The MSM device monitors the charging process as described
earlier, and continues the constant current mode until the battery reaches its target voltage.
Lithiumion batteries require further charging using constant voltage or pulsed techniques.
Figure. Constant current charging
3. TECHNICAL BRIEF
Constant voltage charging

Once constant current charging of a Li-ion battery is finished, the charging continues using Either
constant voltage or pulse techniques. Discussion of constant voltage charging is presented here;
pulse charging is covered in the next subsection.
The MSM device and its software determines if and when it is appropriate to begin the constant
voltage mode within the charging process. When the battery voltage reaches a target value, a Timer
is started; when that time expires, charging is complete.
The PM6658 support of constant voltage charging is very similar to its constant current mode:
The battery MOSFET is closed and the pass transistor is closed-loop controlled. However, in this
case, the closed-loop control regulates the voltage at VBAT to match the programmed Value
VMAXSEL. This ensures the most accurate final battery voltage - lithium-ion battery manufacturers
recommend a voltage accuracy of 1% or better at the end of charge.
Figure. VBAT regulation during constant voltage charging
3. TECHNICAL BRIEF
3.14 Audio and sound
3.14.1 Overview of Audio & Sound & BT path
2.7V 1.8V
ANT PM_SCL
PM_SDA
STLC2500C PCMDATAOUT WM_ADCDAT
Filter VXDOUT
PCMDATAIN WM_DACDAT VXDIN AU_19.2M
(BT) MIC_BIAS
PCM PCMSYNC WM_LRC
VXFS PCM
BT_19.2M PCMCLK Level WM_BCLK VXCKLK
UART
Shifter
MIC1
MIC
SCLK
SDIN OUT3
LOUT1
Receiver
UART0 SPK_AMP_EN
I2CSCL0 VT_SW
GPIO GPIO
I2CSDA0 MAX9775
WM_DACDAT
ROUT1
MSPRXD0
WM_MSPRXD0 Speaker
LOUT2
Switch
ROUT2
STN8810
(CPU) GPIO21
WM_LRC WM_8753 Audio
WM_BCLK (Audio Codec) Subsystem
GPIO22
SDA
SCL
MSPTCK0 BCLK MIC2
GPIO19
MSPTFS0 LRC
MSPTFS0
Head Set
MSPTXDO ADCDAT
MSPTXDO DACDAT I2S
GPIO GPIO RXP 18PIN CONN
RSN
MSM LINE1
6280 LINE2
WM_MONO1
WM_MONO2
HOOK_SENSE_N
EAR_SENSE_N
Figure. Block diagram of Audio & Sound path
3. TECHNICAL BRIEF
3.14.2 Audio signal processing & interface

3.14.2.1 MSM6280 audio interface
The MSM6280 audio front end is comprised of the stereo wideband codec, PCM interface, and
additional DSP audio processing.
The stereo wideband codec allows the MSM6280 device to support stereo music/ringer melody
applications in addition to the 8 kHz voice band applications on the forward link. In the audio transmit
path, the device operates as 13-bit linear converter with software-selectable 8 kHz and 16kHz
sampling rate. In the audio receive path, the device operates as a software selectable 13-bit or 16-bit
linear converter with software selectable 8 kHz, 16 kHz, 22.05 kHz, 24 kHz,32 kHz, 44.1 kHz, or 48
kHz sampling rate. Through software, the Rx path can be configured as either a mono or stereo
output.
New to the MSM6280 device is a transmit (Tx) ADC path that now supports stereo wideband
sampling.The integrated codec contains all of the required conversion and amplification stages for the
audio front end. The codec operates as a 13-bit linear codec with the transmit (Tx) and receive (Rx)
filters designed to meet ITU-T G.712 requirements. The codec includes a programmable sidetone path
for summing a portion of the Tx audio into the Rx path. An on-chip voltage/current reference is
provided to generate the precise voltages and currents required by the codec. This circuit requires a
single capacitor of 0.1 uF to be connected between the CCOMP and GND pins.
The on-chip voltage reference also provides a microphone bias voltage required for electret condenser
microphones typically used in handset applications. The MICBIAS output pin is designed to provide
1.8 volts DC while delivering as much as 1 mA of current. Audio decoder summing and headset switch
detection are included.
The codec interface includes the amplification stages for both the microphone and earphone.
On the transmit (Tx) path the interface supports two differential microphone inputs, a differential
auxiliary input, and a stereo line input. On the receive (Rx) path the interface supports one differential
earphone output, a stereo single-ended headphone output, one differential auxiliary output and stereo
single-ended line outputs.
The codec is configured by the codec SBI Registers. Also part of the audio front end is the PCM
interface. The PCM interface allows for an external codec to be used instead of the internal codec.
This interface can be used in I2S mode which will allow for an external stereo DAC to be used.
The audio front end includes additional DSP audio processing that does gains, filtering and other audio
processing. The DSP audio processing is configured through the QDSP4000 command types, and is
not directly controlled by the microprocessor.
3. TECHNICAL BRIEF
Figure. Detailed diagram of MSM6275 audio interface
3. TECHNICAL BRIEF
3.14.2.2 STn8810 audio interface

- Smart Audio Accelerator (SAA)
This high-performance block performs an audio hardware accelerator based on a programmable audio
DSP with 24-bit data path and ultra low power implementation.
Figure. Detailed diagram of STn8810 audio interface
3. TECHNICAL BRIEF
3.14.2.3 WM8753L audio interface

The WM8753L is a low Power, high quality stereo Codec with integrated Voice CODEC designed for
portable digital telephony applications such as mobile phone, or headset with Hi-Fi playback capability.
The device integrates dual interfaces to two differentially connected microphones, and includes drivers
for speakers, headphone and earpiece. External component requirements are reduced as no separate
microphone or headphone amplifiers are required. Advanced on-chip digital signal processing
performs tone control, Bass Boost and automatic level control for the microphone or line input through
the ADC.
Figure. Detailed diagram of WM8753L audio interface
3. TECHNICAL BRIEF
MSM6280 Block Handset main MIC Block
WM_MONO2
WM_MONO1
WM_HPH_R
WM_HPH_L
WM_RXN
WM_RXP
VREG_MSMP_2.6V VREG_MSMP_2.6V
WM_MICBIAS
SPM0204HE5-PB-3
R501
P
4 C239 1u
R500
G2 WM_MIC1N
3
RESOUT_EBI2_N
R502
300K
150K
G1
47K
MSM_RESIN_N
2
100K
BUFF_TCXO
SLEEP_CLK
O
1
100K
R830
R829
WM_MIC1P
MIC200 C243 1u
C250
R504
R503
VBATT_SENSE
Place near C854 C853 C852 C851 C510 C511

VBAT_TEMP
AMUX_OUT
C505
39p
MSM pin W18
0.1u 39p 39p 39p 39p 10p 10p
TP500
10% (CODEC VSS)

0
DNI
TP818
AC18
AC17
AC22
AC21
AC19
AC20
AE17
AE21
AE22
AA23
AB23
AA17
AE18
AA18
AA19
AE19
AE20
AA20
AF18
AF19
AF21
AF22
AF20
W21
W17
AD1
AA4
D18
U23
A10
B10
A16
B16
Y23
V21
V19
Y21
F13
T21
T15
F11
TCXO
RESIN_N
RESOUT_N
RESOUT_N_EBI1
WDOG_EN
MODE2
MODE1
MODE0
BOOT_MODE
BOOT_MODE2
BOOT_MODE3
HKAIN0
HKAIN1
HKAIN2
HKAIN3
HKAIN4
HKAIN5
LINE_ON
LINE_OP
HPH_R
HPH_L
EAR1ON
EAR1OP
MICBIAS
AUXOUT
HPH_VREF
LINE_L_IP
LINE_L_IN
LINE_R_IP
LINE_R_IN
AUXIN
AUXIP
MIC2N
MIC2P
MIC1N
MIC1P
CCOMP
USB_XTAL48_IN
USB_XTAL48_OUT
SLEEP_XTAL_IN
SLEEP_XTAL_OUT
F25
SDCC_DAT1_GPIO99
M25
SDCC_DAT2_GPIO100
M26
SDCC_DAT3_GPIO101
AE3
MDP_VSYNC_SECONDA_GPIO104
AD2
MDP_VSYNC_PRIMARY_GPIO105
H25
WDOG_STB_SBCK1_GPIO0
F26
SBDT1_GPIO1
H11
PA_ON1_GPIO2
D5
GRFC9_GPIO12
J21
CAMCLK_PO_GP_MN_GPIO13 CAMCLK_24MHZ
A6
GPIO28 PWR_BTN
N19
USB_RX_DATA_GPIO29
W15
XMEM2_CS_N2_GPIO35 HCSN_ETMCLK_XTICLK
AA15
XMEM2_CS_N3_GPIO36
AE13
LCD_EN_GPIO37 FOLDER_DETECT
H9
GPIO43 AP_PON
B6
SYNTH2_GPIO65
F8
GPIO66 TP501
AA1
XMEM1_CS_N1_GPIO76 CAM_IF_PWDN BUFF_TCXO_FF
Y6
XMEM1_CS_N3_SDRAM1_CS_N1_GPIO77 EAR_SENSE_N
L25
UART3_RFR_N_GPIO87 VREG_TCXO_2.85V
H6 NC7SZ74L8X U500
UART2_DP_RX_DATA_GPIO89 C542
F18 8 1
SYNTH0_GP_PDM0_GPIO92 RTC_CONT VCC _PR 0.1u
H18
SBST1_GPIO93 EAR_MIC_LDO_EN
7 2
C545 CK _CLR
H13
TX_AGC_ADJ 33p R506
L13 6 3
TRK_LO_ADJ D Q TRK_LO_ADJ
F19
TCXO_EN_GPIO94 TCXO_EN 2K
F17 5 4
PA_ON0 PA_ON _Q GND C546
33nF
A12
Q_OUT_N TX_QM
B 12
Q_OUT TX_QP
A13
I_OUT_N TX_IM
B13
I_OUT TX_IP
F12
DAC_REF DAC_REF
W23
Q_IM_CH1 GPS_QN
U501-1 Q_IP_CH1
I_IM_CH1
V 23
V25
GPS_QP
GPS_IM
W25
I_IP_CH1 GPS_IP
AA25
MSM6280_A Q_IM_CH0
Q_IP_CH0
Y25
AB25
RX_QM
RX_QP
I_IM_CH0 RX_IM
AC25
I_IP_CH0 RX_IP
Head Set Jack Block R1114D181D U804

3 1
VREG_MSMP_2.6V
VOUT VDD
2 4
GND1 NC
5 6
GND2 CE EA R_MIC_L DO_EN
C227
10u
R214
R213
1.5K
1M
VIN- 4 5
AP_VDD_IO_1.8V VCC 1
HOOK_SENSE
18 PIN MMI 330K
VIN+ 3 G ND
2
OU T
U206
NCS2200SQ2T2G
CN201 R215
100K R216
21 CONNECTOR VBATT_SENSE PIN CHECK!!
19 1%
1 R217
WM_MIC2N
2
WM_MIC2P 470K VBATT_SENSE
3
47n
FB200 1000
4 R218 100ohm
R220
680K
EAR_L
5
EAR_R
C231
6 R219 100ohm
USB_D+
7
USB_D-
8 FB201
EAR_SENSE_N
9
VBATT
10
11 U207 +5V_PWR
REMOTE_PWR_ON
12 1 2
IN OUT
13
14 GND
15 NFM18PC104R1C3
USB_VBUS 3
16
UART_TXD
17
UART_RXD
18 U20 8
PSD12-LF
SRC DRAIN
RSB6.8CST2R
RSB6.8CST2R
INSTPAR
20 5 4
EVLC18S02003
EVLC18S02003
EVLC14S02050
EVLC14S02050
EVLC14S02050
EVLC14S02050
EVLC14S02050
22
GATE CNTRL
USFB13L D200 6 3
OUT GND DNI
7 2
33p
47p
47p
D201
1u
smd_1608h_9_r
VCC IN
8 1
C247
C244
C246
DRAIN_THERMAL
VA207
VA208
C245
VA202
VA203
VA200
VA201
9
VA205
VA204
VA206
NUS3065MUTAG
TA OVP Circuit
3. TECHNICAL BRIEF
Audio Codec(WM8753) Block

Audio Codec.
AP_VDD_IO_1.8V WM_DVDD WM_AVDD
R200
0
C202
C203
C204
C205
C206
C207
10u
0.1u
0.1u
10u
0.1u
0.1u
C864 C865
G2
H7
H6
C8
C9
A7
A8
F8
F9
J7
33p 33p
DGND
DCVDD
DBVDD
NC1
NC2
NC3
NC4
HP_SPKRGND
HPVDD
SPKRVDD
C208 1u A2 E9
WM_HPH_L LINE1 OUT4
C209 1u A1 E8
WM_HPH_R LINE2 OUT3 RECEIVER+
C210 1u B1
WM_RXP RXP
D8
C211 1u LOUT1 RECEIVER-
C2
WM_RXN RXN
C866 C867 WM_LOUT1

A3
1u
33p 33p ACIN 1u C214

B7
U201 MONO2 WM_MONO2
B3 B6 1u C219
C213
ACOP WM8753LEB-RV MONO1 WM_MONO1
D2
WM_MIC1N MIC1N C863 C862
D9
ROUT1 WM_ROUT1 51p 51p
C1
WM_MIC1P M IC 1
C220 1u E2
WM_MIC2N MIC2N
A9
C221 1u D1 LOUT2 WM_LOUT2
WM_MIC2P MIC2
MODE_GPIO3
B4 B9
CSB_GPIO5
WM_MICBIAS MICBIAS ROUT2 WM_ROUT2

GP1_CLK1
GP2_CLK2
PCMCLK
VXDOUT
DACDAT
ADCDAT
VXCLK
VXDIN
GPIO4
AGND
PGND
MCLK
PVDD
AVDD
VREF
VXFS
BCLK
SCLK
VMID
SDIN
LRC
C223
4.7u
A5
A4
A6
B5
J6
G9
H9
G8
J9
J8
J3
J1
J2
H3
J4
H4
H5
J5
F1
H1
G1
F2
E1
4.7u
4.7u
100K R209
C224
C225
100K R210
TP205
100K R211
SPK_AMP_EN
MSPTXD0
WM_DACDAT
WM_LRC
WM_BCLK
MSPTCK0
MSPTFS0
WM_MSPRXD0
WM_ADCDAT
AU_19.2M
PM_SCL
PM_SDA
VT_SW
WM_AVDD WM_DVDD
Audio Codec(WM8753) Block

AP_+VPWR
C232
AP_+VPWR
C233 C234
2.2u
10u 1u
D6
A5
B5
F1
R836 10K
C235
2.2u
CPVSS
VSS
VDD
PVDD
C236 1u
A4
C1N
A3
CPGND
A2 A6
C1P HPL EAR_L
A1 B6
1u C237 CPVDD HPR EAR_R
E3
WM_LOUT2 1u C238 INA1
E4 U209 C6
WM_ROUT2 INA2 OUTRX
1u C240 E5 MAX9775EBX+T
WM_ROUT1 INB1
1u C241 D5 C1
WM_LOUT1 INB2 OUTL+ SPK_R+
B4 E1
R843 2.2K
R844 2.2K
INC1 OUTL- SPK_R-

C5
INC2
B3 F4
VBIAS OUTR+ SPK_L+
TP813 C2 F2
PM_SDA SDA OUTR- SPK_L-
TP814 D2
PGND1
PGND2
PM_SCL SCL
CR_H
TP203 E2
CR_L
CL_H
CL_L
GND
SPK_AMP_EN _SHDN
C251
F6
D1
F3
E6
F5
B1
B2
1u
C252
C253
C254
C255
2200p
22n
2200p
22n
AUDIO SUBSYSTEM
3. TECHNICAL BRIEF
3.15 Camera interface

KT610 has two cameras : 2M Pixel CMOS and VGA Pixel CMOS Camera Below figures shows the
camera board to board connector and camera I/F signal.
3.15.1 2 Mega Camera Interface
FL402 EVRC18S03Q015050R
FL400 EVRC18S03Q015050R 1 9
1 9 CCIRID(7)_CAM INOUT_A1 INOUT_B1 CCIRID(7)
2 8
R404 0 INOUT_A1 INOUT_B1 CCIRID(6)_CAM INOUT_A2 INOUT_B2 CCIRID(6)
2 8 3 7
MCLK_27MHZ_CAM INOUT_A2 INOUT_B2 MCLK_27MHZ CCIRID(5)_CAM INOUT_A3 INOUT_B3 CCIRID(5)
3 7 4 6
I2CSDA0_CAM INOUT_A3 INOUT_B3 I2CSDA0_SW CCIRID(4)_CAM INOUT_A4 INOUT_B4 CCIRID(4)
4 6
I2CSCL0_CAM INOUT_A4 INOUT_B4 I2CSCL0_SW
G1
G2
G1
G2
5
10
5
10
10
5
FL401 EVRC18S03Q015050R
G1
G2
1 9
CCIRID(3)_CAM INOUT_A1 INOUT_B1 CCIRID(3) CCIRIHS_CAM INOUT_A4 INOUT_B4 CCIRIHS
2 8 4 6
CCIRID(2)_CAM INOUT_A2 INOUT_B2 CCIRID(2) CCIRIVS_CAM INOUT_A3 INOUT_B3 CCIRIVS
3 7 3 7
CCIRID(1)_CAM INOUT_A3 INOUT_B3 CCIRID(1) CCIRICLK_CAM INOUT_A2 INOUT_B2 CCIRICLK
4 6 2 8
CCIRID(0)_CAM INOUT_A4 INOUT_B4 CCIRID(0) CAMCLK_24MHZ_CAM INOUT_A1 INOUT_B1 CAMCLK_24MHZ
1 9
R405 0
G1
G2
FL403 EVRC18S03Q015050R
5
10
Figure. Schematic of 2 Mega Camera EMI/ESD filter I/F
AP_VDD_CAM_AVDD_2.7V
AP_VDD_CAM_IO_2.7V
AP_VDD_CAM_1.8V
2M CAM Connector
HB-1M1005-601JT
HB-1M1005-601JT
HB-1M1005-601JT
CN402
G1 G2
1 24
2 23
FB400
FB402
CCIRID(7)_CAM I2CSCL0_CAM
FB401
3 22
CCIRID(6)_CAM I2CSDA0_CAM
4 21
CCIRID(5)_CAM
5 20
CCIRID(4)_CAM CCIRIVS_CAM
6 19
CCIRID(3)_CAM CCIRIHS_CAM
7 18
CCIRID(2)_CAM CAMCLK_24MHZ_CAM
8 17
CCIRID(1)_CAM
9 16
CCIRID(0)_CAM
10 15
CCIRICLK_CAM
11 14
2M_RSTN
12 13
2M_PWDN
C409 TP400
C412
C415
C411
C410
C413
C414
G3 G4
0.1u
0.1u
0.1u
0.1u
10u
10u
10u
Figure. Schematic of 2 Mega Camera Board to Board Connector
3. TECHNICAL BRIEF
No Pin Name I/O Description

1 GND GND GND
2 D7 O Pixel Clock
3 D6 O Ground
4 D5 O Ground
5 D4 O Initializes sensor, Active Low
6 D3 O Ground
7 D2 O Non-connection
8 D1 O Data for two-wire serial interface
9 D0 O Clock for two-wire serial interface
10 PCLK O Non-connection
11 RSTN I Non-connection
12 PWDN I Ground
13 GND GND Power down mode, active High
14 VDDD 1.8V P Actuator Voltage
15 VDDIO 2.8V P Actuator Voltage
16 VDDA 2.8V P Analog Voltage
17 GND GND Analog Voltage
18 MCLK I Horizontal Synchronous signal
19 HSYNC O Vertical Synchronous signal
20 VSYNC O Ground
21 GND GND Master clock
22 SDA I/O Ground
23 SCK I Image data output
24 GND I Image data output
Table. Interface between 2M Camera Module and Main Board (in camera module)
The 2M Camera module is connected to main board with 34pin Board to Board connector
(AXK8L34125). Its interface is dedicated camera interface port in STN8810 and MSM6280.
The camera port supply 24MHz master clock to camera module and receive 40.078MHz pixel clock
(max.15fps), vertical sync signal, horizontal sync signal, reset signal and 8bits data from camera
module. The camera module is controlled by I2C port from STN8810.
3. TECHNICAL BRIEF
3.15.2 VGA Camera Interface
AP_VDD_IO_2.7V AP_+VPWR
MAIN-FOLDER CON-SOCKET
CN400
G 2 G1
70 1
0 R400 LCD_NRESET
69 2
MOT_PWR- 0 R401 LCD_VS
68 3
KEY_ON_SW_N LCD_DATA_O_6
67 4
KPD_FOLDER_DRV_N LCD_DATA_O_4
66 5
WLED_nRST LCD_DATA_O_2
65 6
LCD_DATA_O_0
64 7
MCLK_27MHZ_CAM LCD_DATA_O_8
63 8
LCD_DATA_O_10
62 9
CCIRICLK LCD_DATA_O_12
61 10
CCIRIHS LCD_DATA_O_14
60 11
CCIRIVS LCD_DATA_O_15
59 12
CCIRID(7) LCD_DATA_O_13
58 13
57 14
56 15
55 16
54 17
53 18
52 19
CCIRID(0) R402 0 SDIS_CSN_O
51 20
VGA_STANDBY DIS_WEN_O
50 21
VGA_RSTN 0 R403 MDIS_CSN_O
49 22
I2CSDA0_CAM DIS_RS_O
48 23
C400 I2CSCL0_CAM
47 24
1u
46 25
I2CSCL0
45 26
I2CSDA0
44 27
43 28
KEY_ROW(0) RECEIVER-
42 29
KEY_ROW(1) RECEIVER+
41 30
KEY_ROW(2)
40 31
KEY_ROW(3) SPK_R+
39 32
KEY_ROW(4) SPK_R-
38 33
KEY_ROW(5)
37 34
KEY_COL(6) SPK_L-
36 35
KEY_COL(7) SPK_L+
G4 G3
C401 C402
1u AXT570124 1u
C403 C404 C405 C406 C407 C408
47p 47p 22p 22p 22p 22p
Figure. Schematic of Main-Folder B to B connector (in main BD)
AP_VDD_CAM_2.8V AP_VDD_CAM_1.8V
VGA_CAMERA
CN100
1 20
VGA _STA NDB Y
FL 100 EVRC18S03Q015050R 2 19
1 9 3 18
MCL K _27MHZ_CA M INOUT_A 1 INOUT_B 1 VGA _RSTN
2 8 4 17
CCIRICL K INOUT_A 2 INOUT_B 2 I2CSCL 0_CA M
3 7 5 16
CCIRID(0) INOUT_A 3 INOUT_B 3 I2CSDA 0_CA M
4 6 FL 101 EVRC18S03Q015050R
6 15 FL 102 EVRC18S03Q015050R
CCIRID(1) INOUT_A 4 INOUT_B 4
1 9 7 14 1 9
CCIRID(2) INOUT_A 1 INOUT_B 1 INOUT_A 1 INOUT_B 1 CCIRIHS
G1
G2
2 8 8 13 2 8
CCIRID(3) INOUT_A 2 INOUT_B 2 INOUT_A 2 INOUT_B 2 CCIRIVS
9 12
5
10
3 7 3 7
CCIRID(4) INOUT_A 3 INOUT_B 3 INOUT_A 3 INOUT_B 3 CCIRID(7)
4 6 10 11 4 6
G1
G2
G1
G2
A XK 720147
5
10
5
10
Figure. Schematic of VGA Camera Board to Board Connector (in Main-Folder FPCB)
3. TECHNICAL BRIEF
The VGA Camera module is connected to main slider FPCB with 20pin Board to Board
connector(AXK820145). The main slider FPCB is connected to main board with 70pin board to board
connector.
Its interface is dedicated camera interface port in STN8810. The camera port supply 27MHz master
clock to camera module and receive 13.5MHz pixel clock (max. 15fps), vertical sync signal, horizontal
sync signal, reset signal and 8bits data from camera module.
The camera module is controlled by I2C port from STN8810.
No Name Type Description

1 ENABLE I Active ‘High’
2 MCLK I Master Clock
3 GND GND Ground
4 PCLK O Video Output Clock D [0:7]
5 D0 O Imaga Data [0]
13 VSYNC O Vertical Synchronization
14 HSYNC O Horizontal Synchronization
15 GND GND Ground
16 SDA I/O Data for two wire serial interface
17 SCL I Clock for two wire serial interface
18 RESET I Reset initializes sensor Active Low
19 DVDD P Digital core circuit power supply voltage
20 AVDD &IOVDD P Analog core circuit power supply voltage &
Digital I/O circuit power supply voltage
Table. Interface between Camera Module and Main Board (in camera module)
3. TECHNICAL BRIEF
3.15.3 LCD backlight / Power of VGA Camera

U100(in Key PCB) is a charge pump. This module supply the 1.8V and 2.8V power to VGA camera.
This part is controlled by I2C of STN8810.
A P_+VPWR
C100
C101
C102
1u
1u
1u
D6
C6
C5
C4
B5
A4
A5
C1N
C1P
C2N
C2P
C3N
C3P
CPGND
B6 B4
VB A TCP VOUT L ED_A NODE
A P_VDD_IO_2.7V F3
VB A T1
E3 A3
VB A T2 L ED1 ML ED 1
B3
L ED2 ML ED 2 C103
A2
L ED3 ML ED 3 4.7u
B1
L ED4 ML ED 4
B2 A P_+VPWR
WGND
U100 L ED5
C1
ML ED 5
E6 D1
VIO L ED6 SL ED1
B D6085GUL L ED7
D2
SL ED2
C2
C105 1u FL GND
D3
10u C104 WL ED_n RST RESETB
D5 F5
I2CSDA 0 SDA VB A TL DO1
D4 F2 A P_VDD_L CD_2.7V
I2CSCL 0 SCL VB A TL DO2
AP_VDD_CAM_1.8V
EVLC14S02050
EVLC14S02050
EVLC14S02050
E5 AP_VDD_CAM_2.8V
L DO1O 1u
E1 TP100
L DO2O C106
E4
L DO3O
F4 E2
A GND L DO4O
T1
T2
T3
T4
F6
F1
A1
A6
VA11 2
VA113
VA111
1u 1u 1u
C107 C108 C109
L CD_B ac k l i g h t d r i v er
Figure. Schematic of charge pump
3. TECHNICAL BRIEF
3.15.4 LCD module
Hinge
CPU LCD module
WLED_NRST BD6085
2 LCD Backlight DriverAP_VDD_LCD_2.7V
I2C &
LDO
Main backlight control

Main LCD
2.4íí QVGA
Data[15:0] 16
nM_CS
nWE EMI/ESD filter
RS
nRESET
LCD_VSYNC
Sub LCD
nS_CS EMI/ESD filter 1.45íí 160X64
SUB backlight control
Figure. LCD I/F Block Diagram
3. TECHNICAL BRIEF
3.15.5 Display
LCD module (With Main and Sub LCD)) is connected to FPCB with 50-pin connector(AXK8L50125).
The LCD is controlled by 16-bit in STN8810.
CN400
G 2 G1
70 1
0 R400 LCD_NRESET
69 2
68 3
67 4
66 5
WLED_nRST LCD_DATA_O_2
65 6
LCD_DATA_O_0
64 7
MCLK_27MHZ_CAM LCD_DATA_O_8
63 8
LCD_DATA_O_10
62 9
CCIRICLK LCD_DATA_O_12
61 10
CCIRIHS LCD_DATA_O_14
60 11
CCIRIVS LCD_DATA_O_15
59 12
58 13
57 14
56 15
55 16
54 17
53 18
52 19
CCIRID(0) R402 0 SDIS_CSN_O
51 20
VGA_STANDBY DIS_WEN_O
50 21
VGA_RSTN 0 R403 MDIS_CSN_O
49 22
I2CSDA0_CAM DIS_RS_O
48 23
C400 I2CSCL0_CAM
47 24
1u
46 25
I2CSCL0
45 26
I2CSDA0
44 27
43 28
42 29
41 30
KEY_ROW(2)
40 31
KEY_ROW(3) SPK_R+
39 32
KEY_ROW(4) SPK_R-
38 33
KEY_ROW(5)
37 34
KEY_COL(6) SPK_L-
36 35
KEY_COL(7) SPK_L+
G4 G3
C401 C402
1u AXT570124 1u
C403 C404 C405 C406 C407 C408
47p 47p 22p 22p 22p 22p
Figure. Schematic of Main-Folder FPCB B to B connector (in main BD)
L CD_CONNECTOR
CN103
51 52
1 50
R? 22 2 49
RECEIVER+ SPK _R+
R? 22 3 48
RECEIVER- SPK _R-
4 47
5 46 TP100
PUL L _DOWN
6 45
L CD_DA TA _O_1 L CD_DA TA _O_0
7 44
8 43
9 42
10 41
11 40
12 39
13 38
14 37
PUL L _UP DIS_WEN_O
15 36
SDIS_CSN_O DIS_RS_O
16 35
MDIS_CSN_O TP101
17 34 A P_VDD_L CD_2.7V
L CD_VS L CD_NRESET
18 33
19 32
L ED_A NODE
20 31
ML ED5
21 30
M L ED4
22 29
ML ED3 L ED_A NODE
23 28
ML ED2 SL ED2
24 27
ML ED1 SL ED1
25 26
53 54
A XK 8L 50125
Figure. Schematic of LCD connector (in Key PCB)
3. TECHNICAL BRIEF
Table. Interface between LCD Module and Main Board (in camera module)
3. TECHNICAL BRIEF
3.16 Bluetooth
KT610 supported bluetooth, which is possible to data file transfer, BT headset call.
CPU (STn8810) interfaces with bluetooth one chip module (U100 in Sub) which includes RF and
baseband.
The STLC2500C is a single chip ROM-based Bluetooth solution for applications requiring integration
up to HCI level.
The STLC2500C's main interfaces are UART for HCI transport between CPU (STn8810) and bluetooth
module, PCM for voice between audio codec.(WM8753) and bluetooth module and GPIOs for control
purposes . Voice data is transferred to CPU(STn8810) through audio codec.(WM8753).
The radio has been designed specifically for single chip requirements and for low power consumption.
Radio signal from bluetooth antenna (ANT100 in Sub) is transferred to bluetooth module through
BALUN filter (FL100). Bluetooth module has its’ own oscillator (X100,27MHz) for normal operation and
use sleep clock(32.768KHz) from PM6658 (PMIC of MSM 6280).
■ Bluetooth™‚ specification compliance: V2.0
■ Transmit Power : Power Class2
■ Ultra low power architecture with 3 different low power levels:
- Sleep Mode
- Deep Sleep Mode
- Complete Power Down Mode
Figure. Diagram of STLC2500C
3. TECHNICAL BRIEF
3.17 Main Features
3.17.1 Main features of KT610

- Communicator Type
- WCDMA(2100) + GSM(900,1800) + PCS(1900) Triple mode
- Main LCD: 320 x 240, 65K (2.4”)
- Sub LCD : 160 x 64, (1.45”)
- 2.0M Pixel CMOS Camera
- VGA CMOS Camera
- 10 x 18 φ speaker (2ea)
- Stereo Headset
- Video telephony in WCDMA with camera
- HSDPA up to 3.6Mbps
- Loud Speaker phone (in GSM and WCDMA)
- 64 Poly Sound
- MP3/AAC/WMA decoder and play
- MPEG4 encoder/decoder and play/save
- H.263 decoder
- JPEG en/decoder
- Support Bluetooth, USB
- 108.9 x 53.9 x 17.2 mm
- 950mAh hard pack
3. TECHNICAL BRIEF
3.18 Main Component
3.18.1 Main Components of KT610
LCD FPCB,
MAIN Top Side MAIN Bottom Side L Speaker,
Vibrator
VGA camera 2M camera
SUB Bottom Side SUB Top Side
Internal Antenna
KEY Top Side KEY Bottom Side

LCD, R Speaker, Receiver
3. TECHNICAL BRIEF
3.18.1.1 Main Top Side
U402
LED
Side Key
Reference Description
U402 Folder_Sense IC
3. TECHNICAL BRIEF
3.18.1.2 Main Bottom Side
CN201
U208
ANT605
CN200
U603
CN402
Q800
U302
X800
U801 CN800
Q801 U200
U500
U400
U204
U203
U300
U301 J300
U800 U304
U501 U401
CN400
U100
X300
X601
U305 U209
U303 U803
U602 U201
U601
SW601
U604
MIC200
3. TECHNICAL BRIEF
Reference Description Reference Description
ANT605 GPS Antenna CN201 Connector (I/O, Ear jack, Power)
U603 RF LNA Module U208 FET (OVP)
Q800 FET (OVP) CN200 B To B Connector
X800 32.768KHz Oscillator CN402 2M CAM Connector
U801 PM6658 U302 AP PMIC
Q801 FET (OVP) CN800 Main Battery Connector
U500 D Flip-Flip U200 Level Shifter

U204 U204 U400 Key Scan Controller
U300 Dual SPDT analog Switch U203 UART Switch
U301 Level Shifter J300 USIM Connector
U800 MP Memory U304 LDO Regulator
U501 MSM6280 U401 Power Inductor
X601 19.2M TCXO CN400 70 Pin Connector
U100 STN8810 X300 19.2MHz Oscillator
U305 Dual 2 Input And Gate U209 Audio Subsystem
U303 LDO Regulator U803 Single SPDT Analog Switch
U602 RTR6285 U201 Audio Codec.

U601 RF Tx Module SW601 RF ADAPTER
U604 RF PAM MIC200 Microphone
3. TECHNICAL BRIEF
3.18.1.3 SUB Top Side
ANT100 BAT100
CN100 S100
3.18.1.4 SUB Bottom Side
X100
U101

ANT100 Bluetooth Ant. BAT100 Back Up Battery
CN100 SUB to MAIN Connector S100 Micro-SD Card Socket
X100 19.2MHz Oscillator U101 Bluetooth Module
3. TECHNICAL BRIEF
3.18.1.5 KEY Top Side
LED
SW115
3.18.1.6 KEY Bottom Side
U100
CN100
SW115 Dome Switch CN100 FCPB to Key PCB Connector
U100 LCD Backlight Driver LED Back light LED
3. TECHNICAL BRIEF
3.18.1.7 LCD FPCB
Speaker
Vibrator
CN103
CN101
Speaker Speaker CN103 FPCB to LCD Connector
Vibrator Vibrator CN101 MAIN-SLIDER CON-SOCKET
4. TROUBLE SHOOTING
4. TROUBLE SHOOTING
4.1 RF Component
RF component (WCDMA / GSM)
U601 EDGE PAM(2G PAM+ASM) FL603 PCS RX SAW
U602 GSM/WCDMA Transceiver FL605 WCDMA Duplexer
U604 WCDMA PAM FL606 WCDMA RX SAW
U802 Coupler FL607 WCDMA TX SAW
FL601 GSM RX SAW SW601 RF Antenna Connector
FL602 DCS RX SAW
4. TROUBLE SHOOTING
ANT605
U603
FL604
RF component (GPS)
Reference Description
ANT605 GPS ANTENNA
U603 GPS LNA
FL604 GPS SAW FILTER
4. TROUBLE SHOOTING
4.2 SIGNAL PATH
GSM/DCS/PCS Rx Tx PATH
A. GSM/DCS/PCS Rx PATH
B. GSM/DCS/PCS Tx PATH
4. TROUBLE SHOOTING
WCDMA RX/ TX PATH
C. WCDMA Rx PATH
D. WCDMA Tx PATH
4. TROUBLE SHOOTING
GPS Signal PATH
E. GPS Rx PATH
4. TROUBLE SHOOTING
4.3 Checking TCXO Block

The output frequency (19.2MHz) of TCXO (X601) is used as the reference one of RTR6285 and
PM6658 internal VCO.
TP1
TP2
TP3
TCXO
C677 1000p DSA321SCE-19.2M X601
TCXO_PM TP3
7
NC3 NC2
6
TP2
NC4 NC1
8 5
C679 1000p
RTR6275_TCXO OUTPUT GND
3 2
R612 100ohm
VREG_TCXO_2.85V VCC VCONT TRK_LO_ADJ
4 1
C687 C688 C689
0.1u 1000p 10n
0603 TP1 0603
Schematic of the Crystal Part (19.2MHz)
4. TROUBLE SHOOTING
Check TP1
VCC of TCXO
No
VCC 2.8 V Check PM6658
Yes
Check TP2
No
2.4V Voltage 0.4V Check MSM6280
Yes
Check TP3
No
Check soldering and
19.2 MHz Signal
components
Yes
TCXO is OK
4. TROUBLE SHOOTING
4.4 Checking Ant. Switch Module Block
VBATT (TP1)
U601
Ant_Sel2
Ant_Sel1 Ant_Sel0
KMS-518
ANT601 SW601
2.7nH
C
A
C603
C602
G1
G2
C604 56p
100p
ANT606
L602 C609
C608 15nH 100nH
1.2p
ANT_SEL2
SKY77519 U601
28 8
ANT_SEL0 27
BS1 ANT
ANT_SEL1 BS2
1
TXEN
26 2
1000p C620 VBATT MODE
C618 1000p1000p 3
RSVD
C619 25
VAPC
TP1 23
RX4
4
5
GSM_IN RX3
6
RX2
21 7
DCS_PCS_IN RX1
10
WCDMA1
24
VBATT GND13
C625 22 9
C629 GND12 GND1
10u 20 11
51p GND11 GND2
19 12
GND10 GND3
18 13
GND9 GND4
17 14
GND8 GND5
16
GND7
15 29
GND6 PGND
2.2K R601
GSM_PA_RAMP
C644
68p
Schematic of the Antenna Switch Block
4. TROUBLE SHOOTING
Logic Table of the Antenna Switch
Switch Mode ANT_SEL0 ANT_SEL1 ANT_SEL2
GSM900 TX LOW LOW LOW
GSM1800/1900 TX LOW LOW LOW
GSM900 RX LOW LOW LOW
WCDMA LOW LOW LOW
Checking Switch Block Power Source
Check ANT_SEL0, 1, 2
High Level
No
1.2V < Voltage < 7V Check TP1 VBATT
Yes
Check the Logic

In each mode
4. TROUBLE SHOOTING
4.5 Checking WCDMA Block
START
1
2, 5
1. Check TCXO 19.2 MHz
3, 4
2. Check ASM Block
Refer to 1.4
3. Check RF Tx Level
4. Check PAM Block

Refer to 1.5.4
5. Check RF Level
6. Re-download SW & Cal.
4. TROUBLE SHOOTING
4.5.1 Checking TCXO Block

Refer to 1.3
4.5.2 Checking ASM Block

Refer to 1.4
4.5.3 Checking RF TX Level
TP1
TP3
TP2
TP4
Test Point (TX Level)
4. TROUBLE SHOOTING
KMS-518
TP1
ANT601 SW601
2.7nH
C
A
C603
C602
G1
G2
C604 56p
100p
ANT606
L602 C609
C608 15nH 100nH
1.2p
ANT_SEL2
SKY77519 U601
28 8
ANT_SEL0 27
BS1 AN T
ANT_SEL1 BS2
1
TXEN
26 2
C618 1000p1000p 3
RSVD
C619 25
VAPC
4
RX4
23 5
GSM_IN RX3
6
RX2
21 7
DCS_PCS_IN RX1
VBATT
24
GND13
WCDMA1
10
TP2
C625 22 9
C629 GND12 GND1
10u 20 11
51p GND11 GND2
19 12
GND10 GND3
18 13
GND9 GND4
17 14
GND8 GND5
16
GND7
15 29
GND6 PGND
2.2K R601
GSM_PA_RAMP
C644
68p
TP3
1.2nH
C698
VBATT
C696
2.2u
LDC151G9520Q-359 U802
C857 1.8p
1
1p L629
C700 C701
OUT
IN
1000p 100p
TP4
COU
TER
ACPM-7381 U604
4
11
PGND
10 1
VCC2 VCC1
9 2
51 GND3 RFIN
8 3
R839
PWR_DET RFOUT VMODE1

51
R840 7 4
GND2 VMODE0 PA_R0
6 5
R837
R838
GND1 VEN
120
120
7.8 dB C861
Atten. 100p
C704
100p
PA_ON
4. TROUBLE SHOOTING
For testing, Max power output is needed.
Check ANT_SEL 0, 1, 2
(High, Low, Low)
Check TP1 Yes

RF Tx Level is OK
Over 21 dBm ?
No
Yes
Check TP2
Check ASM
Over 21 dBm ?
No
Yes
Check TP3
Check Duplexer
Over 21 dBm ?
No
Yes
Check TP4
Check RTR6285
Over 7 dBm ?
No
Check PAM Block

Refer to 1.5.4
RTR6285 Maximum output Power = 7 dBm

RTR6285 minimum output Power = -80 dBm
PAM(ACPM-7381) = Maximum input Power = 10 dBm
4. TROUBLE SHOOTING
4.5.4 Checking PAM Block
PAM control signal

PA_ON : PAM Enable
PA_RO: PAM Gain Control
PAM_IN PAM_OUT
PA_ON must be HIGH (over 2.6V)
PAM IN/OUT Signal :

When PAM is under the operation of high power mode (PA_R0:Low),
PAM OUT power must be over 21 dBm
PAM IN power must be under 10 dBm
4. TROUBLE SHOOTING
TP1 TP2 TP3
TP3
1.2nH
C698
VBATT
C696
2.2u
LDC151G9520Q-359 U802
C857 1.8p
1
1p L629
C700 C701
OUT
IN
1000p 100p
TP1
COU
TER
ACPM-7381 U604
TP2
4
11
PGND
10 1
VCC2 VCC1
9 2
51 GND3 RFIN
8 3
R839

51
R840 7 4
GND2 VMODE0 PA_R0
6 5
R837
R838
GND1 VEN
120
120
7.8 dB C861
Atten. 100p
C704
100p
PA_ON
4. TROUBLE SHOOTING
Set the phone Tx is ON and

PDM is 210
Check TP3 Yes

RF Tx Level is OK
Over 21 dBm ?
No
Yes
Check TP2
Check MSM6280
PA_R0 2.6 V
No
Yes
Check TP1
Check RTR6285
Over 10 dBm?
No
Change the board
4. TROUBLE SHOOTING
4.5.5 Checking RF Rx Level
TP3
TP1
TP4
TP2
Test Point (RF Rx Level)
4. TROUBLE SHOOTING
KMS-518
TP1
ANT601 SW601
2.7nH
C
A
C603
C602
G1
G2
C604 56p
100p
ANT606
L602 C609
C608 15nH 100nH
1.2p
ANT_SEL2
SKY77519 U601
28 8
ANT_SEL0 27
BS1 ANT
ANT_SEL1 BS2
1
TXEN
26 2
C618 1000p1000p 3
RSVD
C619 25
VAPC
4
RX4
23 5
GSM_IN RX3
6
RX2
21 7
DCS_PCS_IN RX1
VBATT
24
GND13
WCDMA1
10
TP2
C625 22 9
C629 GND12 GND1
10u 20 11
51p GND11 GND2
19 12
GND10 GND3
18 13
GND9 GND4
17 14
GND8 GND5
16
GND7
15 29
GND6 PGND
2.2K R601
GSM_PA_RAMP
C644
68p
4
3
PGND
ANT
ACMD-7602
FL605
RX
TX
TP3
1
2
L626 1.2nH
Rx Tx
L625 2.7p
RX_WCDMA_2100
LDC151G9520Q-359 U802
L628
1.5nH
1
2
OUT
IN
COU
TER
4
WCDMA LNA CIRCUIT

C693 L624
5.6nH 3nH WCDMA_MIX_IN_M

EFCH2140TDE1
FL606
2 3
C697 2.2p C699
G1 O1
WL NA _OUT IN 0.75p
1 G2 O2
5 4
L630 L631
5.6nH 3nH
WCDMA_MIX_IN_P
TP4
4. TROUBLE SHOOTING
Bias Block
WPRXSE2_OUT
WPRXSE1_OUT
WB_MX_INM
WB_MX_INP
PGND
VREG_RF_SMPS_2.1V
69
34
35
28
29
L623
C694 C695
2nH
R614
0.1u 100p
1K
C673
22p
0603
WCDMA_MIX_IN_P
WCDMA_MIX_IN_M
WLNA_OUT
4. TROUBLE SHOOTING
Set the Phone Rx is ON
No
Check BIAS over
Check bias block soldering
2.1 V ?
Yes
No
Check TP1
Check RF Switch (M/S)
Signal exist ?
Yes
Check TP2 No Check ASM Block

Signal exist ? Refer 1.4
Yes
No
Check TP3
Check Duplexer
Signal exist ?
Yes
No
Check TP4 Check RTR6285 and
Signal exist ? Rx SAW filter
Yes
Change the board
4. TROUBLE SHOOTING
4.6 Checking GSM Block
Start
1. Check TCXO Block
2. Check ANT.SW Module
2
3
3. Check RF TRX Level
4. Re-download SW & Cal.
4. TROUBLE SHOOTING
4.6.1 Checking TCXO Block

Refer to 1.3
4.6.2 Checking ASM Block

Refer to 1.4
4.6.3 Checking RF TX Level
TP1
TP2
TP3
4. TROUBLE SHOOTING
KMS-518
TP1
ANT601 SW601
2.7nH
C
A
C603
C602
G1
G2
C604 56p
100p
ANT606
L602 C609
C608 15nH 100nH
1.2p
ANT_SEL2
SKY77519 U601
28 8
ANT_SEL0 27
BS1 ANT
ANT_SEL1 BS2
1
TXEN
26 2
C618 1000p1000p 3
RSVD
C619 25
VAPC
4
RX4
23 5
GSM_IN RX3
6
RX2
21 7
DCS_PCS_IN RX1
10
WCDMA1
24
VBATT GND13
C625 22 9
C629 GND12 GND1
10u 20 11
51p GND11 GND2
19 12
GND10 GND3
18 13
GND9 GND4
17 14
GND8 GND5
16
GND7
15 29
GND6 PGND
2.2K R601
GSM_PA_RAMP
C644
68p
WCDMA2100
R605
TP2 GSM_TX
91
R606 12.0 dB R607
82 82
Atten.
R608
TP3 DCS_PCS_TX
47
R609 R610
130 6.8 dB 130
Atten.
4. TROUBLE SHOOTING
Start
Check TCXO Block

Refer to 1.3
No
Check TP1 Yes GSM/DCS/PCS

If GSM over 31 dBm ? Tx is OK
If DCS/PCS over 28 dBm ?
Check other part
No
Check TP2, 3 Yes Check Ant.SW Block

If GSM(TP2) under 6 dBm ? (ASM+EDGE PAM)
If DCS/PCS(TP3) under 6 dBm ?
Refer to 1.4
No
No Problem
Check RTR & PAD Check soldering and

components
Still exist Problem
Change the board
4. TROUBLE SHOOTING
4.6.4 Checking RF Rx Block
GSM900 PCS1900
DCS1800
L601 8.2nH
5 4
G2 O2 L603 L604
IN
1 G1 O1 18nH 68nH
3FL0F00
SAFEB9242M
FL601
L606 8.2nH GSM Band

925-960MHz
L607 3.3nH
5 4
G2 O2 L608 L609
IN
1 G1 O1 12nH 10nH
SAFEB12G843FA0F00
FL602
L610
3.3nH
L611 3.3nH DCS Band
1805-1880MHz
L612 1.2nH
5 4
G2 O2 L613 L614
IN
1 G1 O1 8.2nH 6.8nH
SAFEB12G963FA0F00
FL603
L615
GPS_IN
3.3nH
L618 1.2nH
1.5p
L617
PCS Band
1930-1990MHz
Schematic of GSM/DCS/PCS Rx Block
4. TROUBLE SHOOTING
TP2
TP3
TP1
KMS-518
TP1
ANT601 SW601
2.7nH
TP2 L601 8.2nH
C
A
C603
C602
G1
G2
C604 56p
100p
GSM
C607
ANT606
30p
5 4
L602 C609 G2 O2 L603 L604
IN
C608 15nH 100nH 1 G1 O1 18nH 68nH
1.2p
3FL0F00
SAFEB9242M
FL601
L606 8.2nH
ANT_SEL2
SKY77519 U601
28 8
ANT_SEL0 27
BS1 ANT
ANT_SEL1 BS2
1 L607 3.3nH
TXEN
26 2
C618 1000p1000p 3
RSVD
C619 25
DCS
C622
VAPC
2.7p
4 5 4
RX4
23 5 G2 O2 L608 L609
GSM_IN RX3 IN
6 1 G1 O1 12nH 10nH
RX2
21 7 SAFEB12G843FA0F00
DCS_PCS_IN RX1 FL602
10 L610
WCDMA1
24 3.3nH
VBATT GND13
C625 22 9 L611 3.3nH
C629 GND12 GND1
10u 20 11
51p GND11 GND2
19
18
17
GND10
GND9
GND8
GND3
GND4
GND5
12
13
14
TP3
16
GND7
15 29
GND6 PGND
2.2K R601 L612 1.2nH
GSM_PA_RAMP
C644
PCS
C645
68p
2.2p
5 4
G2 O2 L613 L614
IN
1 G1 O1 8.2nH 6.8nH
SAFEB12G963FA0F00
FL603
L615
3.3nH
L618 1.2nH
WCDMA2100
Schematic of GSM/DCS/PCS Rx Block
4. TROUBLE SHOOTING
Set the Phone Rx is ON
Check TP1 No
Check RF Switch (M/S)
Signal exist ?
Yes
Check TP2 No Check ASM Block

Signal exist ? Refer 1.4
Yes
No
Check TP3 Check RTR6285 and
Signal exist ? Rx SAW filter
Yes
Change the board
4. TROUBLE SHOOTING
4.7 Power on trouble

Power on sequence of KT610 is :
PWR key press → KEY_ON_SW_N go to low (D405, PM6658 KPD_PWR_N) → PM6658
Power Up → VREG_MSMC_1.2V(C802), VREG_MSME_1.8V(C831),
VREG_MSMP_2.6V(C825), VREG_MSMA_2.6V(C824), VREG_TCXO_2.85V(C823) power
up → PON_RESET_N assert to MSM and assert to STn8810 → AP_VDD_IO_2.7V(C326),
AP_VDD_IO_1.8V(C304), AP_VCORE(C307), AP_VPLL(C313), AP_VFUSE(C314) power
up → CPU and Phone booting & PS_HOLD(D801) assert High to PMIC(PM6658)
Start
Battery voltg. higher NO Changing or charging the

than 3.22V? Battery
YES
Press PWR key NO Follow the LED trouble
Keypad LED on? shoot
YES
ZD404 high to low NO Check open Pattern
when key press? of power button
YES
VREG_MSMC_1.2V,
VREG_MSMP_2.6V, VREG_MSME_1.8V NO
VREG_TCXO_2.85V,
Change the Main board
VREG_MSMA_2.6V power up?
YES
Is clock ok?
NO
X300 : 19.2M Check the TXCO
X800 : 32.768Khz
YES
4. TROUBLE SHOOTING
X800 (32.768 KHz)

VREG_MSMP_2.6V (C825)
AP_VFUSE (C314) AP_VPLL (C313)
VREG_MSMA_2.6V (C824)
VREG_MSME_1.8V (C831)
AP_VCORE (C307)
PS_HOLD (D801)
VREG_MSMC_1. 2V (C802) VDD_IO_1.8V (C304)
VREG_TCXO_2.85V (C823)
<TOP Side>
X601 (TCXO)
VDD_IO_2.7V(C326)
X300 (19.2MHz OSC)
KEY_ON_SW_N (ZD404)
4. TROUBLE SHOOTING
4.8 USB trouble

USB Initial sequence of KT610 is :
USB connected to KT610 → USB_VBUS(VA203) go to 5V → USB_OVP_G enable(Q801 Pin#3 high)
USB_VBUS_IN go to 5V (Q801 Pin#4) → USB_D+(VA200) go to 3.3V → USB_DATA is triggered →
USB work
Start
NO
Cable is insert? Cable insert
YES
NO Check VA203, Q801
USB_VBUS is about
to 5V? USB cable
YES
NO
USB_D+ is about to 3.3V? Check VA200
YES
VA200 (USB_D+)
VA203(USB_VBUS)
Q801
4. TROUBLE SHOOTING
4.9 SIM detect trouble

USB Initial sequence of KT610 is :
VREG_USIM_2.85V(C830 of PM6658) go to 3.0V → USIM clock, reset and data triggered →
USIM IF work (Schematic and place are refer to SIM technical brief)
Start
Re-insert the SIM card
Yes
Work well? End
No
NO Check J300, C830,
VREG_USIM_2.85V is 3.0V?
USIM_P_CLK is run? C320,C321,
R307,L302
YES
Change SIM card
Yes
Work well? End
No
C320 (USIM_P_RST_N)
C321
(USIM_P_CLK)
C322 (VREG_USIM_2.85V)
R307 (USIM_P_DATA)
J300
4. TROUBLE SHOOTING
4.10 Key sense trouble

Key Sense sequence of KT610 is :
Default condition ROW(0-7) is 2.7V → Press the key → Corresponding ROW(x) and COL(x) go to 0V
→ Key sensing by key coder IC (U400) → Key coder IC send the key information to CPU by I2C
interface
START
Check the RA400 with no key press

Side Key
NO
ROW(0-4) is 2.7V? Check RA400 , RA401
Yes
Check the RA400, RA401 with key press
Check Metal
ROW(0-7), Yes DOME SHEET
COL(0-7) is 0V? Sub & Main
board
NO
Change the side key
Work well?
YES
NO
Change FPCB
NO
Work well?
YES
NO Dome sheet
Change Key PCB
NO
Work well?
YES
NO
Check R406,R407,C416,R856,R851
Work well?
YES
NO
Change the Main board End
4. TROUBLE SHOOTING
AP_VDD_IO_2.7V
R856
RA400 RA400,
R851
2
4
6
8
2
4
6
8
RA400 100K
RA401 100K
RA401
1 2
1
3
5
7
1
3
5
7
SW400 SW401
R856, KEY_ROW(0)
R856
100o h m 5 6
SW407 SW408
R851 KEY_ROW(1)
9 0
SW413 SW414
R851
KEY_ROW(2)
100o h m E R
SW419 SW420
KEY_ROW(3)
U400 U
SW425
I
SW426
KEY_ROW(4)
S K
SW431 SW432
KEY_ROW(5)
J D
SW437 SW438
KEY_ROW(6)
C V
SW445 SW446
KEY_ROW(7)
KEY_COL(0)
KEY_COL(1)
KEY_COL(2)
KEY_COL(3)
KEY_COL(4)
KEY_COL(5)
C417 R406 R407 KEY_COL(6)

KEY_COL(7)
EVLC14S02050
EVLC14S02050
RA401
VA402
VA805
AP_VDD_IO_2.7V
KEYCODER IC
R406 R407
R406
R407
KEY_ROW(0:7)
3.3K
3.3K
KEY_ROW(1)
KEY_ROW(0)
KEY_ROW(3)
KEY_ROW(2)
I2CSCL1
KEY_ROW(7)
KEY_ROW(6)
KEY_ROW(5)
KEY_ROW(4)
I2CSDA1
G6
G7
C7
D7
D6
C2
C1
C6
A7
B6
E7
E6
B7
F7
F5
F6
KEY_COL(3:0)
SCL_AB
SDA_AB
NC5
NC6
NC7
NC8
NC1
NC2
NC3
NC4
Wake_INP5
Wake_INP4
Wake_INP1
Wake_INP0
Wake_INP3
Wake_INP2
A6 G5 KEY_COL(3)
B5 G4
KEY_COL(4) Wake_INP7 K_Out2 KEY_COL(1)
A5 F4
KEY_COL(5) K_Out4 U400 K_Out1 KEY_COL(0)
B4 G3
KEY_COL(6) K_Out5 LM8333GGR8_NOPB K_Out0
A4 F3
KEY_COL(7) K_Out6 _RESET KEYCODER_RSTN
A3 G2
B3
K_Out7
U400 Int_Rx
G1
Gen_IO_0
Gen_IO_1
Gen_IO_2 WD_Out
Gen_In1
Gen_In0
A2 F2
CLK_In
Gen_IO_3 Int_Tx KEYCODER_INT

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
VCC1
VCC2
PWM
B2
A1
B1
TP401 D2
D1
F1
E1
E2
C3
C4
C5
D3
D4
D5
E3
E4
E5
C416 C417
68K
0.1u 0.1u
C417
PWR_BTN
MENU_KEY
R408
AP_VDD_IO_2.7V
Schematic of key sense part
4. TROUBLE SHOOTING
4.11 Keypad backlight trouble

Key Pad Back Light is on as below :
Key pressing → STn8810 commend MSM6275 lighting the Key LED → MSM 6280 let
KPD_DRV_N of PM6658 to go to Low → LED On (Key Pad LED controlled by PM6658)
Start
Key press
Check device short :

NO LD400~403 and R409~412 (Main)
AP_+VPWR is OK?
LD100~101 and R103~104 (Sub)
Yes
Signal KPD_DRV_N NO
Change the main board
is Low?
Yes
Yes Check connection
Only Sub board LED between Main and FPCB
is not work? and between FPCB and Sub
NO
Yes Check device open :
Some LED
is not work? LD400~403 and R409~412 (Main)
LD100~101 and R103~104 (Sub)
NO
NO
Work well? Change the main & Sub board
Yes
End
LD400~403 and R409 ~412

LD100~101 and R103~104 (Sub)
4. TROUBLE SHOOTING
KEYPAD LED
+VPWR AP_+VPWR
R852 (KPD_DRV_N)
LD400 LEWWS44-E R409 R852

KPD_MAIN_DRV_N
68 51
VA416
68 EVL14S02200

68
68
LD400~403 and R409~412 (Main)
A P_+VPWR
KEYPAD LED (SUB)
L EWWS44-E
L D100 R103
100o h m
L EWWS44-E
L D101 R104
K PD_FOL DER_DRV_N
100o h m
VA 1 1 0
EVL 14S02200
LD101~101 and R103~104 (Sub)
Schematic of keypad backlight part
4. TROUBLE SHOOTING
4.12 Folder on/off trouble

Folder On/Off(Close/Open) is worked as below :
Folder On/Off Event → Flip(U402 pin 1,key board) is triggered(Open : about 2.7V, Close : 0V) →
Folder event transfer to GPIO5 of STn8810 and GPIO37 of MSM6280 directly
Start
NO
Check the magnet in
Insert the magnet
folder Assy
Yes
No magnet to U402
YES Check the U402 Pin#4

FLIP(U402 pin#1, C418) is 0V? for AP_VDD_IO_2.7V
No
Approach magnet to U402
NO
FLIP(U402 pin#1, C418) is 0V? Change the Main Board
YES
NO
Work well? Change the Main Board
Yes
End
magnet
C418 U402
4. TROUBLE SHOOTING
U402 BU52031NVX
1 4 AP_VDD_IO_2.7V
FOLDER_DETECT OUT VDD
PGND
2 3
GND NC
C418
0.1u
5
FOLDER_SENSE
C6 KEYCODER_RSTN
GRFC9_GPIO12 GPIO3
J21 D7 KEYCODER_INT
CAMCLK_PO_GP_MN_GPIO13 CAMCLK_24MHZ GPIO4
A6 F8 FOLDER_DETECT
GPIO28 PWR_BTN GPIO5
N19 E8 HOOK_SENSE
USB_RX_DATA_GPIO29 GPIO6
W15 F15 MSPTCK0
XMEM2_CS_N2_GPIO35 HCSN_ETMCLK_XTICLK GPIO19
AA15 D16 WM_LRC
XMEM2_CS_N3_GPIO36 GPIO21
AE13 C16 WM_BCLK
LCD_EN_GPIO37 FOLDER_DETECT GPIO22
H9 C17 VGA_RSTN_AP
GPIO43 AP_PON GPIO26
B6 D18 LEVEL_SHIFT_EN
SYNTH2_GPIO65 GPIO28
F8 C18 CAM_I2C_CTL
GPIO66 TP501
GPIO29
AA1 AB8 VGA_STANDBY
XMEM1_CS_N1_GPIO76 CAM_IF_PWDN BUFF_TCXO_FF GPIO34
Y6 AB7 CAM_IF_POWER
XMEM1_CS_N3_SDRAM1_CS_N1_GPIO77 EAR_SENSE_N GPIO35
L25 AC7 WLED_nRST
UART3_RFR_N_GPIO87 GPIO36
H6 AD7 USB_SW
UART2_DP_RX_DATA_GPIO89 NC7SZ74L8X U500 GPIO37
F18 8 1 AD6 UTXD2
SYNTH0_GP_PDM0_GPIO92 RTC_CONT VCC _PR GPIO38
H18 N6 I2CSCL1
SBST1_GPIO93 EAR_MIC_LDO_EN GPIO53
7 2 N5 I2CSDA1
GPIO54
C545 CK _CLR G3 BT_RESETN
H13 GPIO58_SSPTXD
TX_AGC_ADJ 33p R506 D22 CAM_IF_PWDN
L13 6 3 GPIO76
TRK_LO_ADJ D Q K4 HPI_IT_MOD_ETMSYNCA_XTIDAT
F19 GPIO91
TCXO_EN_GPIO94 TCXO_EN 2K J3 HPI_IT_APE_ETMPSTA0_XTIDAT
F17 5 4 GPIO92
PA_ON0 PA_ON _Q GND
D6 UTXD0
A12 UTXD0
Q_OUT_N TX_QM F7 URXD0 VDDIOE
B12 URXD0
Q_OUT TX_QP E7 UCTS0N
A13 UCTS0N
I_OUT_N TX_IM D8 URTS0N
U100 I_OUT
B13
F12
TX_IP U501-1 URTS0N
URXD2
AB6 URXD2
R108
DAC_REF DAC_REF
STN8810S12B2V1 Q_IM_CH1
W23
GPS_QN
MSM6280_A USBVP
USBVM
E24
F22
USBVP
USBVM
3.3K
V23 F23 USBRCV R109

Q_IP_CH1 GPS_QP USBRCV
V25 E22 USBSDA
I_IM_CH1 GPS_IM USBSDA
W25 G22 USBINTN
I_IP_CH1 GPS_IP USBINTN
3.3K
AA25 G23 USBOEN

Q_IM_CH0 RX_QM USBOEN
Y25 E23 USBSCL
Q_IP_CH0 RX_QP USBSCL
AB25
I_IM_CH0 RX_IM
AC25 F5 I2CSCL0
I_IP_CH0 RX_IP I2CSCL0
F4 I2CSDA0
I2CSDA0
E21 IT_WAKE_UP_AP
PWLOUT
K5 CCIRID(7)
CCIRID7_CCIROD7
K3 CCIRID(6)
CCIRID6_CCIROD6
L4 CCIRID(5)
CCIRID5_CCIROD5
L5 CCIRID(4)
CCIRID4_CCIROD4
L3 CCIRID(3)
CCIRID3_CCIROD3
M4 CCIRID(2)
CCIRID2_CCIROD2
M5 CCIRID(1)
CCIRID1_CCIROD1
M3 CCIRID(0)
CCIRID0_CCIROD0
P5 CCIRIVS
CCIRIIVS
P3 CCIRIHS
CCIRIHS
R5 CCIRICLK
CCIRICLK_CCIROCLK
Schematic of Folder on/off part
4. TROUBLE SHOOTING
4.13 Micro SD trouble

Micro SD is worked as below :
Micro SD insertion → Card Detect (SD_INT) goes to low → STn8810 detect SD_INT and assert
VMMC_3.1V by STw4810 → go working
Start
Insert the Micro SD Card
NO NO
Does the micro SD icon SD_INT (D101 Pin#6)
appears ? is be low ?
YES YES
NO NO
Work well? Check VMMC_3.1V
is over 2.85V?
YES YES
End Check the Pull up resistor Change the main board

R100, RA100
S100 (MicroSD Socket)
R100
RA100
D101
4. TROUBLE SHOOTING
R100, RA100 VMMC_3.1V
2
4
6
8
10K
10K
RA100
R100
1
3
5
7
S100 SCHA 1B 0102
SD_DAT(2) DA T2_RSV
R101 10 CD_DA T3_CS
SD_DAT(3)
R102 10 CMD_DI
SD_CMD
R103 10 VDD
SD_CLK CL K _SCL K
R104 10 VSS
SD_DAT(0) DA T0_DO
R105 10 DA T1_RSV
SD_DAT(1)
R106 10 COMMON
DETECT
SD_INT
DUMMY1
DUMMY2
RCLAMP0504P.TCT
RCLAMP0504P.TCT
R107
3
C101
C102
C103
C104
C105
IO2
NC
IO1
D100
D101
IO1
NC
IO2
C106
P_GND
P_GND
5V_NC
5V_NC
1u
IO3
IO4
IO4
IO3
DNI
DNI
DNI
DNI
DNI
DNI
4
D101 Pin#6 of Sub (SD_INT) C106 (VMMC_3.1V)
Schematic of Micro SD
4. TROUBLE SHOOTING
4.14 Charging trouble
+5V_PWR
TA OVP
(4.8V)
1K
C819 2.2u U801
R807 51 K C1
VCHG
TP800 C2
USB
C821
CHG_CTL_N
D1
33p
ICHARGEOUT ISNS_M
Cable TP801 D2
ISNS_P
VBATT E1
(5.0V) E2
VBAT
BATT_FET_N BAT_FET_N
F2
USB_OVP_G
J10
VCOIN
H1
USB_VBUS
2
+VPWR
SIA411DJ
Q800
Main
D1 D2 D3 D4 D5
S1 S2
Battery VBATT ICHARGEOUT

G
OVP Circuit
BATT_FET_N
Fig. Charging Pass
■ Charging Procedure
- Connecting TA or USB Cable → +5V PWR Line PM6658(VCHG) → PM6658(ICHARGEOUT) →
OVP Circuit (between PM6658 and Main Battery) → Main Battery
■ Check Point
- Connection of TA or USB Cable
- Charging current path
- Battery
■ Trouble Shooting Setup
- Connect TA or USB Cable and battery to the phone
■ Trouble Shooting Procedure
- Check the charger connector
- Check the charging current path
- Check the battery
4. TROUBLE SHOOTING
Start
Check the pin and battery

Connect terminals of I/O connector
NO
Connection OK? Change I/O connector
Yes
Is the TA voltage 4.8V? NO

Is the USB voltage 5.0V? Change TA/USB cable
Yes
Check the U208, Q800
Yes
Yes
Charging OK? END
NO
Change the board
Q800
U208
PM665
8(U801)
+5V
PWR
(C819)
VBAT
(C800)
4. TROUBLE SHOOTING
4.15 Audio trouble
4.15.1 Receiver path

Voice Receiver path as below:
MSM6280 Ear1ON/Ear1OP → U201(audio codec) → CN400 (B to B connector between Main and
Folder ) → CN103 (B to B connector to LCD FPCB) → receiver solder PAD included in LCD Module
→ Receiver
Start
Connect the phone to network

Equipment and setup call
Setup 1KHz tone out
Hear the tone to the receiver?
NO
YES
Change the Receiver END
The sine wave appear NO

at C210,C211? Change the Main board
YES
The sine wave appear NO Check the U201 or
atC403,C404? Change the Main board
YES
The sine wave appear at YES Check the pads of Receiver

R101,R102 of Folder FPCB?
NO
Check connector pin
or change the LCD FPCB
Can you hear the tone?
YES
END
4. TROUBLE SHOOTING
LCD connector
Receiver Receiver pads
U201
CN103
(B to B connector to LCD FPCB
C210,C211
C403,C404
C225, C226
CN400
(B to B connector between Main and Folder )
4. TROUBLE SHOOTING
4.15.2 Voice path for headset

Voice path for Head_Set as below:
MSM6280 HPH_R, HPH_L → C208,C209 → U201 (audio codec) → C240,C241 → U209 (audio
subsystem) → R218,R219 #4, #5 pin of CN201 headset Jack
Start

Setup 1KHz tone out
And insert head_Set
Headset insertion detection NO Check #8 pin of CN202

in the Main LCD Display OK? or change the Main bíd
YES
NO
The sine wave appear at
C208,C209 ? Change the Main board
YES
NO
The sine wave appear at Check the U201
C240, C241 ? Or change the Main bíd
YES
NO
Check the U209
or change the Main bíd
R218,R219 ?
YES
NO
Can you hear the tone? Check the CN201 or change
the Main bíd
YES
END
4. TROUBLE SHOOTING
C208, C209
U201 (audio codec)
C240, C241
U209 (audio subsystem)
U501 (MSM6280)
R218, R219
#8pin of CN201
CN201(Headset Jack)
Main PCB
4. TROUBLE SHOOTING
4.15.3 Sound path for headset

Multimedia Sound path for Head_Set as below:
STN8810 (msptxd0) → U201 (audio codec) → C240, C241 → U209 (Audio Subsystem,
WM_LOUT1,WM_ROUT1) → R218, R219 → #4,#5 pin of CN201 headset Jack
Start

Setup 1KHz tone out
And insert head_Set
Headset insertion detection NO Check #8 pin of CN201

in the Main LCD Display OK? or change the Main bíd
NO
The sine wave appear at Check the U201
C240, C241 ? Or change the Main bíd
YES
NO
Check the U209
or change the Main bíd
R218,R219 ?
YES
NO
Can you hear the tone? Check the CN201 or change
the Main bíd
YES
END
4. TROUBLE SHOOTING
C208, C209
U201 (audio codec)
C240, C241
U209 (audio subsystem)
U100 (STN8810)
R218, R219
#8pin of CN201
CN201(Headset Jack)
Main PCB
4. TROUBLE SHOOTING
4.15.4 Loud speaker path (voice speaker phone)

Loud speaker path as below:
MSM62780 HPH_R, HPH_L → C208,C209 → U201 (audio codec) → C237,C238 → U209 (Audio
Syb system) → 70 Pin BtoB Connector → FPCB pads for Left speaker, PAD of LCD Module for Right
speaker
AP_VDD_IO_1.8V WM_DVDD
R200
C202
C203
C204
Start C208, C209
10u
0.1u
0.1u
Connect the phone to network C864 C865
H7
H6
J7
33p 33p
DGND
DCVDD
DBVDD
C208 1u
Setup 1KHz tone out WM_HPH_L
A2
LINE1
C209 1u A1
Set phone with speaker phone mode WM_HPH_R LINE2
C210 1u B1
WM_RXP RXP
C211 1u C2
WM_RXN RXN
C866 C867
A3
1u
33p 33p ACIN
The sine wave appear at NO

Change the Main board B3
U201
C213
ACOP
C208,C209?
D2
WM_MIC1N MIC1N
C1
YES WM_MIC1P MIC1
The sine wave appear at NO Check the U201 or

C237, C238? Change the Main board
YES
The sine wave appear at NO Check the U209

pads of speaker? and 70pin connector
YES
NO Change the speaker
Can you hear the tone? AP_+VPWR
or LCD Module
C232
YES AP_+VPWR
C237,C238 C233 C234

2.2u
END 10u 1u
D6
A5
B5
F1
R836 10K
C235
2.2u
CPVSS
VSS
VDD
PVDD
C236 1u
A4
C1N
A3
CPGND
A2 A6
C1P HPL
A1 B6
1u C237 CPVDD HPR
E3
E4 U209 C6
WM_ROUT2 INA2 OUTRX
WM_ROUT1 INB1
1u C241 D5 C1
WM_LOUT1 INB2 OUTL+
B4 E1
R843 2.2K
R844 2.2K
INC1 OUTL-
C5
INC2
B3 F4
VBIAS OUTR+
TP813 C2 F2
PM_SDA SDA OUTR-
TP814 D2
PGND1
PGND2
PM_SCL SCL
CR_H
TP203 E2
CR_L
CL_H
CL_L
GND
SPK_AMP_EN _SHDN
C251
F6
D1
F3
E6
F5
B1
B2
4. TROUBLE SHOOTING
4.15.5 Loud speaker path (VT, multimedia play, etc)

Loud speaker path (VT, multimedia play) as below:
STN8810(msptxd0) → U201 (audio codec) → C237,C238 → U209 (Audio Syb system) → 70 Pin
BtoB Connector → FPCB pads for Left speaker, PAD of LCD Module for Right speaker
B7 1u C214
MONO2
Start MONO1
B6 1u C219
D9
ROUT1 WM_ROUT1
Equipment and setup call A9
LOUT2 WM_LOUT2
Setup 1KHz tone out
Set phone with speaker phone mode B9
ROUT2 WM_ROUT2
Audio Codec
The sine wave appear at NO Check the U201 or

C237, C238? Change the Main board
YES
The sine wave appear at NO Check the U209

pads of speaker? and 70pin connector
YES
NO Change the speaker

Can you hear the tone?
or LCD Module
YES
C232
END AP_+VPWR
C233 C234
2.2u
10u 1u
D6
A5
B5
F1
R836 10K
C235
2.2u
CPVSS
VSS
VDD
PVDD
C236 1u
A4
C1N
A3
CPGND
A2 A6
C1P HPL
A1 B6
1u C237 CPVDD HPR
E3
E4 U209 C6
WM_ROUT2 INA2 OUTRX
WM_ROUT1 INB1
1u C241 D5 C1
WM_LOUT1 INB2 OUTL+
B4 E1
R843 2.2K
R844 2.2K
INC1 OUTL-
C5
INC2
B3 F4
VBIAS OUTR+
TP813 C2 F2
PM_SDA SDA OUTR-
TP814 D2
PGND1
PGND2
PM_SCL SCL
CR_H
TP203 E2
CR_L
CL_H
CL_L
GND
SPK_AMP_EN _SHDN
C251
F6
D1
F3
E6
F5
B1
B2
4. TROUBLE SHOOTING
Speaker R Speaker pads Speaker L
U201
C237,C238
C210,C211
C403,C404
CN400
(B to B connector between Main and Folder )
4. TROUBLE SHOOTING
4.15.6 Microphone for main MIC

Main Microphone path as below:
MIC → C239,C243 → U201(audio codec) → C214, C219 → MSM62780 → MIC feed back gain logic
MSM internal CODEC
C214, C219
C239, C243
WM_MICBIAS B7
U201 MONO2 WM_MONO2
SPM0204HE5-PB-3 B3 B6 1u C219
C213

P
4 C239 1u
G2 WM_MIC1N D2
3 WM_MIC1N MIC1N C863 C862
G1 D9
2 ROUT1 WM_ROUT1 51p 51p
O C1
MIC200
1
C243 1u
WM_MIC1P
WM_MIC1P
WM_MIC2N
C220 1u E2
MIC1
MIC2N
[audio codec] A9
LOUT2 WM_LOUT2
C250
C221 1u D1
WM_MIC2P MIC2
MODE_GPIO3
B4 B9
CSB_GPIO5
GP1_CLK1
GP2_CLK2
39p
PCMCLK
VXDOUT
DACDAT
ADCDAT
VXCLK
VXDIN
GPIO4
AGND
PGND
MCLK
PVDD
AVDD
VREF
VXFS
BCLK
SCLK
VMID
SDIN
LRC
C223
4.7u
A5
A4
A6
B5
J6
G9
H9
G8
J9
J8
J3
J1
J2
H3
J4
H4
H5
J5
F1
H1
G1
F2
E1
4.7u
4.7u
100K R209
C224
C225
100K R210
TP205
100K R211
[main MIC]
C223
WM_MONO2
WM_MONO1
WM_RXP
Start C505
MSM pin W18
0.1u 39p 39p 39p 39p 10p 10p
10% (CODEC VSS)
AC22
AC21
AC19
AC20
AA18
AA19
AE19
AE20
AA20
AF18
AF19
AF21
AF22
AF20
T15
Make a call
EAR1OP
MICBIAS
AUXOUT
HPH_VREF
LINE_L_IP
LINE_L_IN
LINE_R_IP
LINE_R_IN
AUXIN
AUXIP
MIC2N
MIC2P
MIC1N
MIC1P
CCOMP
SDCC_DAT1_GPIO99
F25
M25
[MSM6280]
SDCC_DAT2_GPIO100
M26
SDCC_DAT3_GPIO101
AE3
AD2
NO
MIC_BIAS(C223) is 2.7V? Change the Main Bíd
YES
make some sound or
voice to MIC
YES
Can you scoping some NO

sound signal at C239,C243? Change the MIC
Can you scoping some NO Check the U201 or

sound signal at C214,C219 ? Change the Main Bíd
YES
YES
Work well? END
4. TROUBLE SHOOTING
Main MIC (MIC200)
C239, C243
C223
C214, C219
4. TROUBLE SHOOTING
4.15.7 Microphone for headset

MIC for Head_Set path as below:
Insert Headset → EAR_SENSE_N(pin8) go 0V → MSM62780 and STN8810 sense Head_Set
insertion → MIC signal → U201(audio codec) → MSM6280.
C214, C219
VRE
R1114D181D U804
3 1
VOUT VDD
2 4
5
GND1
GND2
NC
CE
6
C220, C221
C227
10u
R214
R213
1.5K
1M

B7
U201 MONO2 WM_MONO2
VIN- 4 5
AP_VDD_IO_1.8V VCC 1 B3 B6 1u C219
C213
18 PIN MMI 330K
VIN+ 3 G ND
2
OU T
U206
NCS2200SQ2T2G D2
CN201 WM_MIC1N MIC1N C863 C862
R215 D9
100K R216 ROUT1 WM_ROUT1 51p 51p
C1
21 WM_MIC1P MIC1
19 C220 1u E2
1 WM_MIC2N MIC2N
WM_MIC2N A9
2 C221 1u D1 LOUT2 WM_LOUT2
WM_MIC2P
3 WM_MIC2P MIC2
FB200 1000
4 R218 100ohm
MODE_GPIO3
EAR_L B4 B9
5
CSB_GPIO5
EAR_R WM_MICBIAS MICBIAS ROUT2 WM_ROUT2
GP1_CLK1
GP2_CLK2
6 R219 100ohm
PCMCLK
VXDOUT
USB_D+
DACDAT
ADCDAT
7
VXCLK
VXDIN
GPIO4
USB_D-
AGND
PGND
MCLK
PVDD
AVDD
VREF
VXFS
BCLK
SCLK
VMID
SDIN
8 FB201
LRC
EAR_SENSE_N C223
9
VBATT 4.7u
10
A5
A4
A6
B5
J6
G9
H9
G8
J9
J8
J3
J1
J2
H3
J4
H4
H5
J5
F1
H1
G1
F2
E1
11
REMOTE_PWR_ON
4.7u
12
4.7u
13 100K R209
14 C224
C225
15
USB_VBUS 100K R210
TP205
16
UART_TXD
17
UART_RXD 100K R211
18
RSB6.8CST2R
RSB6.8CST2R
20
EVLC18S02003
EVLC18S02003
EVLC14S02050
EVLC14S02050
EVLC14S02050
EVLC14S02050
EVLC14S02050
22
USFB13L D200
33p
47p
47p
1u
smd_1608h_9_r
C247
C244
C246
VA207
VA208
C245
VA202
VA203
VA200
VA201
VA205
VA204
VA206
WM_MONO2
WM_MONO1
WM_RXP
Start
C505
MSM pin W18
0.1u 39p 39p 39p 39p 10p 10p
10% (CODEC VSS)
Make a call
AC22
AC21
AC19
AC20
AA18
AA19
AE19
AE20
AA20
AF18
AF19
AF21
AF22
AF20
T15
EAR1OP
MICBIAS
AUXOUT
HPH_VREF
LINE_L_IP
LINE_L_IN
LINE_R_IP
LINE_R_IN
AUXIN
AUXIP
MIC2N
MIC2P
MIC1N
MIC1P
CCOMP
YES SDCC_DAT1_GPIO99
F25
Try change the head set END SDCC_DAT2_GPIO100

SDCC_DAT3_GPIO101
M25
M26
AE3
AD2
NO
NO
EAR_SENSE_N is 0V? Change the Main bíd
YES
NO
MIC_BIAS is 1.8V ? Change the Main bíd
YES
make some sound or
voice to MIC
Can you scoping some NO

sound signal at C221? Change the MIC
YES
Can you scoping some NO Check the U201 or

sound signal at C214,C219? Change the Main Bíd
YES
YES
Work well? END
4. TROUBLE SHOOTING
C220, C221
U201 (audio codec)
C214, C219
#8pin of CN201
CN201(Headset Jack)
Main PCB
4. TROUBLE SHOOTING
4.16 Camera trouble

2M camera control signals are generated by STN8810 and MSM6280. VGA camera control signals
are generated by STN8810. Data signals are processed by STN8810.
KT610 has two cameras. The one is a 2 Mega Camera, the other is VGA camera.
2M START
Check the camera conn. and

reconnect the camera
Yes
Camera is OK? End
NO
NO MSM6280 output signal check

(CAM_IF_PWR, CAM_IF_PWDN,
2M_RSTN, 2M_PWDN)
Yes
NO Check AP_VDD_CAM_IO_2.7V,
AP_VDD_CAM_1.8V
Yes
NO
Check master clock
Yes
Check the CCIRCLK_CAM Yes No

Check the EMI/ESD filter
(FL403 #2) (FL403 #8)
No Yes
Change the camera

Change the Filter (FL403)
Yes
Camera is OK End
NO
4. TROUBLE SHOOTING
CAM_IF_PWDN
(TP501)
CAM_IF_POWER
(TP507)
2M_RSTN
(C409)
2M_PWDN
(TP400)
24MHz Master Clock

(R405)
AP_VDD_CAM_IO_2.7V
AP_VDD_CAM_1.8V
(FB400)
CCIRICLK
(FB401)
FL403 (#2)
4. TROUBLE SHOOTING
AP_VDD_CAM_ AP_VDD_CAM_AVDD_2.7V
IO_2.7V AP_VDD_CAM_IO_2.7V
AP_VDD_CAM_1.8V
2M CAM Connector
HB-1M1005-601JT
AP_VDD_CAM_
HB-1M1005-601JT
HB-1M1005-601JT
CN402
G1 G2 AVDD_2.7V
1 24
2 23
FB400
FB402
CCIRID(7)_CAM I2CSCL0_CAM
FB401
3 22
CCIRID(6)_CAM I2CSDA0_CAM
4 21
CCIRID(5)_CAM
5 20
CCIRID(4)_CAM CCIRIVS_CAM
6 19
CCIRID(3)_CAM CCIRIHS_CAM
CCIRID(2)_CAM
7 18
CAMCLK_24MHZ_CAM
AP_VDD_CAM_1.8V
8 17
CCIRID(1)_CAM
9 16
CCIRID(0)_CAM
10 15
CCIRICLK_CAM
11 14
2M_RSTN
12 13
2M_PWDN
C409 TP400
C412
C415
C411
C410
C413
C414
G3 G4
0.1u
0.1u
0.1u
0.1u
10u
10u
10u
2M_RSTN 2M_PWDN
10
5
G1
G2
CCIRIHS_CAM INOUT_A4 INOUT_B4 CCIRIHS

4 6
CCIRIVS_CAM INOUT_A3 INOUT_B3 CCIRIVS
3 7
CCIRICLK_CAM INOUT_A2 INOUT_B2 CCIRICLK
2 8
CAMCLK_24MHZ_CAM INOUT_A1 INOUT_B1 CAMCLK_24MHZ
1 9
R405 0
FL403 EVRC18S03Q015050R
CCIRICLK_CAM CAMCLK_24MHZ_CAM
FL403 (#2) FL403 (#1)
Schematic of 2M camera part
4. TROUBLE SHOOTING
VGA START
Check the camera & 70-pin

main conn.
And reconnect these connectors
Yes
Camera is OK? End
NO
NO
STN8810 output signal check
(VGA_RSTn, VGA_STNADBY)
Yes
NO
Check AP_VDD_CAM_2.8V, Change the BD6085
AP_VDD_CAM_1.8V
Yes
NO
Check master clock
(CAMCLK_27MHZ : R404)
Yes
Check the EMI/ESD filter NO Change the Filter

(FL100/ 101/ 102) (FL100/ 101/ 102)
Yes
NO No
Check the CCIRCLK Check the CCIRCLK (in FPCB)
(FL100 #2)
Yes
Change the camera
Change the slider FPCB
Yes
Camera is OK End
NO
4. TROUBLE SHOOTING
VGA_RSTN VGA_STANDBY
(R403) (R402)
MCLK_27MHZ_CAM
(R404)
AP_VDD_CAM_2.8V
(C109)
AP_VDD_CAM_1.8V
(C108)
CCIRICLK
(FL100 #2)
4. TROUBLE SHOOTING
CN400
G 2 G1
70 1
69 2 0 R400
MOT_PWR- 0 R401
68 3
KEY_ON_SW_N
67 4
KPD_FOLDER_DRV_N
66 5
WLED_nRST
65 6
64 7
MCLK_27MHZ_CAM
63 8
62 9
CCIRICLK
61 10
CCIRIHS
60 11
CCIRIVS
59 12
VGA_RSTN CCIRID(7)
CCIRID(6)
58 13
57 14
CCIRID(5)
56 15
CCIRID(4)
55 16
CCIRID(3)
VGA_RSTN CCIRID(2)
54
53
17
18
CCIRID(1)
52 19
CCIRID(0) R402 0 51 20
VGA_STANDBY
50 21
VGA_RSTN 0 R403 49 22
I2CSDA0_CAM
48 23
C400 I2CSCL0_CAM
47 24
1u
46 25
I2CSCL0
45 26
I2CSDA0
44 27
43 28
FL400 EVRC18S03Q015050R
1 9 VGA _STA NDB Y
R404 0 INOUT_A1 INOUT_B1 FL 100 EVRC18S03Q015050R
2 8
MCLK_27MHZ_CAM INOUT_A2 INOUT_B2 MCLK_27MHZ 1 9
3 7 MCL K _27MHZ_CA M INOUT_A 1 INOUT_B 1
I2CSDA0_CAM INOUT_A3 INOUT_B3 I2CSDA0_SW 2 8
4 6 CCIRICL K INOUT_A 2 INOUT_B 2
3 7
I2CSCL0_CAM INOUT_A4 INOUT_B4 I2CSCL0_SW CCIRID(0) INOUT_A 3 INOUT_B 3
4 6
G1
G2
CCIRID(1) INOUT_A 4 INOUT_B 4

G1
G2
5
10
5
10
MCLK_27MHZ_CAM CCIRCLK
(in Main BD) FL100 #2 (in FPCB)
A P_+VPWR
U100 L ED5
C1
ML ED5
E6 D1
VIO L ED6 SL ED1
B D6085GUL L ED7
D2
SL ED2
C2
FL GND
D3
RESETB
D5 F5
SDA VB A TL DO1
SCL VB A TL DO2
AP_VDD_CAM_1.8V
E5 AP_VDD_CAM_2.8V
L DO1O 1u
E1 TP100
L DO2O C106
E4
L DO3O
F4 E2
A GND L DO4O
T1
T2
T3
T4
F6
F1
A1
A6
AP_VDD_CAM_1.8V
1u 1u 1u
C107 C108 C109
AP_VDD_CAM_2.8V
LCD_Backlight driver
Schematic of VGA camera part
4.17 Main LCD trouble
Main LCD control signals are generated by STN8810. Those signal’s path are :
STN8810 → 70-pin main connector (CN400 in main PCB) → 70-pin connector (CN400 in Main-Folder
FPCB) → 50-pin connector (CN103 in Main-Folder FPCB) → LCD Module
START
Press END key

to turn the power on
No Follow the Power ON

Is the circuit powered?
trouble shooting
Yes
Disconnect and reconnect
70-pin , 50-pin B to B
connector
Yes
LCD display OK?
No
Check AP_VDD_LCD_2.7V, LCD_NRESET,

LCD_DATA(0) in Main BD
No Yes
Change the Main BD

Check the same signal
in Main-Folder FPCB
No Yes
Change the Main-Folder FPCB Yes

& re-check Display OK?
Yes
No
Yes
Change the Backlight Driver IC
in Key PCB No
No
Change the LCD module The LCD works
End
LCD_NRESET
(R400)
LCD_DATA(0)
(FL404 #4)
AP_VDD_LCD_2.7V
(C107)
CN400
G 2 G1
70 1
LCD_NRESET
0 R400 LCD_NRESET
69 2
0 R401 LCD_VS
68 3
LCD_DATA_O_6
67 4
LCD_DATA_O_4
LCD_VS
66 5
LCD_DATA_O_2
65 6
LCD_DATA_O_0
64 7
LCD_DATA_O_8
63 8
LCD_DATA_O_10
62 9
LCD_DATA_O_12
61 10
LCD_DATA_O_14
60 11
LCD_DATA_O_15
59 12
LCD_DATA_O_13
58 13
LCD_DATA_O_11
57 14
LCD_DATA_O_9
56 15
LCD_DATA_O_7
55 16
LCD_DATA_O_5
54 17
LCD_DATA_O_3
53 18
LCD_DATA_O_1
52 19
R402 0 SDIS_CSN_O
51 20
DIS_WEN_O
50 21
0 R403 MDIS_CSN_O
49 22
DIS_RS_O
48 23
47 24
46 25
EVRC14S03Q030100R FL404
9 1
LCD_DATA_O_6 INOUT_B1 INOUT_A1 LCD_DATA(6)
8 2
LCD_DATA_O_4 INOUT_B2 INOUT_A2 LCD_DATA(4) LCD_DATE
7 3
LCD_DATA_O_0
6
INOUT_B4 INOUT_A4
4
LCD_DATA(0) (In Main BD)
G2
G1
10
5
A P_+VPWR
U100 L ED5
C1
ML ED5
E6 D1
VIO L ED 6 SL ED1
B D6085GUL L ED7
D2
SL ED2
C2
FL GND
D3
RESETB
D5 F5
SDA VB A TL DO1
SCL VB A TL DO2
AP_VDD_CAM_1.8V
E5 AP_VDD_CAM_2.8V
L DO1O 1u
E1 TP100
L DO2O C106
E4
L DO3O
F4 E2
A GND L DO4O
T1
T2
T3
T4
F6
F1
A1
A6
1u 1u 1u
AP_VDD_LCD_2.7V
C107 C108 C109 (In Key PCB)
Schematic of LCD part
4.18 Bluetooth trouble
Bluetooth control signals are generated by STN8810.
Bluetooth Chip (STLC2500) and peripherals are mounted in Sub Board which is connected by B-to-B
connector.
Those signal’s path are : STN8810 → AP_VDD_IO_1.8V and AP_VDD_IO_2.7V is asserted →
CLK32K is asserted → Bluetooth ON → BT_RESETN is High → CLK_REQ_OUT_1 is High →
REF_CLK_IN is asserted → transmit/receive data/control through UART → transmit/receive voice
data through PCM I/F AP_VDD_IO_2.7V is same with AP_VDD_BT_2.7V which are just connected
through 0 ohm resistor
A P_VDD_IO_2.7V A P_VDD_B T_2.7V
A P_VDD_B T_2.7V
R109
0
X100 R109
U101 STL C2500C
D3
X100 CSC3M192000EEVRS00 B T_RESETN RESET_N
4 3 D6
VDD OUT REF_CL K _IN
1 2 G3
TRI_OPEN GND CL K 32K L P_CL K
C4
19.2MHz CL K _REQ_OUT_1
C5
C100 B T_WA K EUP
1u
F5 F6
UTXD0 UA RT_RXD UA RT_TXD URXD0
G4 F4
URTS0N UA RT_CTS UA RT_RTS UCTS0N C107
PCMCL K
D1
PCM_CL K 33u
C2
PCMSYNC PCM_SYNC
D2
PCMDA TA IN PCM_A
E1
PCMDA TA OUT PCM_B
B3
GPIO_16
C3
GPIO_8
B1 B2
C1
GPIO_9
GPIO_10
GPIO_11
FL100 C123
D5 A2
GPIO_0 VSS_RF1
E6
G6
CL K _REQ_IN_1
CL K _REQ_IN_2
VSS_RF2
A5
ANT100
F7 DEA 212450B T-7043C1
HOST_WA K EUP
FL 100 A NT100
E2 A3 C123 10p
A P_VDD_B T_2.7V CONFIG_1 RFP NC1
F2 A4 5 1
CONFIG_3 RFN B P1 U_B P FEED NC2
F1
CONFIG_2
4 2
B P2 B P_DC
G7 L 101
G2
G1
A P_VDD_IO_1.8V CL K _REQ_OUT2 C124

DNI 1.5p
A6
6
3
TOUT_IP_QN
B5 E3
TOUT_IN_QP VSS_DIG1
E4
VSS_DIG2
R110
R110 G2
0
VDD_D
G5
VDD_IO_A
F3
VDD_IO_B
E7
VDD_CL D
B4
VSS_A NA 1
A7 B6
VDD_HV_A VSS_A NA 2
C6
VSS_A NA 3
G1
VDD_HV_D
B7
VDD_DSM
C7
VDD_N
D7 E5
VDD_CL A F_PRG
A1
VDD_RF
220n
220n
220n
220n
220n
1u
1u
C115 1u
1u
1u
C109
C113
C110
C112
C114
C116
C117
C118
C111
B L UETOOTH MODUL E
Figure. Schematic of Bluetooth Interface
4. TROUBLE SHOOTING
Bluetooth RF Test
TC-3000A (Bluetooth Te ster)
TC-3000A (Bluetooth Tester)
1. Set phone to bluetooth test-mode:

Enter Test Mode(*#32*36907#) → Module Test Set → BT DUT → BT DUT ON
2. Connect phone to bluetooth tester
3. Set channel to 39
4. Measure output-power
5. Check TP1 : output-power > -6 dBm
Set the bluetooth ON X100 R110 U101
AP_VDD_BT_2.7V Check Power

is asserted? (R109, R110)
REF_CLK_IN Check Oscillator

is asserted? (X100)
R109 C123
RF Power (C123) Check BT Antenna

< -6 dBm? (ANT100) soldering
Check FL100
soldering
Change
Bluetooth is work well?
the main board
FL100 ANT100
END
5. DOWNLOAD
5. DOWNLOAD
5.1 COM PORT setting method when using USB Download
5.1.1 Install NEXUS3 Driver Serial Port Driver)
execute
5.5.2 Device Manager setting about USB device

• Open ‘Universal Serial Bus controllers’ in Device Manager on your PC
• Make ‘Standard Enhanced PCI to USB Host Controller’ all disabled.
• You need to get connection USB Cable of Nexus 3 with PC step by step: USB1, USB2, etc.
cf. If you connect USB1 to PC, there will be appeared USB2 port automatically.
(You can see the list in Device Manager window on your PC)
Reference Setting manual - NEXUS-III Manual_Kor_8P_080115_ .ppt (Page 9~)
5. DOWNLOAD
5.5.3 NEXUS III → M06: 3G_QC_CM, VBATT : 4.0

Select ‘Mode’, move Up and Down to set M06 then press SET
Use standard 18 pin-Cable

MMI18P-COMM
(MRO 1671570)
5.5.4 Com Port Setting method about USB
• KT610 Model USB Driver is just same as KT610 Model which is not working as normal Qualcomm
3G chipset.
• After connecting USB1, USB2, etc. to Phone,
• f you find new HW device in Device Manager and click Folder which contains above file
‘lgjoyusb.sys’, then it will be installed.
• You need to follow the following steps:
In your Device Manager window,
1) Select ‘PORT’ menu and highlight LGE USB Serial Port(COMXX).
2) Press the right button on you Mouse( ) and move to PORT Setting tab( ), and press
Advanced( ).
3) You need to select Port number start from COM57.
cf. KT610 use Port number 57 to 72 for USB Download.
(It’s possible Port number 41 to 56 for USB Download as well)
• Please make sure that you need to reboot your PC after USB Com Port Setting.
5. DOWNLOAD
5. DOWNLOAD
5.2 How to KT610 Download
5.2.1 How to set the position of Download files [dll,S/W]

• Copy KT610 Model Dll [KT610_Date_MP.dll] to C:\DOWNLOAD\Model\KT610
• Phone SW for download: Copy the BIN Image[APP], DZ Image[Modem] To
C:\DOWNLOAD\Model\KT610
5.2.2 After running LGDP2, how to initial Setting

• Run LGDP2_V34_UMTS.exe
• In the window of Model Buyer Choice, Select OK key after checking the UMTS in Division
Selection
• Press the OK after the following setting.
• Port Selection : After checking the USB Mode , it should be checked for the download port from
COM57 to COM72.
• DLL Selection : Selecting the DLL file in C:\DOWNLOAD\Model\KT610
• Run Download Configuration :
- AP Image : Select the BIN file in C:\DOWNLOAD\Model\KT610
- MP Image : Select the DZ file in C:\DOWNLOAD\Model\KT610
- Select the Update Boot, Update Modem Boot when changing the buyer.
→ Exception for Update Modem Boot in CS version.
• DLL Information : Display Download Configuration information.
5. DOWNLOAD
Select USB Mode
5. DOWNLOAD
5.2.3 How to Download

• Click the START button : Select before Download
cf. Before click the START button, Though connecting phone, it can not be
processed.
• Click the STOP button : selection for no more download.
• Before connecting the Phone, it is standby mode for Download. After connecting Phone, the
download will be processed.
cf. If cannot be process when connecting to Phone, check the USB LED and displaying the port
in device management of NEXUS II
• During the D/Load : Displaying the message about port
• D/Load Error : Font color turn to red and display the ‘Fail’
• D/Load PASS : Font color turn to blue and display the ‘Pass’
• In case of Fail, it will be reconnected. In case of ‘Pass’, connect the new phone.
6. BLOCK DIAGRAM
6. BLOCK DIAGRAM
PYXIS RF Block Diagram
ANT
ANT
STN8810S12
STN8810S12
GSM/ WCDMA RX Data GSM1900_RX
SAW Filter
EBI2 GSM1800_RX
SAW Filter
GSM900_RX
SAW Filter
SKY77519
SKY77519
GSM900_TX ( ED G E P A M + A S M )
GSM/ WCDMA TX Data ( ED G E P A M + A S M )
GSM1800/ 1900_TX
NAND
UMTS2100_TX
SDRAM RF MAIN CHIPSET

RF MAIN CHIPSET
MSM6280 (RTR6285) SAW Filter
(RTR6285)
EBI1
PAM Coupler
PAM Coupl Duplexer
TCXO ACPM- 7381 (20dB) Duplexer
TCXO ACPM- 7381 (ACMD- 7602)
(19.2MHz) (ACMD- 7602)
(19.2MHz
PWR_DET
USIM
USB
UMTS2100_RX GPS
GPS_IN GPS
PM6558 ANT
PM6558 A
GPS LNA
GPS LN SAW Filter
(ALM- 1412)
SIM
GPS_LNA_EN
6. BLOCK DIAGRAM
PYXIS Application Processor Block Diagram
Sub LCD STn8810S12B2V1

BBTT Bluetooth
(1.45î 160 x 64) UART 0 SSTTLLC
C22550000C
C (Ver.1.2, EDR)
MDIF
Receiver (0906)
Main LCD LLeevveell
SSTT M
MC CPP M
Meem moorryy Speaker (1018)
(2.4î 320 x 240)
NNAANNDD 11GGBB SShhififtteerr
SSDDRRAAMM 551122M
MB A MMA AXX
B Auuddiioo 99777755
Speaker (1018)
LLCCDDBBaacckklilg
ighhttDDrriv
iveerrIC
IC GPIO CCooddeecc
MSP0(I2S) switch Headset
W
WMM88775533
Camera (2M Pixel) MI C2
CCIR M IC 1
Camera (VGA)
MIC Mono out

Numeric KKeeyyccooddeerrICIC EBI2
Key pad I2C(1)
((LLM
M88333333)) H PI
EBI1
NAND SDRAM MMOODDEEM M RRFF
MCP (TY9000A800KOGG40) ((M
MSSMM66228800)) CChhiippsseett
Qwerty Key board
UART 2 UART
USB
MM/SD I2C(0) OTG US B SIM
LLeevveell
Camera, LCD Backlight Audio Codec.
SShhififtteerr L/S
L/S SSIIM
M
L/S L/S PM6658
M KKeeyyppaaddLLEEDD
Mic
icrrooSSDD STw4810
VVibibrraattoorr
SSeerria
iall UART SW
PPoorrtt Coin cell
1188ppiinn
UUSSBB MMM MII US B S W
C
Coonnnn.. Battery
DC Charging
OVP
Power Circuit
6. BLOCK DIAGRAM
PYXIS LCD Block Diagram
Hinge
LCD module
WLED_NRS BD6085
T AP_VDD_LCD_2.7V
2 LCD Backlight Driver
&
I2C LDO
Main backlight control

Main LCD
2.4íí QVGA
16
Data[15:0]
nM_CS EMI/ESD filter
nWE
CPU RS
nRESET
LCD_VSYN
C
Sub LCD
EMI/ESD filter 1.45íí 160X64
nS_CS SUB backlight control
6. BLOCK DIAGRAM
PYXIS Camera Block Diagram
AP_VDD_IO_ VREG_MSMP
1.8V 2.8V
1.8V _2.7V AP_+VPWR
( BD6085) ( BD6085)
(STW4810) (PM6658)
STN8810
MCAM_CLK_OUT
Level Shifter
LEVEL_SHIFT_EN
I2CSCL0
Main Folder
V G A C a m er a
Level Shifter Con-Socket
I2CSDA0 Module
(70pin)
VGA_STANDBY_AP
VGA_RSTN_AP
CCIRICLK
CCIRIHS F i lt er
CCIRIVS
CCIRID 0~7
CAM_I2C_CTL
F i lt er
CAM_IF_POWER
CAM_IF_PWDN 2M Camera
Module
CAM_IF_PWDN
CAM_IF_POWER
2M_PWDN SW
2M_RSTN
AP_VDD_CAM_ AP_VDD_CAM_
CAMCLK_24MHZ AP_VDD_IO_ AP_VDD_CAM_
IO_2.7V AVDD_2.7V
2.7V (LDO) 1.8V (PM6658)
MSM6280 (PM6658) (PM6658)
6. BLOCK DIAGRAM
PYXIS Audio Block
ANT
AU_19.2M
Filter STLC2500C Level MIC_BIAS
(BT) PCM Shifter
P CM
BT_19.2M MIC
UART MIC 1
GPIO OUT3
LOUT1
WM_DACDAT
Receiver
SPK_AMP_EN
UART0
MSPRXD0 WM_MSPRXD0
GPIO MAX9775
Switch
MSPTXD0
ROUT1
GPIO
S p e a k er
WM_BCLK
LOUT2
I 2S WM_LRC
ROUT2
WM_8753
(Audio Codec.) Audio
WM_MSPTCK0 Subsystem
M S PR C K 0 WM_MSPTFS0 I 2S
SD A
STN8810MSPRFS0 SCL
P M_ S CL M IC 2
( C P U ) I 2 CS CL 0 Level PM_ SD A
SCL
I2CSDA0 SD A
GPIO GPIO Shifter Head Set
18PIN CONN
RX P
MSM R SN
6280 WM_MONO1
WM_MONO2
HOOK_SENSE_N
EAR_SENSE_N
6. BLOCK DIAGRAM
PYXIS Clock Distribution Diagram
19.2MHz 19.2MHz
OSC MXTALI 27MHz
CLKOUT0 L/S VGA Camera
19.2MHz
PWREN
Nomadik 27MHz
27MHz
2M Camera
OSC
AU_PWR_EN
SXTALI
19.2MHz
OSC
WM8753 (Audio Codec.) 19.2MHz

19.2MHz
REF_CLK_IN CLK_RE Q_ OUT _ 1
STLC2500C (BT)
PWREN SUB
CLK32K_IN B2B LP_CLK
32.768KHz
C on.
L/S TC X O _ E N
STw4810
Request_MC
L/S
SLEEP_CLK 32.768KHz
19.2MHz 19.2MHz
PM6658 32.768KHz
TCXO
(X-tal)
TCXO_OUT_1
19.2MHz
RTR6285_TCXO TCXO
U S B 4 8 M Hz
RF Block MSM6280 (X-tal)
6. BLOCK DIAGRAM
PYXIS Power Distribution Diagram
DC VBAT
Power
Power ON/Off
Charging
Logic
Cir c u it
+VPWR AP_+VPWR
CAM_2.8V 2M_CAMERA Key Pad MAX9775 BH30FB1WHFV BD6085 BD6085

CAM_1.8V (Connector) V ib r ato r
LED (Audio SubSystem) (LDO Audio) (LDO CAM) (LCD Backlight
CAM_2.7V Driver)
AU_3.0V CAM_1.8V
VRE G _ MSM A
_ 2 . 6V
V RE G _ M SMC MAX4717 WM8753LEB VGA_CAM
_1.25 (AU SW) (Audio Codec.) (Connector)
MSM62 8 0 LCD
P M6 6 5 8 (Connector)
( P MI C )
VDD_IO
AP_VD _IO 1.8V
VRE G _MSMP
_ 2 . 7V VCORE/ VDDIOC/D/E
STw4810
VRE G _MSME VPLL/ VDDQ/DDR/NAND STLC2500C
(P M I C ) ST 2 3 7 8
_ 1 . 8V VFUSE (BT)
ST n 8 8 1 0 (Level Shifter)
TY9000A800
KOGG40 (CPU)
(Memory) Reset
RST
Logic
VDDIOA/B/F
VRE G _USIM
_ 2 . 8 5V U SIM V M M C _ 3 . 1V VUSB_3.1V
(Socket)
TransFlash SLAS4717EPMTR2G
VRE G _TCX O (Connector) (USB SW )
_ 2 . 8 5V
V R E G _ SY N T H
_ 2 . 8 5V MIC5219-2.7
VRE G _ RFTX (LDO IO)
AP_VDD IO 2.7V
_ 2 . 8 5V RF Block
VREG_RFR Key Pad
_ 2 . 8 5V Key Pad LM8333 NLAS3158MNR2G A3212EELLT-T
Array pull up (Key Coder) Array pull up
(UART SW) (Folder Sense)
(Folder)
7. CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 6
A A
VDDIOA VDDIOB VDDIOC VDDIOD VDDIOE VDDIOF VDD12 VDDNAND VDDDDR VDDA VDDQ AP_VFUSE
VDDIOC AP_VDD_IO_1.8V VDD12 AP_VCORE
REMOTE_PWR_ON_AP
R100 R101 0
NAND_READY_AP
C100
C101
C102
C103
C104
C105
C106
C107
0
R103
C108
C109
MCDAT31DIR
VDDIOD VDDA AP_VPLL
MCDAT0DIR
MCDAT2DIR
MCCMDDIR
MSPRXD0
MCFBCLK
MSPTXD0
MSPTFS0
MCDAT3
MCDAT2
MCDAT1
MCDAT0
120p
120p
120p
120p
0.33u
0.33u
0.33u
0.33u
MCCMD
R102 10
SD_INT
MCCLK
120p
1u
C7 51K
VDDIOE
AC24
AD23
AD24
AA12
AA14
AA15
AA16
AA18
AA21
AB20
AA13
AA20
AB18
AA17
AB24
AE12
AE15
AA11
AB11
W23
W25
M21
AC3
AD3
AD4
M25
AA9
G21
AA8
G25
G24
H21
U21
N21
R21
C23
C24
D24
D12
C12
D13
C13
D14
C14
D15
C15
H22
H25
R25
Y21
Y22
K21
V21
B12
B15
Y25
E17
E13
E14
E15
E16
T21
F14
F20
F13
F10
F12
F16
F18
F21
F17
F24
L21
F11
W6
W2
M6
M2
G2
H6
R6
U6
R2
H2
C3
C4
D3
K6
P6
V6
Y2
E3
F9
T6
T2
F3
F6
L6
L2
J6
B B
VDDIOA1
VDDIOA2
VDDIOA3
VDDIOA4
VDDIOB1
VDDIOB2
VDDIOB3
VDDIOC1
VDDIOC2
VDDIOC3
VDDIOC4
VDDIOC5
VDDIOC6
VDDIOC7
VDDIOC8
VDDIOC9
VDDIOC10
VDDIOC12
VDDIOC13
VDDIOC14
VDDIOC15
VDDIOD1
VDDIOD2
VDDIOD3
VDDIOD4
VDDIOD5
VDDIOD6
VDDIOE1
VDDIOE2
VDDIOE3
VDDIOF1
VDDIOF2
VDDIOF3
VDD12_1
VDD12_2
VDD12_3
VDD12_4
VDD12_5
VDD12_6
VDD12_7
VDD12_8
VDD12_9
VDD12_10
VDD12_12
VDD12_13
VDD12_14
VDD12_15
VDDNAND1
VDDNAND2
VDDNAND3
VDDNAND4
VDDDDR1
VDDDDR2
VDDDDR3
VDDDDR4
VDDDDR5
VDDDDR6
VDDA
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VOTP
RCOMP
GNDA
DECOUPLING1
DECOUPLING2
DECOUPLING3
DECOUPLING4
DECOUPLING5
DECOUPLING6
DECOUPLING7
DECOUPLING8
DECOUPLING9
DECOUPLING10
DECOUPLING12
DECOUPLING13
MCCLK
MCFBCLK
MCCMD
MCCMDDIR
MSPTXD0
MSPTFS0
MSPRXD0
MSPSCK0
MSPTXD2_SMPCE2N
MSPTFS2_SMPCE1N
MSPTCK2_SMPIORN
GND77
GND78
GND79
GND80
VDDIOC11
VDD12_11
DECOUPLING11
MCDAT3
MCDAT2
MCDAT1
MCDAT0
MCDAT0DIR
MCDAT31DIR
VDDQ
C21 C6 KEYCODER_RSTN
CPU_19.2M MXTALI GPIO3
C22 D7 KEYCODER_INT
MXTALO GPIO4
C19 F8 FOLDER_DETECT VDDDDR
CLK32K SXTALI GPIO5
C20 E8 HOOK_SENSE
SXTALO GPIO6
D20 F15 MSPTCK0
PORN P O RN GPIO19
D17 D16 WM_LRC
MCAM_CLK_OUT CLKOUT0 GPIO21
C1 6 WM_BCLK VDDNAND
GPIO22
VDDIOD E6 C17 VGA_RSTN_AP
TMS GPIO26
C5 D18 LEVEL_SHIFT_EN
AP_VDD_IO_1.8V T DO GPIO28
D5 C18 CAM_I2C_CTL
VDDIOE TDI GPIO29
D4 AB8 VGA_STANDBY
TCK GPIO34
DNI E5 AB7 CAM_IF_POWER
T RS T N GPIO35
H24 A C7 WLED_nRST VDDNAND
TAPSEL GPIO36
AD7 USB_SW VDDQ VDDDDR
R105
would be deleted
47K
C R104 GPIO37
N22 AD6 UTXD2
SCANEN GPIO38
D23 N6 I2CSCL1
SCANMOD GPIO53
L11 N5 I2CSDA1
TSTCLK GPIO54
G3 BT_RESETN
R106
R107
GPIO58_SSPTXD C110 C111

D21 D22 CAM_IF_PWDN
BATOK GPIO76 C112 C113 C114 C115 C116 C117 C118 C119 0.1u 0.1u
VDDOK D19 K4 HPI_IT_MOD_ETMSYNCA_XTIDAT
VDDOK GPIO91 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u
12K
PWREN E20 J3 HPI_IT_APE_ETMPSTA0_XTIDAT

12K
PWREN GPIO92
E19
REMAP1_SMPREGN
F19 D6 UTXD0
REMAP0_SMDIRN UTXD0
F7 URXD0 VDDIOE
URXD0
M24 E7 UCTS0N
SMAD10 UCTS0N
W21 D8 URTS0N
SMPS1N URTS0N
J21 AB6 URXD2
SMPS0N URXD2
R108
J22
SMCS1N
K22 E24 USBVP
SMCS0N USBVP
M23 F22 USBVM VDD12
D SMAD9 USBVM D
3.3K
R109
L24 F23 USBRCV
SMWEN USBRCV
P21 E22 USBSDA
SMOEN USBSDA
N23 G22 USBINTN
SMAD0 USBINTN
3.3K
K23 G23 USBOEN
SMAD1 USBOEN
VDDIOD L23 E23 USBSCL
SMAD2 USBSCL
K24
SMAD3 C120 C121 C122 C123 C124 C125 C126 C127 C128
M22 F5 I2CSCL0
SMAD4 I2CSCL0 0.1u 0.1u 0 .1 u 0.1u 0.1u 0 .1 u 0.1u 0.1u 0.1u
N24 F4 I2CSDA0
10K
SMAD5 I2CSDA0
J23
SMAD6
L22 E21 IT_WAKE_UP_AP
SMAD7 PWLOUT
R110
J24
SMAD8
P24 K5 CCIRID(7)
NAND_READY_AP SMWAITN CCIRID7_CCIROD7
Y23 K3 CCIRID(6)
SMFWPN CCIRID6_CCIROD6
Y24 L4 CCIRID(5)
SMFRSTN CCIRID5_CCIROD5
TP100 W22
V23
SMA_DQ0 U100 CCIRID4_CCIROD4
L5
L3
CCIRID(4)
CCIRID(3)
E SMA_DQ1 CCIRID3_CCIROD3 E
T23 M4 CCIRID(2)
SMA_DQ2 CCIRID2_CCIROD2
T22
V24
SMA_DQ3
SMA_DQ4
STN8810S12B2V1 CCIRID1_CCIROD1
CCIRID0_CCIROD0
M5
M3
CCIRID(1)
CCIRID(0)
U2 4 P5 CCIRIVS VDDIOD VDDIOE VDDIOF
SMA_DQ5 CCIRIIVS
P23 P3 CCIRIHS
SMA_DQ6 CCIRIHS
P22 R5 CCIRICLK
SMA_DQ7 CCIRICLK_CCIROCLK
V22
SMA_DQ8
U23 D9
SMA_DQ9 CCPDAP
U22 E9
SMA_DQ10 CCPDAN
W24 C9
SMA_DQ11 CCPCKP C129 C130 C131 C132 C133 C134 C135 C136 C137
R23 E10
SMA_DQ12 CCPCKN 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u
R22 C8
SMA_DQ13 CCPRSET
VDDIOD T24
SMA_DQ14
R24 V3 MDIS_CSN
SMA_DQ15 CLPWR
EAR_SENSE_N H23 W4
SMPIOWN CLLPHS
AU_PWR_EN E18 V5 DIS_RS
F R111 4.7K SMPIOIS16N CLPCK F
AE7 AA7 LCD_VS
TMPWNG0 CLFPVS
AE8 W3 DIS_WEN
TMPWNG1 CLACDE
AE19 V4
VDDIOA NANDWP0N CLLE
AE20 AC8 SDIS_CSN
NANDWP01 CLCD17 LCD_DATA(0:15)
R112 10K AD8 LCD_NRESET VDDIOC
CLCD16
HCSN_ETMCLK_XTICLK H3 AC6 LCD_DATA(15)
HCSN CLCD15
UART_SW
G5 AB5 LCD_DATA(14)
HALEN_SSPRXD CLCD14
EBI2_ADDR(2)
H4 AC5 LCD_DATA(13)
HADR2_URXD1 CLCD13
EBI2_ADDR(1)
H5 AA6 LCD_DATA(12)
HADR1_UTXD1 CLCD12
HPI_EME_MOD_ETMPSTA1_XTIDAT J5 AA5 LCD_DATA(11)
HADR0 CLCD11
HPI_EME_APE_ETMPSTA2_XTIDAT J4 AD5 LCD_DATA(10)
R113
HBHEN CLCD10 C138 C139 C140 C141 C142 C143 C144

100K
E BI2 _W E_ N G6 AC4 LCD_DATA(9)

100K HWRN_SSPFRM CLCD9 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u
EBI2_OE_N G4 AB4 LCD_DATA(8)
HRDN_SSPCLK CLCD8
E4 AA4 LCD_DATA(7)
R114 HRDY_RTCK CLCD7
HPIEV_IT_STATE_ETMTRIGIN N4 AB3 LCD_DATA(6)
EBI2_DATA(0:15) HPIEV CLCD6
EBI2_DATA(15) E12 Y5 LCD_DATA(5)
C HDAT15 CLCD5 C
EBI2_DATA(14) C11 AA3 LCD_DATA(4)
HDAT14_MSPSCK1 CLCD4
EBI2_DATA(13) D11 Y4 LCD_DATA(3)
HDAT13 CLCD3
EBI2_DATA(12) E11 Y6 LCD_DATA(2)
HDAT12 CLCD2
EBI2_DATA(11) C10 Y3 LCD_DATA(1)
HDAT11_MSPTFS1 CLCD1
EBI2_DATA(10) D10 W5 LCD_DATA(0)
HDAT10_MSPTXD1 CLCD0
EBI2_DATA(9) N3
HDAT9
EBI2_DATA(8) P4 L25
HDAT8 DU1
EBI2_DATA(7) R4 T25 C
HDAT7 DU2
EBI2_DATA(6) R3
HDAT6
EBI2_DATA(5) T5 AE25
HDAT5 GND63
EBI2_DATA(4) T4 AE26
HDAT4 GND64
EBI2_DATA(3) T3 AF24 VDDIOA VDDIOB
HDAT3 GND65
EBI2_DATA(2) U5 AF25 VDDIOA AP_VDD_IO_2.7V
HDAT2 GND66
EBI2_DATA(1) U4 AF26
HDAT1 GND67
EBI2_DATA(0) U3 R115 0
SDRDQMU
SDRDQSU
SDRDQML
SDRRASN
SDRCASN
SDRDQSL
SDRFBCK
SDRCS1N
SDRCS0N
SDRCKE1
SDRCKE0
SDRDQ10
SDRDQ12
SDRDQ13
SDRDQ14
SDRDQ15
SDRDQ11
HDAT0
SDRAD10
SDRAD12
SDRAD13
SDRAD14
SDRAD11
SDRWRN
SDRCKN
SDRCKP
SDRDQ0
SDRDQ1
SDRDQ2
SDRDQ3
SDRDQ4
SDRDQ5
SDRDQ6
SDRDQ7
SDRDQ8
SDRDQ9
SDRAD0
SDRAD1
SDRAD2
SDRAD3
SDRAD4
SDRAD5
SDRAD6
SDRAD7
SDRAD8
SDRAD9
D D
GND10
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND11
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
VDDIOB
C145 C146 C147 C148 C149 C150
0.1u 0.1u 0.1u 0.1u 0.1u 0.1u
AC15
AC14
AB15
AC16
AD12
AA10
AA19
AB22
AD22
AD21
AB13
AC17
AB14
AB16
AB23
AA23
AD19
AD18
AD9
AD17
AD10
AD13
AD16
AD20
AD14
AD15
AA22
AC23
AB21
AC20
AC22
AC19
AC21
AC18
AB19
AB17
AC13
AB12
AC12
AB9
AC10
AC9
AB10
L12
L13
L14
L15
L16
M12
M13
M14
M15
M16
N12
N13
N14
N15
N16
P12
P13
P14
P15
P16
R12
R13
R14
R15
R16
T12
T13
T14
T15
T16
AA24
B2
B3
B24
B25
C2
C25
A1
A2
A3
C1
A24
A25
A26
B26
C26
AD1
AD2
AE1
AE2
AE3
AF1
AF2
AF3
AD25
AD26
AE24
AE16
B1
B7
B8
B16
B19
B20
AD11
AC11
M11
N11
P11
R11
T11
AE11
B11
VDDIOF
TP101
100K
R116
OJ100 OJ101
AP_VDD_IO_1.8V
E E
100K
R117
D100
REMOTE_PWR_ON REMOTE_PWR_ON_AP
RB521S-30
1 2 3 4 5 6 7 8 9
7. CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VCOIN VMMC_3.1V
SUB B2B Con. AP_VDD_IO_2.7V
CN200
1 34
A 2 33 A
Audio Codec. AP_VDD_IO_1.8V AP_VDD_IO_2.7V
3 32
4 31
PON
AP_VDD_IO_1.8V WM_DVDD WM_AVDD
5 30
C200 C201 CLK32K SD_INT
1K
0.1u 6 29
R200 0.1u
1K
7 28
R202
0 U200 ST2378EBJR UCTS0N
E1 E4
VL VCC 8 27
R203
C202
C203
C204
C205
C206
C207
URXD0
E2 E3
PM_SCL IOVL1 IOVCC1 I2CSCL0 9 26
UTXD0 SD_DAT(1)
10u
0.1u
0.1u
10u
0.1u
0.1u
D1 D4
B PM_SDA IOVL2 IOVCC2 I2CSDA0 10 25 B
URTS0N SD_DAT(0)
D2 D3
VGA_RSTN_AP IOVL3 IOVCC3 VGA_RSTN 11 24
C1 C4
C864 C865 IOVL4 IOVCC4 12 23
G2
H7
H6
C8
C9
A7
A8
F8
F9
J7
33p 33p PCMDATAOUT SD_CLK

C2 C3
DGND
DCVDD
DBVDD
NC1
NC2
NC3
NC4
HP_SPKRGND
HPVDD
SPKRVDD
WM_ADCDAT IOVL5 IOVCC5 PCMDATAOUT 13 22
C208 1u PCMDATAIN
A2 E9 B1 B4
WM_HPH_L LINE1 OUT4 WM_DACDAT IOVL6 IOVCC6 PCMDATAIN 14 21
C209 1u PCMCLK SD_CMD
A1 E8 B2 B3
WM_HPH_R LINE2 OUT3 RECEIVER+ WM_LRC IOVL7 IOVCC7 PCMSYNC 15 20
C210 1u PCMSYNC SD_DAT(3)
B1 A1 A4
WM_RXP RXP WM_BCLK IOVL8 IOVCC8 PCMCLK 16 19
D8
C211 1u LOUT1 RECEIVER- BT_RESETN SD_DAT(2)
C2 A3 A2
WM_RXN RXN GND OE LEVEL_SHIFT_EN 17 18
C C866 C867 WM_LOUT1 C215 C216 C295 C218 C

A3
1u
33p 33p ACIN 1u C214 1u 1u 1u 1u

B7
U201 MONO2 WM_MONO2
B3 B6 1u C219
C213
D2
WM_MIC1N MIC1N C863 C862
D9
ROUT1 WM_ROUT1 51p 51p
C1
WM_MIC1P MIC1
C220 1u E2 AP_VDD_IO_2.7V
WM_MIC2N MIC2N
A9
C221 1u D1 LOUT2 WM_LOUT2 VUSB_3.1V
WM_MIC2P MIC2
MSM_UART_RXD
MODE_GPIO3
B4 B9 TP200
C222
CSB_GPIO5
0.1u
GP1_CLK1
GP2_CLK2
D MSM_UART_TXD D
PCMCLK
VXDOUT
DACDAT
ADCDAT
TP201
VXCLK
VXDIN
GPIO4
AGND
PGND
MCLK
PVDD
AVDD
VREF
VXFS
BCLK
SCLK
VMID
SDIN
LRC
C223 REMOTE_PWR_ON
U204 U203 TP202
4.7u
EVLC14S02050
EVLC14S02050
EVLC14S02050
SLAS4717EPMTR2G 1 12
UART_TXD A0 VCC2
A5
A4
A6
B5
J6
G9
H9
G8
J9
J8
J3
J1
J2
H3
J4
H4
H5
J5
F1
H1
G1
F2
E1
1 10 2 9
V CC NO2 MSM_USB_D- UTXD2 0B0 VCC1
11
4.7u
4.7u
0B1 MSM_UART_TXD
100K R209 2 9 4 10
MSM_USB_D+ NO 1 COM2 USB_D- UART_RXD A1 S0 UART_SW
5
URXD2 1B0
C224
C225
100K R210 3 8 3 8
USB_D+ COM1 I N2 GND1 1B1 MSM_UART_RXD
TP205
6 7
GND2 S1
VA803
100K
VA804
VA802
4 7
100K R211 USB_SW I N1 NC 2 AP_USB_D- C226
NLAS3158MNR2G
R212
100K
100K 0.1u
5 6 R207
AP_USB_D+ NC1 G ND R206
SPK_AMP_EN
MSPTXD0
WM_DACDAT
WM_LRC
WM_BCLK
MSPTCK0
MSPTFS0
WM_MSPRXD0
WM_ADCDAT
AU_19.2M
PM_SCL
PM_SDA
VT_SW
E E
CTS
12
WM_AVDD WM_DVDD UART SWITCH 11
10
RTS
DSR
USB SWITCH [ UART_SW = H : MP , L : AP ]

MSM_USB_D+
MSM_USB_D-
9
8
NC4
NC3
UTXD
URXD
[ USB_SW = H : MP , L : AP ] VREG_MSMP_2.6V USB_VBUS
7
NC2 PWR
VBATT VBAT VB A T
R1114D181D U804 6
REMOTE_PWR_ON ON_SW ON_SW
3 1 +5V_PWR 5
VOUT VDD NC1 VCHA R
4
MSM_UART_TXD TX TX
2 4 3
GND1 NC MSM_UART_RXD RX RX
5 6 2
GND2 CE EA R_MIC_L DO_EN GND GND
WM_DVDD 1
2.5G 3G
UT200
F F
C227
10u
R214
R213
1.5K
1M
U803 FSA 4157L 6X
1 6
VT_SW S B1 WM_DACDAT
2 5 VIN- 4 5
VCC GND
3 4 AP_VDD_IO_1.8V VCC 1
MSPRXD0 A B0 WM_MSPRXD0 HOOK_SENSE
18 PIN MMI VIN+ 3 G ND OU T
0.1u
2 U206
330K
NCS2200SQ2T2G
C230
CN201 R215
100K R216
21 CONNECTOR VBATT_SENSE PIN CHECK!!
19 1%
1 R217
WM_MIC2N
2
C WM_MIC2P 470K VBATT_SENSE C
3
47n
FB200 1000
4 R218 100ohm
R220
680K
EAR_L
AP_+VPWR 5
EAR_R
C231
6 R219 100ohm
USB_D+
7
USB_D-
C232
8 FB201
EAR_SENSE_N
AP_+VPWR 9
VBATT
10
C233 C234
2.2u
11 U207 +5V_PWR
10u 1u REMOTE_PWR_ON
12 1 2
IN OUT
13
GND
D6
A5
B5
F1
R836 10K 14
C235
15 NFM18PC104R1C3
2.2u USB_VBUS
CPVSS
VSS
VDD
PVDD
C236 1u 3
A4 16
C1N UART_TXD
A3 17
CPGND WM_MICBIAS UART_RXD
A2 A6 18 U208
D C1P HPL EAR_L D
A1 B6 SPM0204HE5-PB-3
PSD12-LF
CPVDD HPR EAR_R SR C DRAIN
RSB6.8CST2R
RSB6.8CST2R
INSTPAR
1u C237 E3 20 5 4
EVLC18S02003
EVLC18S02003
EVLC14S02050
EVLC14S02050
EVLC14S02050
EVLC14S02050
EVLC14S02050
WM_LOUT2 1u C238 INA1 P
E4 U209 C6 4 C239 1u 22
WM_ROUT2 INA2 OUTRX G2 WM_MIC1N GATE CNTRL
1u C240 E5 MAX9775EBX+T 3 USFB13L D200 6 3
WM_ROUT1 INB1 G1
1u C241 D5 C1 2
WM_LOUT1 INB2 OUTL+ SPK_R+ O OUT GND DNI
B4 E1 1 7 2
33p
47p
47p
WM_MIC1P
R843 2.2K
R844 2.2K
INC1 OUTL- SPK_R-
D201
1u
smd_1608h_9_r
C5 MIC200 C243 1u
INC2 VCC IN
B3 F4 8 1
VBIAS OUTR+ SPK_L+
C250
TP813 C2 F2
C247
C244
C246
PM_SDA SDA OUTR- SPK_L- DRAIN_THERMAL
VA207
VA208
C245
VA202
VA203
VA200
VA201
TP814 D2 9
VA205
VA204
VA206
PGND1
PGND2
PM_SCL SCL NUS3065MUTAG

CR_H
TP203 E2
CR_L
CL_H
CL_L
GND
SPK_AMP_EN _SHDN
39p
C251
F6
D1
F3
E6
F5
B1
B2
1u
TA OVP Circuit
C252
C253
C254
C255
E E
2200p
22n
2200p
22n
AUDIO SUBSYSTEM
1 2 3 4 5 6 7 8 9
7. CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A A
AP_+VPWR AP_+VPWR AP_VDD_IO_1.8V AP_VCORE
AP_VDD_IO_1.8V
C300
0.1u
1 10 R300 100K
VCC NO2
100K 2 9
NO1 COM2 IT_WAKE_UP_AP
R301 L300 L301
3 8 4.7uH 4.7uH
COM1 IN2 IT_WAKE_UP
R855 4 7
AP_VDD_IO_1.8V VREG_MSMP_2.6V MSM_RESIN_N IN1 NC2 B
R854 20
5 6
AP_PON NC1
GND
DNI
C304
C307
C305
C303
C306
NLAS5223BMNR2G
U300
C301 0.1u C302 0.1u
22u
22u
4.7u
4.7u
4.7u
PON
U301
B4
B6
ST4G3235BJR
VCCB
VCCA
TP817 A1 C1
SLEEP_CLK A4 B4
D10
C10
B10
A10
C4
C6
D9
D8
C9
A4
B4
A3
B3
A2
A5
B5
A3 C3
A3 B3
C308
VLX_VIO_VMEM1
VLX_VIO_VMEM2
VMINUS_VIO_VMEM1
VMINUS_VIO_VMEM2
VIO_VMEM
VMINUS_ANA
VLX_VCORE1
VLX_VCORE2
VMINUS_VCORE1
VMINUS_VCORE2
VCORE
VBAT_VIO_VMEM1
VBAT_VIO_VMEM2
VBAT_ANA
VBAT_VCORE1
VBAT_VCORE2
A5 C5
A2 B2 0.1u C
D1
VBAT_DIG C309 0.1u
A7 C7 C3 C7
MCLK_27MHZ A1 B1 MCAM_CLK_OUT VMINUS_DIG VBAT_VPLL_FUSE
GND
A8
VPLL AP_VPLL
C8
PON
B2
A1 A7
CLK32K CLK32K_IN VFUSE AP_VFUSE
R302 47K D2
MASTER_CLK C310 1u
A9
VREF_18
C2
IT_WAKE_UP IT_WAKE_UP
B2 B6
REQUEST_MC REQUEST_MC VBAT_VAUX
C1 A6
AU_PWR_EN TCXO_EN VAUX
H6 F9 C311 1u
PWREN PWREN VBAT_USB C313 C314 VUSB_3.1V
J2 J9
R303 VDDOK VDDOK VMINUS_USB 1u 1u
J3 H10 470n C312
PORN PORN CP USB_VBUS_IN
K3 J10
0 CLK32K CN
K4
SW_RESET D
F10
VUSB
J6 G10
PM_SCL SCL U302 VBUS C315 C316
H7
PM_SDA SDA STW4810AHDT_LF 1u 4.7u
E8
ID
J7
USBVP USBVP R304 20
K8 E9
USBOEN USBOEN DP AP_USB_D+
J8 E1 0
USBVM USBVM DN AP_USB_D-
K7 R305 20
USBRCV USBRCV
H8 J4
USBINTN USBINTN VBAT_MMC
G9
USBSCL USBSCL
H9 K5
USBSDA USBSDA VMMC VMMC_3.1V
TP308 G2 F3
MCCLK MCCLK LATCHCLK C317
H5 G1
MCFBCLK MCFBCLK CLKOUT 2.2u
R306 100ohm TP310 G3
MCCMDDIR MCCMDDIR
TP311 H1 F1
MCCMD MCCMD DATAOUT3 E
TP312 K2 E3
C318 MCDAT0DIR MCDAT0DIR DATAOUT2
K1 E2
120p MCDAT0 MCDATA0 DATAOUT1 SD_CLK
H4 E1
MCDAT31DIR MCDATA31DIR DATAOUT0 SD_DAT(3)
H3 F2
MCDAT1 MCDATA1 CMDOUT SD_DAT(2)
H2
MCDAT3 MCDATA3 SD_DAT(1)
TP317 K9 J5
MCDAT2DIR MCDAT2DIR GPO1 SD_DAT(0)
TP318 J1 K6
MCDAT2 MCDATA2 GPO2 SD_CMD
GND1
GND2
NC1
NC2
NC3
NC4
NC5
NC6
NC7
B1
B7
B8
C5
F8
G8
K10
B9
D3
C319
1u
VREG_USIM_2.85V
AP_+VPWR AP_VDD_IO_2.7V AP_+VPWR WM_AVDD J300 5000-6P-1.8SL

1 4
R307
C1 C5
12K
2 5
USIM_P_RST_N C2 C6
3 6
+VPWR USIM_P_CLK C3 C7 USIM_P_DATA
AP_+VPWR 7 10
GND1 GND4
8 9
GND2 GND3
U303 BH33FB1WHFV
U304 1 5
AU_PWR_EN STBY NC
0
C320
C321
C322
MIC5219-2.7YM5 2 6
GND BGND C
1 5 3 4
IN OUT VIN VOUT
2
GND
L302
0.1u
3 4
10p
27p
PON EN BYP
470p
2.2u
C323
C324 C327 2.2u
1u 0.1u
C325
C326
USIM Connector
D
AP_VDD_IO_1.8V
AP_VDD_IO_1.8V
C328 0.1u
U305
NC7WZ08L8X
X300
CSC3M192000EEVRS00 PWREN 7 A1 VCC 8 E
4 3 6 1
VD D OUT B1 Y1 CPU_19.2M
1 2 5 2
REQUEST_MC TRI_OPEN GND AU_19.2M Y2 B2 AU_PWR_EN
19.2MHz 4 GND A2 3
C329
0.1u
1 2 3 4 5 6 7 8 9
7. CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
AP_VDD_IO_2.7V
A
MAIN-FOLDER CON-SOCKET A
CAMERA EMI/ESD FILTER CN400

G2 G1
70 1
2
4
6
8
2
4
6
8
LCD_NRESET
RA400 100K
RA401 100K
69 2 0 R400
68 3
FL400 EVRC18S03Q015050R 67 4
1 9 66 5
R404 0 INOUT_A1 INOUT_B1 WLED_nRST LCD_DATA_O_2
1 2 3 4 SHIFT_L LSK MENU MCLK_27MHZ_CAM
2
INOUT_A2 INOUT_B2
8
MCLK_27MHZ
65 6
LCD_DATA_O_0
SW406 64 7
1
3
5
7
1
3
5
7
SW400 SW401 SW402 SW403 SW404 SW405 3 7

I2CSDA0_CAM INOUT_A3 INOUT_B3 I2CSDA0_SW MCLK_27MHZ_CAM LCD_DATA_O_8
4 6 63 8
I2CSCL0_CAM INOUT_A4 INOUT_B4 I2CSCL0_SW LCD_DATA_O_10
62 9
MENU_KEY CCIRICLK LCD_DATA_O_12
G1
G2
R856 61 10
KEY_ROW(0) CCIRIHS LCD_DATA_O_14
60 11
5
10
100o h m 5 6 7 8 SHIFT_R RSK CCIRIVS LCD_DATA_O_15
SW407 SW408 SW409 SW410 SW411 SW412 59 12
B CCIRID(7) LCD_DATA_O_13 B
58 13
57 14
56 15
KEY_ROW(1) CCIRID(4) LCD_DATA_O_7
9 0 Q W CHR OK 55 16
SW413 SW414 SW415 SW416 SW417 SW418 FL401 EVRC18S03Q015050R 54 17
1 9 53 18
CCIRID(3)_CAM INOUT_A1 INOUT_B1 CCIRID(3) CCIRID(1) LCD_DATA_O_1
2 8 52 19
R851 CCIRID(2)_CAM INOUT_A2 INOUT_B2 CCIRID(2) CCIRID(0) R402 0 SDIS_CSN_O
3 7 51 20
KEY_ROW(2) CCIRID(1)_CAM INOUT_A3 INOUT_B3 CCIRID(1) VGA_STANDBY DIS_WEN_O
100o h m E R T Y CTRL SHOT CCIRID(0)_CAM
4
INOUT_A4 INOUT_B4
6
CCIRID(0) VGA_RSTN
50 21
MDIS_CSN_O
0 R403 49 22
SW419 SW420 SW421 SW422 SW423 SW424 I2CSDA0_CAM DIS_RS_O
G1
G2
48 23
C400 I2CSCL0_CAM
47 24
5
10
1u
46 25
KEY_ROW(3) I2CSCL0
U I O P A SEND 45 26
I2CSDA0
SW425 SW426 SW427 SW428 SW429 SW430 44 27
43 28
C KEY_ROW(0) RECEIVER- C
42 29
41 30
KEY_ROW(4) KEY_ROW(2)
S K L G H LEFT FL402 EVRC18S03Q015050R 40 31
KEY_ROW(3) SPK_R+
SW431 SW432 SW433 SW434 SW435 SW436 1 9 39 32
CCIRID(7)_CAM INOUT_A1 INOUT_B1 CCIRID(7) KEY_ROW(4) SPK_R-
2 8 38 33
CCIRID(6)_CAM INOUT_A2 INOUT_B2 CCIRID(6) KEY_ROW(5)
3 7 37 34
CCIRID(5)_CAM INOUT_A3 INOUT_B3 CCIRID(5) KEY_COL(6) SPK_L-
4 6 36 35
KEY_ROW(5) CCIRID(4)_CAM INOUT_A4 INOUT_B4 CCIRID(4) KEY_COL(7) SPK_L+
J D F Z X BACK SPACE UP
G1
G2
SW437 SW438 SW439 SW440 SW441 SW442 SW443 SW444 G4 G3
C401 C402
5
10
1u AXT570124 1u
C403 C404 C405 C406 C407 C408
KEY_ROW(6) 47p 47p 22p 22p 22p 22p
C V B N M ENTER RIGHT DOWN
10
5
D D
G1
G2
KEY_ROW(7)
CCIRIHS_CAM INOUT_A4 INOUT_B4 CCIRIHS
4 6
CCIRIVS_CAM INOUT_A3 INOUT_B3 CCIRIVS
3 7
KEY_COL(0) CCIRICLK_CAM INOUT_A2 INOUT_B2 CCIRICLK
2 8
KEY_COL(1) CAMCLK_24MHZ_CAM INOUT_A1 INOUT_B1 CAMCLK_24MHZ
1 9
KEY_COL(2) R405 0
FL403 EVRC18S03Q015050R
KEY_COL(3)
KEY_COL(4)
KEY_COL(5)
KEY_COL(6)
KEY_COL(7)
EVLC14S02050
EVLC14S02050
E E
LCD EMI/ESD FILTER AP_VDD_CAM_AVDD_2.7V

VA402
AP_VDD_CAM_IO_2.7V
VA805
AP_VDD_CAM_1.8V
2M CAM Connector
EVRC14S03Q030100R FL404
HB-1M1005-601JT
HB-1M1005-601JT
HB-1M1005-601JT
9 1 CN402
LCD_DATA_O_6 INOUT_B1 INOUT_A1 LCD_DATA(6) G1 G2
8 2
7 3 1 24
6 4 2 23
FB400
FB402
LCD_DATA_O_0 INOUT_B4 INOUT_A4 LCD_DATA(0) CCIRID(7)_CAM I2CSCL0_CAM
FB401
AP_VDD_IO_2.7V
KEYCODER IC CCIRID(6)_CAM
3 22
I2CSDA0_CAM
G2
G1
4 21
CCIRID(5)_CAM
5 20
10
5
4
F VOL_UP KEY_ROW(6)
3
CCIRID(4)_CAM
6 19
CCIRIVS_CAM F
KEY_COL(5) CCIRID(3)_CAM CCIRIHS_CAM
R406
R407
2 7 18
VOL_DOWN KEY_ROW(7) CCIRID(2)_CAM
8 17
CAMCLK_24MHZ_CAM
KEY_ROW(0:7) 1 CCIRID(1)_CAM
EVLC14S02050
EVLC14S02050
EVLC14S02050
CN401 9 16
CCIRID(0)_CAM
3.3K
3.3K
10 15
CCIRICLK_CAM
EVRC14S03Q030100R FL405 11 14
KEY_ROW(1)
KEY_ROW(0)
KEY_ROW(3)
KEY_ROW(2)
I2CSCL1 2M_RSTN
KEY_ROW(7)
KEY_ROW(6)
KEY_ROW(5)
KEY_ROW(4)
9 1 12 13
I2CSDA1 LCD_DATA_O_8 INOUT_B1 INOUT_A1 LCD_DATA(8) 2M_PWDN
8 2
LCD_DATA_O_10 INOUT_B2 INOUT_A2 LCD_DATA(10) C409 TP400
C412
C415
C411
C410
C413
C414
7 3 G3 G4
6 4 0.1u
LCD_DATA_O_14 LCD_DATA(14)
ZD401
ZD402
ZD403
INOUT_B4 INOUT_A4
G2
G1
0.1u
0.1u
0.1u
10u
10u
10u
10
5
G6
G7
C7
D7
D6
C2
C1
C6
A7
B6
E7
E6
B7
F7
F5
F6
C C
KEY_COL(3:0)
SCL_AB
SDA_AB
NC5
NC6
NC7
NC8
NC1
NC2
NC3
NC4
Wake_INP5
Wake_INP4
Wake_INP1
Wake_INP0
Wake_INP3
Wake_INP2
A6 G5 KEY_COL(3) EVRC14S03Q030100R FL406

B5 G4 9 1
KEY_COL(4) Wake_INP7 K_Out2 KEY_COL(1) END (POWER_ON) LCD_DATA_O_15 INOUT_B1 INOUT_A1 LCD_DATA(15)
A5 F4 8 2
KEY_COL(5) K_Out4 U400 K_Out1 KEY_COL(0) LCD_DATA_O_13 INOUT_B2 INOUT_A2 LCD_DATA(13) AP_VDD_IO_2.7V
B4 G3 SW453 7 3
KEY_COL(6) K_Out5 LM8333GGR8_NOPB K_Out0 LCD_DATA_O_11 INOUT_B3 INOUT_A3 LCD_DATA(11)
A4 F3 6 4
KEY_COL(7) K_Out6 _RESET KEYCODER_RSTN LCD_DATA_O_9 INOUT_B4 INOUT_A4 LCD_DATA(9)
A3 G2
K_Out7 Int_Rx KEY_ON_SW_N I2CSDA0_SW
G2
G1
B3 G1
Gen_IO_0
Gen_IO_1
Gen_IO_2 WD_Out
Gen_In1
Gen_In0
10
5
A2 F2
CLK_In
Gen_IO_3 Int_Tx KEYCODER_INT I2CSCL0_SW

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
VCC1
VCC2
PWM
I2CSDA0
U401
B2
A1
B1
TP401 D2
D1
F1
E1
E2
C3
C4
C5
D3
D4
D5
E3
E4
E5
ZD404 EVLC14S02050 SLAS4717EPMTR2G

1 10
VCC NO2
D D
EVRC14S03Q030100R FL407 2 9
I2CSCL0 NO1 COM2
C416 C417 9 1
8 2 3 8
LCD_DATA_O_5 INOUT_B2 INOUT_A2 LCD_DATA(5) C O M1 I N2
7 3
68K

0.1u 0.1u 6 4 4 7
LCD_DATA_O_1 INOUT_B4 INOUT_A4 LCD_DATA(1) CAM_I2C_CTL IN1 NC2
PWR_BTN
MENU_KEY
TP402
G2
G1
R408
5 6
NC1 G ND
10
5
KEYPAD LED
AP_VDD_IO_2.7V
+VPWR AP_+VPWR
FL408 EVRC14S03Q030100R
U402 BU52031NVX 9 1
E SDIS_CSN_O INOUT_B1 INOUT_A1 SDIS_CSN E
8 2
DIS_WEN_O INOUT_B2 INOUT_A2 DIS_WEN
1 4 AP_VDD_IO_2.7V 7 3
FOLDER_DETECT OUT VDD MDIS_CSN_O INOUT_B3 INOUT_A3 MDIS_CSN
PGND
2 3 6 4
GND NC LD400 LEWWS44-E R409 R852 DIS_RS_O INOUT_B4 INOUT_A4 DIS_RS
C418 KPD_MAIN_DRV_N
G2
G1
0.1u 68 51
5
10
5

VA416
68 EVL14S02200

68
68
FOLDER_SENSE
F
1 2 3 4 5 6 7 8 9
7. CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
WDOG_EN (1:Enable , 0:Disable)

Default Pull-up MODE
ADC HKADC(4):PCB_Rev_ADC
MODE2 MODE1 MODE0 ( Default Pull-Down)
150K : 10K : 0.016V
0 0 0 Native, ARM JTAG HKADC[0] - AMUX_OUT
WM_MONO2
WM_MONO1
A 150K : 47K : 0.62V A
0 1 0 Native, MSM JTAG HKADC[1] - VBATT_SENSE
HKADC[2] 150K : 68K : 0.81V
BOOT_MODE2 BOOT_MODE
WM_HPH_R
WM_HPH_L
HKADC[3] - VBAT_TEMP 150K : 100K : 1.04V
WM_RXN
WM_RXP
X 0 NOR boot HKADC[4] - PCB_Rev_ADC
150K : 150K : 1.30V
VREG_MSMP_2.6V VREG_MSMP_2.6V 0 1 8-bit, NAND boot HKADC[5]
1 1 16-bit, NAND boot 150K : 300K : 1.73V
PMIC_AUXIN[1] 150K : 470K : 1.97V
BOOT_MODE3
PMIC_AUXIN[2] - PA_THERM 150K : 680K : 2.13V
0 Normal boot
150K : 750K : 2.17V
R501
1 Trusted boot
1005 0.1uF 16V +80/-20%
R500
RESOUT_EBI2_N
2012 10uF 6.3V +80/-20% Ceramic
SDRAM_CS_N(0)
SDRAM_CLK_EN
R502
SDRAM_DQM(3)
SDRAM_DQM(2)
SDRAM_DQM(1)
SDRAM_DQM(0)
300K
150K
SDRAM_RAS_N
SDRAM_CAS_N
47K
MSM_RESIN_N
SDRAM_WE_N
100K
SDRAM_CLK
BUFF_TCXO
SLEEP_CLK
VREG_MSMC_1.2V
100K
VREG_MSME_1.8V VREG_MSMP_2.6V VREG_MSMA_2.6V
R830
R829
B B
SDRAM_ADDR(0:14) 10u (CAD : 10uF=>Input MSMA_2.6V)

C500
SDRAM_ADDR(0)
SDRAM_ADDR(1)
SDRAM_ADDR(2)
SDRAM_ADDR(3)
SDRAM_ADDR(4)
SDRAM_ADDR(5)
SDRAM_ADDR(6)
SDRAM_ADDR(7)
SDRAM_ADDR(8)
SDRAM_ADDR(9)
SDRAM_ADDR(10)
SDRAM_ADDR(12)
SDRAM_ADDR(13)
SDRAM_ADDR(14)
SDRAM_ADDR(11)
C502 C501 C503 C504
R504
R503
10n 10u 0.1u 0.1u
R505
VBATT_SENSE
(1608)
Place near C854 C853 C852 C851 C510 C511 (1608)
VBAT_TEMP
AMUX_OUT
C505
MSM pin W18
0.1u 39p 39p 39p 39p 10p 10p
51
TP500
10% (CODEC VSS)
DNI
TP818
C512 C513 C514 C515
AC18
AC17
AC22
AC21
AC19
AC20
AE17
AE21
AE22
AA23
AB23
AA17
AE18
AA18
AA19
AE19
AE20
AA20
AF18
AF19
AF21
AF22
AF20
W21
W17
10n 10 n 1 0n 0.1u C516 C517 C518 C519 C520
AD1
AB1
AA2
AA4
D18
U23
A10
B10
A16
B16
Y23
V21
V19
Y21
N11
F13
T21
T15
P11
F11
W6
M8
M4
M6
G1
N8
N6
N2
N1
N4
U8
U4
V1
P1
P2
P6
P8
Y4
K8
V8
V2
L1
L4
L2
10n 10n 0.1u 0.1u 0.1u
A1_24_GPIO79
A1_1
A1_2
A1_3
A1_4
A1_5
A1_6
A1_7
A1_8
A1_9
A1_10
A1_12
A1_13
A1_14
ROM1_CLK_SDRAM1_CLK
XMEM1_CS_N2_SDRAM1_CS_N0
SDRAM1_CLK_EN
ROM1_ADV_N_SDRAM1_RAS_N
WE1_N_SDRAM1_WE_N
A1_25_SDRAM1_DQM3_GPIO75
A1_23_SDRAM1_DQM2_GPIO78
UB1_N_SDRAM1_DQM1
LB1_N_SDRAM1_DQM0
OE1_N
XMEM1_CS_N0
TCXO
RESIN_N
RESOUT_N
RESOUT_N_EBI1
WDOG_EN
MODE2
MODE1
MODE0
BOOT_MODE
BOOT_MODE2
BOOT_MODE3
HKAIN0
HKAIN1
HKAIN2
HKAIN3
HKAIN4
HKAIN5
LINE_ON
LINE_OP
HPH_R
HPH_L
EAR1ON
EAR1OP
MICBIAS
AUXOUT
HPH_VREF
LINE_L_IP
LINE_L_IN
LINE_R_IP
LINE_R_IN
AUXIN
AUXIP
MIC2N
MIC2P
MIC1N
MIC1P
CCOMP
SDRAM_DATA(0:31)
XMEM1_HWAIT_N
C C
A1_11
USB_XTAL48_IN
USB_XTAL48_OUT
SLEEP_XTAL_IN
SLEEP_XTAL_OUT
XMEM1_LWAIT_N_SDRAM1_CAS_N
F25
SDCC_DAT1_GPIO99
SDRAM_DATA(31) T8 M25
A1_22 SDCC_DAT2_GPIO100
SDRAM_DATA(30) T6 M26
A1_21 SDCC_DAT3_GPIO101
SDRAM_DATA(29) T4 AE3 C521 C522 C523
A1_20 MDP_VSYNC_SECONDA_GPIO104 C524 C525 C526 C527 C528 C529
SDRAM_DATA(28) R8 AD2
A1_19 MDP_VSYNC_PRIMARY_GPIO105 1000 pF1000 pF 1000 pF 10n 10n 10n 10n 0.1u 0.1u 2200p cap => place between
SDRAM_DATA(27) T2
A1_18
SDRAM_DATA(26) T1 H25 D12(VDDA1) and F12(DAC_REF)
A1_17 WDOG_STB_SBCK1_GPIO0
SDRAM_DATA(25) R6 F26
C530
A1_16 SBDT1_GPIO1
2.2n
SDRAM_DATA(24) R4 H11
A1_15 PA_ON1_GPIO2
SDRAM_DATA(23) W4 D5
GPIO_74 GRFC9_GPIO12 DAC_REF
SDRAM_DATA(22) V6 J21
GPIO_73 CAMCLK_PO_GP_MN_GPIO13 CAMCLK_24MHZ
SDRAM_DATA(21) Y2 A6
GPIO_72 GPIO28 PWR_BTN
SDRAM_DATA(20) Y1 N19 C531 C532 C533 C534 C536 C537 C538
GPIO_71 USB_RX_DATA_GPIO29 C535 C539 C540 C541
SDRAM_DATA(19) E1 W15
D GPIO_70 XMEM2_CS_N2_GPIO35 HCSN_ETMCLK_XTICLK 1000 pF 1000 pF 1000 pF 1000 pF 10n 1000 pF 1000 pF 1000 pF 0.1u 0.1u 0.1u D
SDRAM_DATA(18) R11 AA15
GPIO_69 XMEM2_CS_N3_GPIO36
SDRAM_DATA(17) V4 AE13
GPIO_68 LCD_EN_GPIO37 FOLDER_DETECT Near to B18 (VDD_PLL)
SDRAM_DATA(16) U6 H9
GPIO_67 GPIO43 AP_PON
SDRAM_DATA(15) L6 B6 VREG_MSMA_2.6V
SDRAM1_D15 SYNTH2_GPIO65
SDRAM_DATA(14) L8 F8
SDRAM1_D14 GPIO66 TP501
SDRAM_DATA(13) K4 AA1
SDRAM1_D13 XMEM1_CS_N1_GPIO76 CAM_IF_PWDN BUFF_TCXO_FF
SDRAM_DATA(12) J1 Y6
SDRAM1_D12 XMEM1_CS_N3_SDRAM1_CS_N1_GPIO77 EAR_SENSE_N
SDRAM_DATA(11) K6 L25
SDRAM1_D11 UART3_RFR_N_GPIO87 VREG_TCXO_2.85V
SDRAM_DATA(10) J2 H6 NC7SZ74L8X U500
SDRAM1_D10 UART2_DP_RX_DATA_GPIO89 C542 C543 C544
SDRAM_DATA(9) J4 F18 8 1
SDRAM1_D9 SYNTH0_GP_PDM0_GPIO92 RTC_CONT VCC _PR 0.1u 0.1u 10n
SDRAM_DATA(8) P4 H18
AE16
AE15
AA26
AE23
AE24
AA16
AF17
AE11
SDRAM1_D8 SBST1_GPIO93 EAR_MIC_LDO_EN
AC2
AE8
G25
AE6
D25
R25
D12
U25
U26
B24
B14
K25
B15
B18
B21
P23
Y26
T25
B11
10%
W2
M2
7 2
C2
H2
R2
U2
SDRAM_DATA(7) H4
B5
K2
B9
A3
F2
SDRAM1_D7 C545 CK _CLR
SDRAM_DATA(6) G2 H13
SDRAM1_D6 TX_AGC_ADJ
VDD_DIG_0
VDD_DIG_1
VDD_DIG_2
VDD_DIG_3
VDD_DIG_4
VDD_DIG_5
VDD_DIG_6
VDD_DIG_7
VDD_DIG_8
VDD_DIG_9
VDD_DIG_10
VDD_DIG_12
VDD_PLL
VDD_MDDI
(VDD_DAC_REF) VDDA1
VDDA2
VDDA3
VDDA4
VDDA5
VDDA6
VDDA7
VDDA8
VDDA9
VDDA10
VDD_DIG_11
VDD_PAD1_0
VDD_PAD1_1
VDD_PAD1_2
VDD_PAD1_3
VDD_PAD1_4
VDD_PAD2_0
VDD_PAD2_1
VDD_PAD2_2
VDD_PAD3_0
VDD_PAD3_1
VDD_PAD3_2
VDD_PAD3_3
VDD_PAD4_0
SDRAM_DATA(5) J6 L13 33p 6 3 R506
SDRAM1_D5 TRK_LO_ADJ D Q TRK_LO_ADJ
SDRAM_DATA(4) AB4 F19
SDRAM1_D4 TCXO_EN_GPIO94 TCXO_EN 2K
SDRAM_DATA(3) D1 F17 5 4
E SDRAM1_D3 PA_ON0 PA_ON _Q GND C546 E
SDRAM_DATA(2) AB2 C26
SDRAM1_D2 33nF RESERVED
SDRAM_DATA(1) D2 A12 F1
SDRAM1_D1 Q_OUT_N TX_QM VSS_PAD1_0
SDRAM_DATA(0) E2 B12 K1
SDRAM1_D0 Q_OUT TX_QP VSS_PAD1_1 (PLLOUT_TEST)
A13 M1 C1
I_OUT_N TX_IM VSS_PAD1_2 VSS_DIG_0
B13 R1 H1
I_OUT TX_IP VSS_PAD1_3 VSS_DIG_1
AC15 F12 U1 W1
XMEM2_CS_N1 DAC_REF DAC_REF VSS_PAD1_4 VSS_DIG_2
AF14 AC1
LCD_CS_N_GPIO38 VSS_DIG_3
W23 AF6 AF8
Q_IM_CH1 GPS_QN VSS_PAD2_0 VSS_DIG_4
NAND_CLE
NAND_CS_N
AF10
W14
UB2_N
XMEM2_CS_N0
U501-1 Q_IP_CH1
I_IM_CH1
V23
V25
GPS_QP
GPS_IM
AF11
AF15
VSS_PAD2_1
VSS_PAD2_2
VSS_DIG_5
VSS_DIG_6
AF16
T26
AF7 W25 G26
EBI2_OE_N OE2_N I_IP_CH1 GPS_IP VSS_DIG_7
AF4 AA25 R26 D26
EBI2_WE_N
NAND_ALE
AE10
T14
WE2_N
LB2_N_A2_0
MSM6280_A Q_IM_CH0
Q_IP_CH0
Y25
AB25
RX_QM
RX_QP
B17
A15
VSS_PAD3_0
VSS_PAD3_1
VSS_DIG_8
VSS_DIG_9
A24
A14
NAND_READY NAND2_FLASH_READY_GPIO33 I_IM_CH0 RX_IM VSS_PAD3_2 VSS_DIG_10
AC25 A9 A11
EBI2_DATA(0:15) I_IP_CH0 RX_IP VSS_PAD3_3 U501-2 VSS_DIG_11
A5
F MSM6280_B VSS_DIG_12 F
EBI2_DATA(15) AA10 A18 AC23
D2_15 (WCMDA PAM MODE) VSSA1 VSS_DIG
EBI2_DATA(14) AC9 D17 A21
D2_14 GP_PDM2_PA_RAN_GE1 VSSA2
EBI2_DATA(13) W10 H17 D13
D2_13 GP_PDM1_PA_RAN_GE0 PA_R0 VSSA3
EBI2_DATA(12) AA9 D19
D2_12 VSSA4
EBI2_DATA(11) AE7 H15 P26 AA21
D2_11 TRST_N VSSA5 NC
EBI2_DATA(10) AC8 D16 U19
D2_10 TCK VSSA6
EBI2_DATA(9) W9 F15 V26 AA6
D2_9 TMS VSSA7 VSS39
EBI2_DATA(8) AA8 D15 W16 AC4
D2_8 TD I VSSA8 VSS41
EBI2_DATA(7) AC7 A17 W18 AE1
D2_7 TDO VSSA9 VSS43
EBI2_DATA(6) AF5 H16 W26 AE2
D2_6 RTCK VSSA10 VSS44
EBI2_DATA(5) AA7 AB26 AE25
D2_5 VSSA11 VSS45
EBI2_DATA(4) AE5 K19 R507 51K AC16 AE26
D2_4 AUX_PCM_CLK_GRFC14_GPIO80 VSSA12 VSS46
EBI2_DATA(3) AC6 N21 AC26 AF1
D2_3 AUX_PCM_DIN_GRFC13_GPIO14 GPS_LNA_EN VSSA13 VSS47
EBI2_DATA(2) AE4 G4 AD25 AF2
D2_2 AUX_PCM_DOUT_GRFC12_GPIO103 TP502 VSSA14 VSS48
EBI2_DATA(1) AF3 J8 AF23 AF25
D2_1 AUX_PCM_SYNC_GRFC11_GPIO102 VSSA15 VSS49
EBI2_DATA(0) AC5 H12 AF24 AF26
C D2_0 TX_ON_GRFC10 TX_ON VSSA16 VSS50 C
VSS10
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS11
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
B4
AF13 T23
A2_20_GPIO34 GRFC7_GPIO10 ANT_SEL1
A1
A2
A25
A26
B1
B2
B25
B26
D4
D23
F6
F21
H8
H19
K10
L16
M12
M13
M14
M15
N12
N13
N14
N15
P12
P13
P14
P15
R12
R13
R14
R15
T16
W8
W19
L11
M11
T11
AA14 T19
A2_19 GRFX6_GPIO9 ANT_SEL0
T13 D11
A2_18 GRFC5_AUX_SBST_GPIO8
AC14 H10
A2_17 GRFC4_AUX_SBCK_GPIO7
AE14 F10
A2_16 GRFC3_GPIO6
W13 D9
A2_15 GRFC2_GPIO5
AC13 A8
A2_14 GRFC1_AUX_SBDT_GPIO4
AA13 B8
A2_13 GRFC0_GPIO3
AF12
UART1_RFR_N_PA_POWER_CTL_M_GPIO98
A2_12 TP504
AE12 G23
A2_11 BT_CLK_GPIO25 HPIEV_IT_STATE_ETMTRIGIN
AC12 F23 for VSS_THERMAL
A2_10 BT_SBST_GPIO24 HPI_EME_APE_ETMPSTA2_XTIDAT
CAMIF_DATA2_AUX_TRST_N_GPIO54
AA12 E26
A2_9 BT_SBCK_GPIO23 HPI_EME_MOD_ETMPSTA1_XTIDAT
W12 E25
CAMIF_DATA6_AUX_TDO_GPIO58
CAMIF_DATA4_AUX_TMS_GPIO56
CAMIF_DATA3_AUX_TCK_GPIO55
MMC_DATA_SDCC_DAT0_GPIO32
A2_8 BT_SBDT_GPIO22
CAMIF_DATA5_AUX_TDI_GPIO57
TP505
MMC_CLK_SDCC_CLK_GPIO31
T12 H21
D A2_7 BT_TX_RX_N_GPIO21 HPI_IT_MOD_ETMSYNCA_XTIDAT D

AC11 R19 TP506

A2_6 BT_DATA_GPIO20 HPI_IT_APE_ETMPSTA0_XTIDAT
AA11
A2_5
KEYSENSE4_N_GPIO48
KEYSENSE3_N_GPIO47
KEYSENSE2_N_GPIO46
KEYSENSE1_N_GPIO63
KEYSENSE0_N_GPIO62
CAMIF_HSYNC_GPIO15
UART2_RFR_N_GPIO91
CAMIF_VSYNC_GPIO16
UART1_CTS_N_GPIO97
UART2_CTS_N_GPIO90
UART3_CTS_N_GPIO86
AC10 A22
CAMIF_DATA9_GPIO61
CAMIF_DATA8_GPIO60
CAMIF_DATA7_GPIO59
CAMIF_DATA0_GPIO83
CAMIF_DATA1_GPIO81
CAMIF_PCLK_GPIO82
A2_4 MDDIC_DATP
W11 A23
MMC_CMD_GPIO30
GSM_PA_DAC_REF
A2_3 MDDIC_DATN
EBI2_ADDR(2)
I2C_SDA_GPIO26
AF9 B22
I2C_SCL_GPIO27
SYNTH1_GPIO41
RINGER_GPIO18
PA_POWER_CTL
A2_2 MDDIC_STBP
USB_OE_TP_N
EBI2_ADDR(1) AE9 B23

USB_SE0_VM
VDD_EF_USE
MDDIH_STBN
MDDIH_DATN
MDDIH_STBP
USB_DAT_VP
MDDIH_DATP
A2_1 MDDIC_STBN
GPIO45
GPIO53
GPIO52
GPIO51
GPIO50
GPIO49
GPIO44
GPIO39
GPIO64
GPIO40
GPIO42
GPIO19
GPIO17
SBCK
SBDT
SBST
U21
R23
D14
P19
R21
A4
L12
D10
A7
B7
F9
P21
P16
470 M23
L26
470 D8
F7
F14
F4
G6
E4
L23
M21
M19
D6
D7
N26
N23
N25
H14
L14
M16
H26
J23
L21
K21
N16
F20
F16
D20
L15
J19
D22
C25
D21
B3
E23
K23
J25
J26
G21
K26
H23
L19
P25
AD26
A19
A20
B19
B20
R16
R508
100K
TP507
R831
R832
E E
MSM_USIM_CLK
MSM_USIM_RST_N
MSM_UART_RXD
MSM_UART_TXD
2M_RSTN
PM_INT_N
PS_HOLD
RF_SBDT
PM_SBDT
2M_PWDN
CAM_IF_POWER
USB_OE_N
USB_SE0
USB_DAT
MSM_USIM_DATA
GSM_PA_RAMP
GSM_PA_DAC_REF
10% Place near

C547
0.1u MSM pin AD26
F
(Check CAM_DATA PINOUT !!!!)
1 2 3 4 5 6 7 8 9
7. CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
KMS-518
ANT601 SW601
2.7nH L601 8.2nH
C
A
C603 TX_IP
C602
G1
G2
C604 56p
C606
100p
GSM 68p
C607
ANT606 5 4
30p
A C609 A
L602 L603 L604
RF TRANCEIVER
G2 O2
IN
C608 15nH 100nH 1 G1 O1 18nH 68nH
1.2p TX_IM
3FL0F00
SAFEB9242M
FL601
U602 RTR6285 TX_QP
L606 8.2nH 26 64
TX_ON RF_ON TX_IP C611
2 63
ANT_SEL2 RTR6275_TCXO
20
T C XO TX_IN
66
68p
RF_SBDT SBDT TX_QP
SKY77519 U601 65
C612 100p TX_QN
55
GSM_TX LB_RF_OUT1 C613 0.01u TX_QM
28 8 57 5
ANT_SEL0 27
BS1 ANT LB_RF_OUT2 VTUNE1
24 C614 0.01u
ANT_SEL1 BS2
1 L607 3.3nH C615 22p 56
VTUNE2
9 C616 1000p VTUNE-Connected directly to GND
TXEN DCS_PCS_TX HB_RF_OUT1 VTUNE_GPS
26 2 58
1000p C620 VBATT MODE C617 3nH HB_RF_OUT2
C618 1000p1000p 3 59 11
RSVD WCDMA_2100_TX_OUT HB_RF_OUT3 PRX_QP RX_QP
C619 25 12
DCS
C622
VAPC PRX_QN RX_QM B
2.7p
4 5 4 C621 30 14
RX4 C623 WPRXLBP PRX_IP RX_IP
23 5 G2 O2 L608 L609 100p 31 13
GSM_IN RX3 IN 1.5p WPRXLBN PRX_IN RX_IM
6 1 G1 O1 12nH 10nH C624 32
RX2 WPRXHBP
21 7 SAFEB12G843FA0F00 22p 33 15
DCS_PCS_IN RX1 FL602 WPRXHBN DRX_QP GPS_QP
10 L610 16
WCDMA1 DRX_QN GPS_QN
24 3.3nH C626 41 17
VBATT GND13 WDRXLB DRX_IP GPS_IP
C625 22 9 L611 3.3nH 100p 18
C629 GND12 GND1 DRX_IN GPS_IM
10u 20 11 C627 22p 40
51p GND11 GND2 WDRXHB1
19 12 C630 22p 39 19
0.1u
0.1u
0.1u
0.1u
0.1u
GND10 GND3 WDRXHB2 NC
22p
22p
22p
22p
22p
18 13
GND9 GND4
17 14 C631 50 67
GND8 GND5 GCELL_INP DAC_IREF DAC_REF
C632
C633
C634
C635
C636
C637
C638
C639
C640
C641
16 22p 51
GND7 GCELL_INN
15 29 3 VREG_SYNTH_2.7V
GND6 PGND VDDA1_1
48 4 R850 2.2
2.2K R601 EGSM_INP VDDA1_2 C642 C643
L612 1.2nH 49 6 R849 10
GSM_PA_RAMP EGSM_INN VDDA1_3 1000p 0.1u
10
VDDA1_4 C
46 22
C644 DCS_INP VDDA1_5
47 53
PCS
C645
68p DCS_INN VDDA1_6
2.2p
5 4
G2 O2 L613 L614 44 1 VREG_RF_SMPS_2.1V
IN GPCS_INP VDDA2_1
1 G1 O1 8.2nH 6.8nH 45 7
GPCS_INN VDDA2_2 C647
SAFEB12G963FA0F00 8
FL603 VDDA2_3 0.1u
L615 L616 C646 42 21 R602 5.1
GPS_IN GPS_IN VDDA2_4
3.3nH 3.3nH 33p C648 52 25 R603 5.1
PWR_DET R604 PDET_IN VDDA2_5
L618 1.2nH 33p 68 27
TX_RBIAS VDDA2_6
1.5p 12K 1%
WCDMA2100 L617 C649
22p
38
36
WPRXSE1 VDDA2_7
37
43
WPRXSE2_OUT
WPRXSE1_OUT
RX_WCDMA_2100 WPRXSE2 VDDA2_8
54
ANTENNA SWITCH MODULE LOGIC
WB_MX_INM
VDDA2_9
WB_MX_INP
60
VDDA2_10 C650 C651
61
VDDA2_11 0.1u 10u
VDDM
PGND
62
TXEN BS1 BS2 VDDA2_12 D
100p
100p
100p
100p
100p
100p
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
4.7u
4.7u
0.1u
0.1u
VREG_RF_SMPS_2.1V
22p
22p
22p
GSM 900 TX LOW LOW HIGH
69
34
35
28
29
23
L623
GSM 1800/GSM 1900 TX LOW HIGH HIGH C694 C695
C652
C653
C654
C655
C656
C657
C658
C659
C660
C661
C662
C663
C665
C667
C668
C669
C666
C664
C670
C671
C672
2nH
R614
0.1u 100p
1K
GSM 900 RX HIGH HIGH LOW R605 C673
GSM_TX 22p
GSM 1800 RX HIGH HIGH HIGH 91 0603
R606 12.0 dB R607
GSM 1900 RX HIGH LOW HIGH 82 82 VREG_MSMP_2.6V
Atten.
WCDMA LOW HIGH LOW WCDMA_MIX_IN_P 1000p 22p 0.01u
C674 C675 C676
WCDMA_MIX_IN_M
WLNA_OUT
R608
DCS_PCS_TX
47
R609 R610
130 6.8 dB 130
Atten.
GSM
TCXO F
WCDMA
C677 1000p DSA321SCE-19.2M X601
C684 GPS LNA CHAIN TCXO_PM

NC3 NC2
3.3p 7 6
NC4 NC1
8 5
C679 1000p
RTR6275_TCXO OUTPUT GND
3 2
R612 100ohm
4.7nH
ANT605 C680
L619
6.8nH
FL604 VREG_TCXO_2.85V
ACS1575JCDXX C681 VC C VCONT TRK_LO_ADJ
100p B9416 4 1
3.3nH 1 4 R611
GND2 FEED OUT IN VREG_SYNTH_2.7V C687 C688 C689
L621 G1 G2 G3
GND1 DUMMY 12ohm 0.1u 1000p 10n
L622
2 3 5
1nH
C685 C686 0603 0603
1
10p 0.1uF
RF_IN
6.8K
2 5
C690 GPS_LNA_EN S_D VDD C
R613 3 4
DNI GND FIL_OUT
C692
33p
U603 ALM-1412 GPS_IN
L620
4
3
4.7nH
PGND
ANT
ACMD-7602
FL605
RX
TX
WCDMA LNA CIRCUIT

1
2
C693 L624
5.6nH 3nH WCDMA_MIX_IN_M D

EFCH2140TDE1
FL606
Rx Tx
1.2nH
C698
2 3
C697 2.2p C699
G1 O1
L626 1.2nH VBATT WL NA _OUT IN 0.75p
L625 2.7p 1 G2 O2
RX_WCDMA_2100
5 4
C696
2.2u
LDC151G9520Q-359 U802
L628 L630 L631

C857 1.8p
1.5nH
1
1p L629
5.6nH 3nH
WCDMA_MIX_IN_P
C700 C701
OUT
IN
1000p 100p
COU
TER
ACPM-7381 U604
E
4
11
PGND
10 1
VCC2 VCC1
9 2
51 GND3 RFIN
8 3
12p
C702
R839
FL607
51
EFC4H19550TDF1 L633
R840 7 4
GND2 VMODE0 PA_R0 O1 G3
6 5 1
R837
R838
GND1 VEN IN WCDMA_2100_TX_OUT

120
120
L632 G2 G1
8.2p
7.8 dB 8.2nH 3 2
C861
Atten. 100p
C704
100p
PA_ON
1 2 3 4 5 6 7 8 9
7. CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VBATT
VREG_MSMP_2.6V +VPWR
A A
SIA411DJ
Q800
D1 D2 D3 D4 D5
S1 S2
VBATT ICHARGEOUT
80.6K
R800
ICVS0505500FR
CN800
PSD05-LF
G
INSTPAR
1
0.01u
4 2 R801
VBAT_TEMP
3
750
33u
ICVS0505500FR
C801
VA800
D800
C800
BATT_FET_N
VA801
B
MP MEMORY B
(1G NAND : 512M SDRAM)
W14
W13
W12
W11
U14
N13
N12
Y14
Y13
Y12
V14
V13
N11
T13
Y11
N10
W4
W3
W2
W1
U3
U1
R9
R7
R2
N9
N6
N5
N4
N3
Y4
Y3
Y2
Y1
V2
V1
P8
P7
T7
T3
T2
VDD_MSM +VPWR
NC89
NC88
NC87
NC86
NC85
NC84
SDRAM_ADDR(0:12) SDRAM_DATA(0:31)
SMPS Circuit 0 R802
NC124
NC123
NC122
NC121
NC120
NC109
NC108
NC107
NC106
NC105
NC104
NC103
NC102
NC101
NC100
NC99
NC98
NC97
NC96
NC95
NC94
NC93
NC92
NC91
NC90
NC119
NC118
NC117
NC116
NC115
NC114
NC113
NC112
NC110
NC111
SDRAM_ADDR(0) C3 U4 SDRAM_DATA(0)
C A0 DQ0 C
SDRAM_ADDR(1) D3 T4 SDRAM_DATA(1)
A1 DQ1
SDRAM_ADDR(2) E3 T5 SDRAM_DATA(2)
A2 D Q2
SDRAM_ADDR(3) E2 V5 SDRAM_DATA(3)
A3 D Q3
SDRAM_ADDR(4) D12 U5 SDRAM_DATA(4)
VREG_MSMC A4 DQ4
SDRAM_ADDR(5) C12 T6 SDRAM_DATA(5)
L800 4.7uH A5 DQ5
SDRAM_ADDR(6) D1 1 V6 SDRAM_DATA(6)
VREG_MSMC_1.2V VSW_MSMC A6 D Q6
A7 DQ7
C804 SDRAM_ADDR(8) D1 0 T9 SDRAM_DATA(8)
A8 DQ8
C803 SDRAM_ADDR(9) C1 0 T10 SDRAM_DATA(9)
C802 A9 D Q9
SDRAM_ADDR(10) E4 V10 SDRAM_DATA(10)
100p 4.7u A10 DQ10
33p SDRAM_ADDR(11) D9 T11 SDRAM_DATA(11)
A11 DQ11
A12 DQ12
V11 SDRAM_DATA(13)
DQ13
L6 T12 SDRAM_DATA(14)
RESOUT_EBI2_N _ WP D Q14
VREG_MSMP_2.6V K6 U12 SDRAM_DATA(15)
EBI2_WE_N _WEN DQ15
D5 P3 SDRAM_DATA(16)
100K
D SDRAM_RAS_N _RAS DQ16 D
D6 R3 SDRAM_DATA(17)
VREG_S2 SDRAM_WE_N _WED DQ17
E6 P4 SDRAM_DATA(18)
SDRAM_CAS_N _CAS D Q18
R804
R805
C8 R4 SDRAM_DATA(19)
R803
VREG_RF_SMPS_2.1V 4.7uH VSW_S2 SDRAM_CLK CLK DQ19
L801 E5 P5 SDRAM_DATA(20)
SDRAM_CS_N(0) _CS DQ20
M3 R5 SDRAM_DATA(21)
NAND_ALE ALE DQ21
100K
M4 P6 SDRAM_DATA(22)
10K
C805 C806 NAND_CLE CLE DQ22
100p M9 R6 SDRAM_DATA(23)
10u NAND_CS_N _CE DQ23
1608 EBI2_OE_N _RE DQ24
NAND_READY RY__BY D Q25
SDRAM_CLK_EN CKE DQ26
VREG_MSME_1.8V C4 P11 SDRAM_DATA(27)
SDRAM_ADDR(13) BA0 DQ27
SDRAM_ADDR(14) BA1 DQ28
P12 SDRAM_DATA(29)
D Q29
C7 R12 SDRAM_DATA(30)
VREG_S3 VCCD1 DQ30
L802 4.7uH VCCD2 DQ31
D1 3
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
E VREG_SYNTH_2.7V VSW_S3 VCCD3 E
V3 U8
VCCD4 DQM0 SDRAM_DQM(0)
V8 T8
VCCD5 U800 DQM1 SDRAM_DQM(1)
C807
C808
C809
C810
C812
C813
C814
C811
V12 V7
C815 C816 VCCD6 DQM2 SDRAM_DQM(2)
VREG_MSMP_2.6V U9
100p 10u V4
TY9000A800KOGG40 DQ M 3 SDRAM_DQM(3)
1608 VCCQD1 EBI2_DATA(0:15)
V9 M11 EBI2_DATA(0)
VCCQD2 IO1
K12 M13 EBI2_DATA(1)
VCCN2 IO2
L10 EBI2_DATA(2)
IO3
C6 L12
0.1u
EBI2_DATA(3)
10n
VSS1 IO4
F7 J9 EBI2_DATA(4)
VSS2 IO5
G2 H12 EBI2_DATA(5)
VSS3 IO6
G1 3 H10
C817
C818
EBI2_DATA(6)
VSS4 IO7
L13 G12 EBI2_DATA(7)
VSS5 IO8
P2 M12 EBI2_DATA(8)
VSS6 IO9
VCOIN P13 L9 EBI2_DATA(9)
VSS7 IO10
R8 L11 EBI2_DATA(10)
F VSS8 IO 1 1 F
U2 K9 EBI2_DATA(11)
MOT_PWR- VSS9 IO12
U6 H13 EBI2_DATA(12)
VSS10 IO13
U1 0 H11 EBI2_DATA(13)
+5V_PWR VSS11 IO14
U1 3 H9 EBI2_DATA(14)
KPD_MAIN_DRV_N VSS12 IO 1 5
G11 EBI2_DATA(15)
R806
IO16
1K
J11
PM6658 NC62
C819 2.2u U801 J13 A1
KPD_FOLDER_DRV_N NC63 NC 1
B5 K1 A2
R807 51K SPKR_IN_M NC64 NC 2
C1 B6 OPT1 OPEN OPEN K2 A3
VCHG SPKR_IN_P NC65 NC3
TP800 C2 A5 K3 A4
C821
1u C820 CHG_CTL_N SPKR_OUT_M OPT2 VDD GND NC66 NC4

D1 A6 D7 A11
33p
ICHARGEOUT ISNS_M SPKR_OUT_P NC67 N C5

TP801 D2 K1 MSMC 1 .2 V 1.2V J1 2 A12
ISNS_P HSET_BIAS (Default) NC68 NC6
VBATT E1 VIB_DRV_N L3 K4 A13
VBAT NC69 N C7
E2 L2 VREG_S3 K5 A 14
BATT_FET_N BAT_FET_N MPP3 (Default) OFF ON NC70 NC8
Q801 F2 L1 K10 B1
USB_OVP_G MPP4 NC71 NC9
D2 D1
SI1072X J10 K11 B2

C VCOIN NC72 NC10 C
H1 D4 K13 B3
USB_VBUS OPT_1 NC73 NC11
H8 K14 B4
S
C822
G
OPT_2 NC74 NC12
10K R808
USB_VBUS R809
D4 D3
F1 L1 B11
VSW_5V NC75 NC13
G1 K2 R810 1K L2 B12
VREG_5V MPP7 REMOTE_PWR_ON 200K NC76 N C14
K5 KPD_PWR_N L4 L3 B 13
4.7u
USB_VBUS_IN VSW_MSMC VSW_MSMC KEY_ON_SW_N NC77 NC15

K4 G10 RB521S-30 D801 L4 B14
VREG_MSMC VREG_MSMC PON_RESET_N MSM_RESIN_N NC78 NC16
K7 F10 L5 C1
VSW_S2 VSW_S2 PS_HOLD PS_HOLD NC79 NC17
L8 L14 C2
VREG_S2 VREG_S2 NC80 NC 18
K6 E8 R811 DNI M5 C5
VSW_S3 VSW_S3 SBST VREG_MSMP_2.6V NC81 N C19
L6 F8 R812 51K M6 C1 3
VREG_S3 VREG_S3 SBCK R813 NC82 NC20
G8 TP803 N2 C14
SBDT_SSBI PM_SBDT RTC_CONT NC83 NC21
A3 C10 TP804
NC61
NC60
NC59
NC58
NC57
NC56
NC55
NC54
NC53
NC52
NC51
NC50
NC49
NC48
NC47
NC46
NC45
NC44
NC43
NC42
NC41
NC40
NC39
NC38
NC37
NC36
NC35
NC34
NC33
NC32
NC31
NC30
NC29
NC28
NC27
NC26
NC25
NC24
NC23
NC22
AP_VDD_CAM_IO_2.7V VREG_GP1 MSM_INT_N PM_INT_N 1K
A2
AP_VDD_CAM_1.8V VREG_GP2
B1 H2
AP_VDD_CAM_AVDD_2.7V VREG_GP3 USB_ID
D14
E10
J10
J6
J5
J4
J3
J2
H6
H5
H4
H3
H2
G10
G9
G8
G7
G6
G5
G4
G3
F13
F12
F10
F9
F8
F6
F5
F4
F3
F2
E13
E12
E11
F11
D1
E9
E8
E7
E1
L9 J2
VREG_MMC USB_D_P MSM_USB_D+
G11 J1
D VREG_MSMA_2.6V VREG_MSMA USB_D_M MSM_USB_D- D
K8 F4
VREG_MSME_1.8V VREG_MSME USB_OE_N USB_OE_N
J11 G4
VREG_MSMP_2.6V VREG_MSMP USB_DAT USB_DAT
A9 H4
R814 0 VREG_RFRX1 USB_SE0 USB_SE0
A10
R815
VREG_RFRX2
A8 D5
0
VREG_RFTX MPP11 MSM_USIM_DATA

B8 H5
VREG_RFUBM MPP12 USIM_P_DATA
L10 D6
VREG_USIM_2.85V VREG_RUIM MPP9 MSM_USIM_CLK
A1 H6
VREG_TCXO_2.85V VREG_TCXO MPP10 USIM_P_CLK
C823
C830
C825
C831
G2 D7
C827
C828
C829
C824
C826 1u VREG_USB MPP5 MSM_USIM_RST_N

B11 H7
VREG_WLAN MPP6 USIM_P_RST_N
1u
2.2u
2.2u
2.2u
2.2u
2.2u
4.7u
4.7u
C832 0.1u C11 A4

REF_BYP VDD_SPKR
D10 A11
121K 1% R816 E10 REF_ISET VDD_WLAN
B2
REF_GND VDD_MAIN +VPWR
B3
VDD_GP
E11 B9
E TCXO_PM TCXO_IN VDD_RF E
D11 H11
DNC VDD_MSM VDD_MSM
D8 K10
TCXO_EN TCXO_EN_1 VDD_RUIM
51 R817 H10 L5
BUFF_TCXO TCXO_OUT_1 VDD_MSMC
E4 L7
BUFF_TCXO_FF TCXO_EN_2 VDD_S23
51 R818 B10
TCXO_OUT_2
F11 E5
TCXO_OUT_RF GND1
L11 E6
XTAL_IN GND2
C833
C834
C835
C836
C837
C838
C839
C840
K11 E7
XTAL_OUT GND3
X800 K9 F5
SLEEP_CLK GND4
CM315_12_5PF 2 1 TP808 K3 F6
AMUX_OUT GND5
4.7u
4.7u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
A7 F7
32.768KHz MPP1 GND6
B7 G5
MPP2 GND7
C841 C842 B4 G6
MPP8 GND8
G7
18p 18p GND9
F
AMUX_OUT
GSM_PA_DAC_REF
SLEEP_CLK
USB_VBUS_IN
R820 DNI
R821 DNI
1 2 3 4 5 6 7 8 9
7. CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A A
FPCB TO K EY PCB
END (POWER_ON)
1 6 DOWN SW100
SW101 SW102 SW103 CN100
1 40
K EY_ON_SW_N MOT_PWR-_PA D SPK _L +
2 39
K EY_ROW(0) ML ED1 SPK _L -
2 7 B A CK 3 38
SW104 SW105 SW106 ML ED2
EVLC14S02050
EVLC14S02050
ZD100 EVL C14S02050 4 37
ML ED3 SL ED1
K EY_ROW(1) 5 36 B
3 8 UP ML ED4 SL ED2 A P_VDD_L CD_2.7V
SW107 SW108 SW109 6 35
ML ED5
7 34 FB 100
VA100
VA101
K EY_ROW(2) L ED_A NODE
4 9 OK 8 33
SW110 SW111 SW112
9 32
A P_VDD_L CD_2.7V I2CSCL 0 KEY_ROW(0)
KEY_ROW(3) 10 31
5 0 SEND I2CSDA 0 KEY_ROW(1)
SW113 SW114 SW115 11 30
R100 100K
KEY_ROW(2)
12 29
KEY_ROW(4) WL ED_n RST KEY_ROW(3)
* # SHOT 13 28 C
SW116 SW117 SW118 K PD_FOL DER_DRV_N KEY_ROW(4)
14 27
K EY_ON_SW_N KEY_ROW(5)
KEY_ROW(5) 15 26
A P_VDD_IO_2.7V MOT_PWR- KEY_COL(6)
16 25
R101 10K
KEY_COL(7)
A P_+VPWR
KEY_COL(6) 17 24
KEY_COL(7)
18 23
AP_VDD_CAM_2.8V
EVLC14S02050
EVLC14S02050
EVLC14S02050
EVLC14S02050
EVLC14S02050
EVLC14S02050
EVLC14S02050
EVLC14S02050
FB 101 19 22
AP_VDD_CAM_1.8V
FB 102 20 21
A XK 740145
VA103
VA105
VA107
VA102
VA104
VA106
VA108
VA109
A P_+VPWR
F
A P_+VPWR
L EWWS44-E
L D100 R103
100o h m
L EWWS44-E
L D101 R104
MOT_PWR-_PA D MOT_PWR- K PD_FOL DER_DRV_N
L 100 56n H 100o h m
D100
VA 110
EVL 14S02200
RB 521S-30
A P_+VPWR
C100
C101
C102
K EYPA D L ED
1u
1u
1u
Vi b r at o r
D6
C6
C5
C4
B5
A4
A5
C1N
C1P
C2N
C2P
C3N
C3P
CPGND
B6 B4
VB A TCP VOUT L ED_A NODE
A P_VDD_IO_2.7V F3
VB A T1
E3 A3
VB A T2 L ED1 ML ED1
B3
L ED 2 ML ED2 C103
A2
L ED3 ML ED3 4.7u D
B1
L ED4 ML ED4
B2 A P_+VPWR
WGND
U100 L ED5
C1
ML ED5
E6 D1
VIO L ED6 SL ED1
B D6085GUL L ED7
D2
SL ED2
C2
C105 1u FL GND
D3
10u C104 WL ED_n RST RESETB
D5 F5
I2CSDA 0 SDA VB A TL DO1
I2CSCL 0 SCL VB A TL DO2
AP_VDD_CAM_1.8V
EVLC14S02050
EVLC14S02050
EVLC14S02050
E5 AP_VDD_CAM_2.8V
L DO1O 1u
E1 TP100
L DO2O C106
E4
L DO3O
F4 E2
A GND L DO4O
T1
T2
T3
T4
E
F6
F1
A1
A6
VA11 2
VA113
VA111
1u 1u 1u
C107 C108 C109
L CD_B ac k l i g h t d r i v er
1 2 3 4 5 6 7 8 9
7. CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A A
VMMC_3.1V
2
4
6
8
10K
10K
A P_VDD_B T_2.7V
RA100
R100
1
3
5
7
B
U101 STL C2500C

S100 SCHA 1B 0102 D3
X100 CSC3M192000EEVRS00 B T_RESETN RESET_N
DA T2_RSV 4 3 D6
SD_DAT(2) VDD OUT REF_CL K _IN
R101 10 CD_DA T3_CS 1 2 G3
SD_DAT(3) TRI_OPEN GND CL K 32K L P_CL K
R102 10 CMD_DI C4
SD_CMD 19.2MHz CL K _REQ_OUT_1
R103 10 VDD C5
C100 B T_WA K EUP
SD_CLK CL K _SCL K 1u
R104 10 VSS F5 F6
UTXD0 UA RT_RXD UA RT_TXD URXD0
DA T0_DO G4 F4
SD_DAT(0) URTS0N UA RT_CTS UA RT_RTS UCTS0N
R105 10 DA T1_RSV
SD_DAT(1)
R106 10 COMMON D1
PCMCL K PCM_CL K
DETECT C2
SD_INT PCMSYNC PCM_SYNC
DUMMY1 D2
PCMDA TA IN PCM_A
DUMMY2 E1
PCMDA TA OUT PCM_B C
B3
GPIO_16
C3
GPIO_8
B1 B2
RCLAMP0504P.TCT
RCLAMP0504P.TCT
GPIO_9 GPIO_11
C1
R107
3
C101
C102
C103
C104
C105
GPIO_10
IO2
NC
IO1
D100
D101
IO1
NC
IO2
D5 A2
C106 GPIO_0 VSS_RF1
P_GND
P_GND
5V_NC
5V_NC
E6 A5
1u CL K _REQ_IN_1 VSS_RF2
IO3
IO4
IO4
IO3
G6
DNI
CL K _REQ_IN_2
DNI
DNI
DNI
DNI
DNI
F7
4
HOST_WA K EUP DEA 212450B T-7043C1

FL 100 A NT100
E2 A3 C123 10p
A P_VDD_B T_2.7V CONFIG_1 RFP NC1
F2 A4 5 1
CONFIG_3 RFN B P1 U_B P FEED NC2
F1
CONFIG_2
4 2
B P2 B P_ D C
G7 L 101
G2
G1
A P_VDD_IO_1.8V CL K _REQ_OUT2 C124 D
DNI 1.5p
A6
6
3
TOUT_IP_QN
B5 E3
TOUT_IN_QP VSS_DIG1
E4
VSS_DIG2
T-FL A SH SOCK ET
R110
G2
0
VDD_D
B L UETOOTH MODUL E A P_VDD_IO_2.7V A P_VDD_B T_2.7V

G5
VDD_IO_A
F3
A P_+VPWR VDD_IO_B
E7
R109 VDD_CL D
B4
VSS_A NA 1
R1114D271D U100 A7 B6
0 VDD_HV_A VSS_A NA 2
6 1 C6
PON CE_OR_NC VD D VSS_A NA 3
G1
VDD_HV_D E
5 2
GND2 GND1
4 3 B7
NC VOUT VDD_DSM
C7
VDD_N
DNI D7
VDD_CL A F_PRG
E5
A1
C108 C107 VDD_RF
220n
220n
220n
220n
DNI 33u
220n
1u
1u
C115 1u
1u
1u
C109
C113
C110
C112
C114
C116
C117
C118
C111
VCOIN VMMC_3.1V
A P_VDD_IO_1.8V A P_+VPWR
SUB B 2B Co n . A P_VDD_IO_2.7V
1
CN100
34 B L UETOOTH MODUL E
F
2 33
3 32
4 31
PON
5 30
CL K 32K SD_INT
6 29
7 28
UCTS0N
8 27
URXD0
9 26 VCOIN
UTXD0 SD_DAT(1) C
10 25
URTS0N SD_DAT(0)
11 24
12 23
PCMDA TA OUT SD_CLK B A T100
13 22
PCMDA TA IN
PCMCL K
14 21
SD_CMD B ac k -u p b at t er y
15 20
PCMSYNC SD_DAT(3)
16 19
B T_RESETN SD_DAT(2)
17 18
D
C119 C120
1u 1u
1 2 3 4 5 6 7 8 9
7. CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A A
AP_VDD_IO_2.7V
A P_+VPWR
MA IN-FOL DER CON-HEA DER

CN101
G2 G1
70 1
L CD_NRESET
69 2
MOT_PWR- L CD_VS
68 3
K EY_ON_SW_N L CD_DA TA _O_6 B
67 4
K PD_FOL DER_DRV_N L CD_DA TA _O_4
66 5
WL ED_n RST L CD_DA TA _O_2
65 6
L CD_DA TA _O_0
64 7
MCL K _27MHZ_CA M L CD_DA TA _O_8
63 8
L CD_DA TA _O_10
62 9
CCIRICL K L CD_DA TA _O_12
61 10
CCIRIHS L CD_DA TA _O_14 AP_VDD_CAM_1.8V
60 11 AP_VDD_CAM_2.8V
CCIRIVS L CD_DA TA _O_15
59 12
CCIRID(7)
CCIRID(6)
58 13
L CD_DA TA _O_13
L CD_DA TA _O_11
VGA_CAMERA
57 14
CCIRID(5) L CD_DA TA _O_9
56 15
CCIRID(4) L CD_DA TA _O_7 CN100
55 16
54 17
53 18 1 20
CCIRID(1) L CD_DA TA _O_1 VGA _STA NDB Y
52 19 FL 100 EVRC18S03Q015050R 2 19
CCIRID(0) SDIS_CSN_O C
51 20 1 9 3 18
VGA _STA NDB Y DIS_WEN_O MCL K _27MHZ_CA M INOUT_A 1 INOUT_B 1 VGA _RSTN
50 21 2 8 4 17
VGA _RSTN MDIS_CSN_O CCIRICL K INOUT_A 2 INOUT_B 2 I2CSCL 0_CA M
49 22 3 7 5 16
I2CSDA 0_CA M DIS_RS_O CCIRID(0) INOUT_A 3 INOUT_B 3 I2CSDA 0_CA M
48 23 4 6 FL 101 EVRC18S03Q015050R
6 15 FL 102 EVRC18S03Q015050R
I2CSCL 0_CA M CCIRID(1) INOUT_A 4 INOUT_B 4
47 24 1 9 7 14 1 9
CCIRID(2) INOUT_A 1 INOUT_B 1 INOUT_A 1 INOUT_B 1 CCIRIHS
G1
G2
46 25 2 8 8 13 2 8
I2CSCL 0 CCIRID(3) INOUT_A 2 INOUT_B 2 INOUT_A 2 INOUT_B 2 CCIRIVS
45 26 9 12
5
10
3 7 3 7
I2CSDA 0 CCIRID(4) INOUT_A 3 INOUT_B 3 INOUT_A 3 INOUT_B 3 CCIRID(7)
44 27 4 6 10 11 4 6
43 28
G1
G2
G1
G2
42 29
41 30 A XK 720147
5
10
5
10
KEY_ROW(2)
40 31
KEY_ROW(3) SPK _R+
39 32
KEY_ROW(4) SPK _R-
38 33
KEY_ROW(5)
37 34
KEY_COL(6) SPK _L -
36 35
KEY_COL(7) SPK _L + D
G4 G3
A XT670124
L CD_CONNECTOR
CN103 A P_+VPWR
1
51 52
50
FPCB TO K EY PCB F
R? 22 2 49
RECEIVER+ SPK _R+
R? 22 3 48
RECEIVER- SPK _R-
4 47 CN102
5 46 TP100 1 40 OUT100
PUL L _DOWN MOT_PWR-_PA D SPK _L + A P_VDD_L CD_2.7V
6 45 2 39
L CD_DA TA _O_1 L CD_DA TA _O_0 ML ED 1 SPK _L -
7 44 3 38
L CD_DA TA _O_3 L CD_DA TA _O_2 ML ED2
8 43 4 37 OUT101
L CD_DA TA _O_5 L CD_DA TA _O_4 ML ED3 SL ED1 MOT_PWR-_PA D
9 42 5 36
L CD_DA TA _O_7 L CD_DA TA _O_6 ML ED4 SL ED2
10 41 6 35
L CD_DA TA _O_9 L CD_DA TA _O_8 ML ED5
11 40 7 34
L CD_DA TA _O_11 L CD_DA TA _O_10 L ED_A NODE
12 39 8 33
13 38 9 32
L CD_DA TA _O_15 L CD_DA TA _O_14 I2CSCL 0 KEY_ROW(0)
14 37 10 31
PUL L _UP DIS_WEN_O I2CSDA 0 KEY_ROW(1)
15 36 11 30
SDIS_CSN_O DIS_RS_O PUL L _UP KEY_ROW(2)
16 35 12 29
MDIS_CSN_O TP101 WL ED_n RST KEY_ROW(3) C
17 34 A P_VDD_L CD_2.7V 13 28
L CD_VS L CD_NRESET K PD_FOL DER_DRV_N KEY_ROW(4)
18 33 A P_VDD_IO_2.7V 14 27
K EY_ON_SW_N KEY_ROW(5)
19 32 15 26 A P_+VPWR
L ED_A NODE MOT_PWR- KEY_COL(6)
20 31 16 25
ML ED5 PUL L _DOWN KEY_COL(7)
21 30 17 24 OUT102
ML ED4 SPK _L +
22 29 18 23
ML ED3 L ED_A NODE
23 28 AP_VDD_CAM_2.8V 19 22
ML ED2 SL ED2
24 27 20 21 OUT103
ML ED1 SL ED1 SPK _L -
25 26
53 54
AP_VDD_CAM_1.8V A XK 840145
A XK 8L 50125
1 2 3 4 5 6 7 8 9
7. CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10
A A
B B
VOL UME SIDE K EY

VOL _UP
K B 100
CN100
1
K EY_ROW(6)
2
K EY_ROW(6) VOL _UP
3
K EY_COL (5)
VOL _DOWN
TP100 TP101 4 VOL _DOWN K B 101
K EY_ROW(7)
K EY_ROW(7)
C C
K EY_COL (5)
D D
1 2 3 4 5
8. BGA IC PIN CHECK
8. BGA IC PIN CHECK
CPU : STn8810 (U100)
N/C : Do Not Connect
8. BGA IC PIN CHECK
CPU : STn8810 (U100)
8. BGA IC PIN CHECK
Audio Codec. : WM8753 (U201)
N C : Do Not Connect
8. BGA IC PIN CHECK
ST PMIC : STw4810 (U302)
8. BGA IC PIN CHECK
Key Coder IC : LM8333 (U400)
N/ : Do Not Connect
8. BGA IC PIN CHECK
Modem : MSM6280 (U501)
8. BGA IC PIN CHECK
MCP (Memory) : TY9000A800KOGG40 (U800)
8. BGA IC PIN CHECK
MSM PMIC : PM6658 (U801)
8. BGA IC PIN CHECK
BT : STLC2500C (U101, Sub)
9. PCB LAYOUT
U402 Folder Sensor

No detection about folder
open / close
9. PCB LAYOUT
CN200 SUB BtoB Conn

U603 LNA for GPS No BT
No Service(GPS) No Micro-SD
No RTC
FL604 GPS RX Sawfilter.

No Service(GPS) CN402 Camera Conn.
No 2M Camera
U801 Modem PMIC
No Power U302 ST CPU PMIC
No Booting No Power
No Service No Booting
No Display
U800 Memory
No Booting U400 Key Coder IC
No Key Recognization
U100 Application CPU STn8810
No Booting CN400 Main-Folder BtoB Conn.
No Display No Display
No Sound
No Vibrator
U501 MSM 6280 Modem BB Chip
No VGA Camera
No Booting
No Call Voice
No Service
U209 Audio Sub System
U602 RTR6285 Transciver.
No Speaker Sound
GSM, DCS,PCS,WCDMA
No Ear Jack Sound
RX Sensitivity.
No Service.
U601 GSM Power amplifier &
Antenna switch module.
FL601(GSM),FL602(DCS),
GSM, DCS,PCS,WCDMA
FL603(PCS) RX Sawfilter.
RX Sensitivity.
RX Sensitivity.
TX Power.
No Service.
No Service.
FL606 WCDMA2100 RX Sawfilter.
U201 Audio Codec.
RX Sensitivity.
No Sound & Voice
No Service.
No Mic.
LGMC
FL605 WCDMA2100 Duplexer.
FL607 WCDMA2100 TX Sawfilter.
RX Sensitivity.
No Service.
TX Power.
No Service.
U604 WCDMA2100 Power amplifier.
TX power.
No Service.
9. PCB LAYOUT
BAT100 Back up Battery

RTC Reset
S100 Micro SD Socket

No Micro SD recognition
CN100 SUB BtoB Conn.

No BT
No Micro-SD
No RTC
9. PCB LAYOUT
U101 BT Chip Set

No BT
9. PCB LAYOUT
9. PCB LAYOUT
U100 LCD Back Light Driver

No LCD Back Light
No Camera
9. PCB LAYOUT
CN102 Key PCB BtoB Conn.

No Folder Key

No Folder Key

No Folder Key
CN100 VGA Camera Conn.

No VGA Camera
9. PCB LAYOUT
CN101 LCD Conn.

No Display
No Sound
No Vibrator
No VGA Camera
No Call Voice
CN103 LCD Conn.

No Display
No Right Speaker
No
10. CALIBRATION & RF AUTO TEST (HOT KIMCHI)
10.1 Usage of Hot-Kimchi
10.1.1 Calibration
Model Name
Calibration Only
* Procedure
1. Click SETTING in menu, and logic operation in sub-menu.
Choose “1” in LOGIC MODE (means calibration alone)
2.Select the model name which you want in list box
3.Click Start button to calibrate a phone
10.1.2 Basic Setting
* Contents
- Click SETTING in menu, and logic operation in sub-menu.
- You can select how to control AT comm, Testset, and Power supply in DLL Operating Mode.
- You can set UART Port and logic mode. (mode 1 : Calibration alone)
- You can set Result File’s name type. If you choose “TIME”, the saved files’ name is saved in a run
- time.
- You can run the multi mode (S/B1,S/B2 : You can use S/B1 for only one port.)
- You can set the path of HOTKIMCHI program.
10.1.3 Log of Calibration and Test
* Contents
- Running, Log window is created in center area. It displays logs of command, and measurements of
Calibration or Autotest.
- The result files are saved in the directory “~janghee\debug\Cal”, “~janghee\debug\Auto”, or
“~janghee\debug\CalAuto”.
11. TEST MODE
11. TEST MODE
A. About Test Mode

Test mode is designed to allow a service man/engineer to view and test the basic functions provided
by a handset.
B. Access Codes
The key sequence for switching the test mode on is 3845#*610#. Pressing END will switch back to
non-test mode operation.
11. TEST MODE
1. Version Info
1.1 AP/MP/HW Version
1.2 Factory Version
2. Device Test
2.1 Auto All Test
2M&VGA Camera Test (Picture & Video) → External Memory Test → Vibrator Test → Keypad LED
→ Ringtone Test
2.2 LCD
2.2.1 Auto Color Test
Red → Green → Blue → Black → White
To exit test, press the right arrow key.
2.2.2 Color Table Test : display the RGB table
2.3 LED
2.3.1 Backlight Test
This controls brightness of Backlight. When entering into the menu, the present backlight-value in
the phone is displayed. Use Left/Right key to adjust the level of brightness.
2.3.2 Keypad Light Test
This controls brightness of keypad light. When entering into the menu, the present keypad light-
value in the phone is displayed.
Use Left/Right key to adjust the level of brightness of keypad.
2.3.3 Blinking Test
Keypad & LCD Backlight blinking test.
2.4 Vibrator
This menu is to test the vibration mode.
2.5 Sound
2.5.1 Ringtone Test
This menu is test ring tone.
2.5.2 Audio Calibration
This menu is to test db value of each volume level.
2.5.3 Vocoder Calibration
This menu is to test db value of each frequency of codec.
2.5.4 Echo Cancelation
This menu is to test echo cancellation parameter of codec.
2.5.5 Sound Calibration
This menu is to test volume gain of codec.
2.5.6 Next Gen. Echo Cancel Test
This menu is to test extended echo cancellation parameter of codec.
11. TEST MODE
2.5.7 Loopback Test

This menu is to test the vibration mode.
2.5.8 AES/ACS Tunning
This menu is to test acoustic echo cancellation/suppression.
2.6 Camera
Camera application will be launched.
2.7 Keypad
This menu is to test all keys.
2.8 MP Msg Viewer
This menu is to display messages from MP.
2.9 RTC Test
This menu is to display current time.
2.10 GPS
This menu is to operate GPS module.
2.11 Band Selection
This menu is to select the operating band of phone.
3. ATS/MTC
This menu is used for verifying the system stability.
4. Factory Reset
This menu is to restore factory setting value.
5. Hidden Reset Off

When crash is occurred, phone will be changed to debug mode.
6. Factory AT CMD
This menu is used for only mass production.
7. XDL
This menu is used for flashing AP and MP SW image using micro SD during mass production.
12. EXPLODED VIEW & REPLACEMENT PART LIST
12.1 EXPLODED VIEW
44 88
43 87
38 44 42 86
37 42
41 85
46 40 84
50
39 83
28 29
30 49 38 82
25 48
21 37 81
19
51 36 80
18
10 39 35 79
9
34 78
7 41
34 33 77
6 17 32 76
2 5 22 24 31 75
1 47
12 40 43 45 30 74
11 29 73
31 33 28 72
27 71
23
32 35 36
27 26 70
26 25 69
20 24 68
23 67
16 22 66
15
14
88 21 65
13 78 79 84
83 20 64
8 77
19 63
76
3 4 74 18 62
17 61
68 73
67 16 60
64 15 59
62 14 58
57 59 87
58 13 57
61
80 12 56
55 11 55
65
10 54
54 66
86 9 53
70 85 8 52
60 69 81
7 51
6 50
53
52 75 5 49
71 72
4 48
3 47
2 46
63
1 45
56
3
10 16
4 11
13
5
17
14 12 16
15 3 17
2 15
8 14
13
16 6 12
11
7 10
9
8
11
7
2
10 6
9 5
4
3
17
2
1
1
4
12
13 11
14
15 5
9
2
10 8
8 10
5
11
2 3 11
1 10
9
8
7
6
11
5
4
3
3
2
1
12 9
6
7
14
2
10
6
13
5 11 8
14
13
12
4 11
10
9
12 8
2 7
3 6
9 5
1
4
3
2
1
14
8
13
2
3
3
3
2 2
1
12.2 Replacement Parts Note: This Chapter is used for reference, Part order
is ordered by SBOM standard on GCSC
<Mechanic component>
Location
Level Description Part Number Spec Color Remark
No.
1 IMT,FOLDER TIFF0015911 Black
Without
4 ADEY00 DATA KIT ADEY0015701 KT610 CD ASSY for H3G Italy
Color
5 MCHZ00 COMPACT DISK MCHZ0051001 COMPLEX, (empty), , , , , Black
Without
3 APLY00 PALLET ASSY APLY0002510 Nyx Hutchison STD1(9501/Angle/3901 Bag/2401 Bag)
Color
4 MPCY00 PALLET MPCY0009501 PALLET(G7100 for Orange UK_EUR) Black
Without
3 MBEE00 BOX,MASTER MBEE0058701 BOX, TW, , , , ,
Color
Without
3 MCJZ00 COVER MCJZ0053001 BOX, TW, , , , ,
Color
Without
3 MLAC00 LABEL,BARCODE MLAC0004541 PRINTING, (empty), , , , ,
Color
Without
3 MLAJ00 LABEL,MASTER BOX MLAJ0004401 LABEL,MASTER BOX(for C1300i NEW_CGR)
Color
Without
3 MPBA00 PAD,BOX MPBA0006601 COMPLEX, (empty), , , , ,
Color
2 APEY PHONE APEY0545702 Black
3 ACGG00 COVER ASSY,FOLDER ACGG0087601 Black
4 ABGF00 BUTTON ASSY,MAIN ABGF0002001 Black 55
4 ABGG00 BUTTON ASSY,SUB ABGG0001701 Black 3
COVER
4 ACGH00 ACGH0052101 Black
ASSY,FOLDER(LOWER)
Color
5 MBFF00 BRACKET,LCD MBFF0016901 CASTING, Zn Alloy, , , , , D, 25
Unfixed
5 MCJH00 COVER,FOLDER(LOWER) MCJH0042201 MOLD, PC LUPOY SC-2302, , , , , Black A, 37
5 MDAN00 DECO,SPEAKER MDAN0013801 PRESS, STS, , , , , Black C, 44
5 MDAN01 DECO,SPEAKER MDAN0013701 PRESS, STS, , , , , Black B, 45
5 MHFD00 HINGE,FOLDER MHFD0013801 COMPLEX, (empty), , , , , Metal Silver P, 38
5 MMAA00 MAGNET,SWITCH MMAA0000301 G, 30
5 MPBN00 PAD,SPEAKER MPBN0057401 COMPLEX, (empty), , , , , Black K, 29, 36
5 MPBT00 PAD,CAMERA MPBT0060001 COMPLEX, (empty), , , , , Black L, 33
5 MPBU00 PAD,CONNECTOR MPBU0031601 COMPLEX, (empty), , , , , Black M, 32
Color
5 MSGC00 STOPPER,FOLDER MSGC0002401 MOLD, Urethane Rubber S190A, , , , , F, 41
Unfixed
5 MTAA00 TAPE,DECO MTAA0162201 COMPLEX, (empty), , , , , Black H, 42
5 MTAA01 TAPE,DECO MTAA0162301 COMPLEX, (empty), , , , , Black I, 43
5 MTAF00 TAPE,MOTOR MTAF0019501 COMPLEX, (empty), , , , , Black O, 35
5 MTAJ00 TAPE,FLEXIBLE PCB MTAJ0007901 COMPLEX, (empty), , , , , Black N, 31
Location
No.
5 MTAJ01 TAPE,FLEXIBLE PCB MTAJ0008101 COMPLEX, (empty), , , , , Black E, 34
5 MTAK00 TAPE,CAMERA MTAK0012901 COMPLEX, (empty), , , , , Black Q, 40
5 MTAZ00 TAPE MTAZ0217001 COMPLEX, (empty), , , , , Black J, 28
COVER
4 ACGJ00 ACGJ0068901 Black
ASSY,FOLDER(UPPER)
5 MCJJ00 COVER,FOLDER(UPPER) MCJJ0051901 MOLD, PC LUPOY SC-1004A, , , , , Black *1, 8
5 MDAE00 DECO,FOLDER(UPPER) MDAE0042001 MOLD, PMMA HI835M, , , , , Black *3, 3
5 MFBB00 FILTER,RECEIVER MFBB0026901 COMPLEX, (empty), , , , , Black *7, 7
5 MPBM00 PAD,RECEIVER MPBM0023801 COMPLEX, (empty), , , , , Black *8, 9
5 MPBN00 PAD,SPEAKER MPBN0057101 COMPLEX, (empty), , , , , Black *9, 11
5 MPBN01 PAD,SPEAKER MPBN0058901 COMPLEX, (empty), , , , , Black *10, 10
5 MPBQ00 PAD,LCD(SUB) MPBQ0036601 COMPLEX, (empty), , , , , Black *5, 5
5 MPBT00 PAD,CAMERA MPBT0059701 COMPLEX, (empty), , , , , Black *11, 14
5 MTAB00 TAPE,PROTECTION MTAB0240501 COMPLEX, (empty), , , , , Black *4
5 MTAE00 TAPE,WINDOW(SUB) MTAE0035601 COMPLEX, (empty), , , , , Black *6 ,6
5 MWAF00 WINDOW,LCD(SUB) MWAF0040001 MOLD, PMMA HI835M, , , , , Black *2, 2
4 ACGK00 COVER ASSY,FRONT ACGK0105501 Black
Without
5 MBJL00 BUTTON,SIDE MBJL0051701 COMPLEX, (empty), , , , , <2>, 53
Color
Color
5 MCJK00 COVER,FRONT MCJK0083301 MOLD, PC LUPOY SC-1004A, , , , , <1>, 54
Unfixed
5 MTAB00 TAPE,PROTECTION MTAB0241401 COMPLEX, (empty), , , , , Black <3>, 52
4 AWAB00 WINDOW ASSY,LCD AWAB0031201 Black 46
4 GMEY00 SCREW MACHINE,BIND GMEY0010601 1.4 mm,2.5 mm,MSWR3(BK) ,N ,+ ,NYLOK Black 48
1.4 mm,1.5 mm,SWCH18A ,N ,+ ,- , ,; ,CH ,+ ,3.5 ,0.3

4 GMZZ01 SCREW MACHINE GMZZ0024001 Black 12
,NYLON ,BLACK ,[empty] ,[empty]
Color
4 MBIB00 BUSHING,HINGE MBIB0006401 CASTING, Zn Alloy, , , , , 39
Unfixed
Color
4 MCCH01 CAP,SCREW MCCH0122301 MOLD, Silicone Rubber KE941-U, , , , , 49
Unfixed
4 MCCH02 CAP,SCREW MCCH0131901 PRESS, STS, , , , , Black 50
4 MCCH03 CAP,SCREW MCCH0132001 PRESS, STS, , , , , Black 51
4 MIDZ00 INSULATOR MIDZ0176701 COMPLEX, (empty), , , , , Black
4 MIDZ01 INSULATOR MIDZ0176801 COMPLEX, (empty), , , , , Black
4 MPBJ00 PAD,MOTOR MPBJ0056101 COMPLEX, (empty), , , , , Black 23
4 MPBN00 PAD,SPEAKER MPBN0059501 COMPLEX, (empty), , , , , Black 26
4 MTAB00 TAPE,PROTECTION MTAB0248801 COMPLEX, (empty), , , , , Black 1
4 MTAB01 TAPE,PROTECTION MTAB0249001 COMPLEX, (empty), , , , , Black
Color
4 MWAE00 WINDOW,CAMERA MWAE0032101 CUTTING, PMMA MR 200, , , , , 47
Unfixed
Location
No.
6 ADCA00 DOME ASSY,METAL ADCA0075601 Black 13
6 MGAZ00 GASKET MGAZ0062601 COMPLEX, (empty), , , , , Black 17
6 MIDZ00 INSULATOR MIDZ0173201 COMPLEX, (empty), , , , , Black 16
3 ACGM00 COVER ASSY,REAR ACGM0106801 Black
Color
4 MCCE00 CAP,RECEPTACLE MCCE0041901 COMPLEX, (empty), , , , , #5, 76
Unfixed
Color
4 MCCG00 CAP,MULTIMEDIA CARD MCCG0010801 COMPLEX, (empty), , , , , #4, 80
Unfixed
Color
4 MCJN00 COVER,REAR MCJN0080301 MOLD, PC LUPOY SC-1004A, , , , , #1, 75
Unfixed
4 MGAD00 GASKET,SHIELD FORM MGAD0167201 COMPLEX, (empty), , , , , Black #14, 69
Color
4 MLEA00 LOCKER,BATTERY MLEA0044301 MOLD, PC LUPOY SC-1004A, , , , , #2, 81
Unfixed
4 MPBH00 PAD,MIKE MPBH0039001 COMPLEX, (empty), , , , , Black #13, 71
4 MPBT00 PAD,CAMERA MPBT0060101 COMPLEX, (empty), , , , , Black #9, 74
4 MPBU00 PAD,CONNECTOR MPBU0031701 COMPLEX, (empty), , , , , Black #12, 73
Color
4 MPFZ00 PLATE MPFZ0031601 PRESS, STS, 0.15, , , , #7, 70-
Unfixed
4 MSDC00 SPRING,LOCKER MSDC0009201 Black #3
4 MTAB00 TAPE,PROTECTION MTAB0241501 COMPLEX, (empty), , , , , Black #10, 79
4 MTAD00 TAPE,WINDOW MTAD0089601 COMPLEX, (empty), , , , , Black #11, 77
Color
4 MWAE00 WINDOW,CAMERA MWAE0032201 CUTTING, PMMA MR 200, , , , , #6, 78
Unfixed
Without
3 GMEY00 SCREW MACHINE,BIND GMEY0011201 1.4 mm,3 mm,MSWR3(BK) ,N ,+ ,NYLOK 82
Color
Without
3 MCCH00 CAP,SCREW MCCH0122401 COMPLEX, (empty), , , , , 83
Color
Without
Color
Without
Color
Without
Color
Without
Color
3 MLAK00 LABEL,MODEL MLAK0006301 LG (30.5x21.5 4-1R) Pearl White
5 ACKA00 CAN ASSY,SHIELD ACKA0004701 Black
ABSORBER,ELECTROMAG
6 MAAA00 MAAA0000801 COMPLEX, (empty), , , , , Black 63
NETIC WAVE
Color
6 MCBA00 CAN,SHIELD MCBA0027501 PRESS, STS, , , , , 64
Unfixed
6 MLAB00 LABEL,A/S MLAB0001102 C2000 USASV DIA 4.0 White 60
5 ADCA00 DOME ASSY,METAL ADCA0075701 Black 56
5 MBFP00 BRACKET,CAMERA MBFP0008701 MOLD, PC LUPOY SC-1004A, , , , , Black 68
5 MPBZ00 PAD MPBZ0213701 COMPLEX, (empty), , , , , Black 65
Location
No.
5 MTAC00 TAPE,SHIELD MTAC0067201 COMPLEX, (empty), , , , , Black 66
12.2 Replacement Parts Note: This Chapter is used for reference, Part order
<Main component>
Location
No.
4 BSEA00 SUPPLEMENTARY PART BSEA0003901 PACKING-LIST ENVELOPE
6 BFAA00 FILM,INMOLD BFAA0089301 ; ,BLACK ,0.06 ,46.9 ,43.9 Black
4 SACY00 PCB ASSY,FLEXIBLE SACY0067101 Mian FPCB 20
PCB
5 SACB00 SACB0042201
ASSY,FLEXIBLE,INSERT
5 SACE00 PCB ASSY,FLEXIBLE,SMT SACE0061501
PCB ASSY,FLEXIBLE,SMT
6 SACC00 SACC0039901
BOTTOM
CONNECTOR,BOARD TO 70 PIN,0.4 mm,STRAIGHT , , ,; , ,0.40MM ,STRAIGHT

7 CN101 ENBY0043101
BOARD ,MALE ,SMD ,[empty] , ,
CONNECTOR,BOARD TO
7 CN103 ENBY0022401 50 PIN,0.4 mm,ETC , ,H=0.9, Header
BOARD
7 FL101 FILTER,EMI/POWER SFEY0013601 SMD ,18 V,4ch. EMI_ESD Filter (50 Ohm, 7.5pF)
PCB ASSY,FLEXIBLE,SMT
6 SACD00 SACD0051001
TOP
CONNECTOR,BOARD TO
7 CN100 ENBY0019501 20 PIN,.4 mm,ETC , ,H=1.5, Socket
BOARD
CONNECTOR,BOARD TO
7 CN102 ENBY0016901 40 PIN,0.4 mm,STRAIGHT ,AU ,MALE
BOARD
7 R101 RES,CHIP,MAKER ERHZ0000441 22 ohm,1/16W ,J ,1005 ,R/TP
6 SPCY PCB,FLEXIBLE SPCY0126901 POLYI ,0.4 mm,MULTI-6 ,PYXIS,50/50 ,; , , , , , , , , ,
4 SAEY00 PCB ASSY,KEYPAD SAEY0060601
PCB
5 SAEB00 SAEB0022901
ASSY,KEYPAD,INSERT
5 SAEE00 PCB ASSY,KEYPAD,SMT SAEE0027801 15
PCB ASSY,KEYPAD,SMT
6 SAEC00 SAEC0026301
BOTTOM
7 C100 CAP,CERAMIC,CHIP ECCH0004904 1 uF,6.3V ,K ,X5R ,TC ,1005 ,R/TP
7 C103 CAP,CERAMIC,CHIP ECCH0007802 4.7 uF,10V ,M ,X5R ,TC ,1608 ,R/TP
Location
No.
10000000 pF,6.3V ,M ,X5R ,TC ,1608 ,R/TP , , ,[empty]

7 C105 CAP,CERAMIC,CHIP ECCH0005604
,[empty] ,[empty] ,[empty] ,[empty] ,[empty] ,0.8 mm
CONNECTOR,BOARD TO
7 CN100 ENBY0016801 40 PIN,0.4 mm,STRAIGHT ,AU ,FEMALE
BOARD
EMD2 ,30 V,1 A,R/TP ,VF=1.5V(IF=200mA) ,

7 D100 DIODE,SWITCHING EDSY0011901
IR=30uA(VR=10V)
7 FB100 FILTER,BEAD,CHIP SFBH0008101 600 ohm,1005 ,
7 L100 INDUCTOR,CHIP ELCH0005007 56 nH,J ,1005 ,R/TP ,
7 R100 RES,CHIP,MAKER ERHZ0000406 100 Kohm,1/16W ,J ,1005 ,R/TP
CSP ,35 PIN,R/TP ,CSP3.3x3.3,7Ch,4LDO ,; ,IC,Sub

7 U100 IC EUSY0230103
PMIC
7 VA100 VARISTOR SEVY0001001 14 V, ,SMD ,50pF, 1005
7 ZD100 VARISTOR SEVY0001001 14 V, ,SMD ,50pF, 1005
PCB ASSY,KEYPAD,SMT
6 SAED00 SAED0025901
TOP
WHITE ,ETC ,R/TP ,SIDEVIEW ,; ,[empty] ,2.9~3.75

7 LD100 DIODE,LED,CHIP EDLH0013701
,30mA , , ,120mW ,[empty] ,[empty] ,2P
Location
No.

7 R103 RES,CHIP ERHY0003301 100 ohm,1/16W ,J ,1005 ,R/TP
6 SPEY00 PCB,KEYPAD SPEY0054001 FR-4 ,0.5 mm,BUILD-UP 4 ,PYXIS ,; , , , , , , , , ,
4 SJMY00 VIBRATOR,MOTOR SJMY0008404 3 V,80 mA,10*2.7 , ,; ,3V ,55mA , ,12000 , , , , 24
4 SURY00 RECEIVER SURY0013401 ASSY ,107 dB,32 ohm,11*07 , ,; , , , , , ,CONNECTOR , 19
ASSY ,8 ohm,90 dB,1810 mm,15mm ,; , ,0.7W , , , ,

4 SUSY00 SPEAKER SUSY0028002 27
,[empty]
4 SUSY01 SPEAKER SUSY0028003 ASSY ,8 ohm,90 dB,1810 mm, ,; , , , , , , ,[empty] 21
4 SVCY00 CAMERA SVCY0014001 CMOS ,VGA ,5.5x11.4x3.2t, Magna 1/7.4" 22
MAIN ,240*320(2.4") + 160*64(1.45") ,43*63.7*3.3t ,262k

4 SVLM00 LCD MODULE SVLM0027601 18
,TFT ,TM ,M:R61505U,S:S6D0164 ,Qwerty
3.0 ,-2.0 dBd, ,EGSM+DCS+PCS+W-BAND I, INTERNAL

4 SNGF00 ANTENNA,GSM,FIXED SNGF0034401 #8, 72
,; ,QUAD ,-2.0 ,50 ,3.0
3 SAFY00 PCB ASSY,MAIN SAFY0252501
4 SAFB00 PCB ASSY,MAIN,INSERT SAFB0081001
5 SPKY00 PCB,SIDEKEY SPKY0055801 POLYI ,0.2 mm,MULTI-2 ,PYXIS ,; , , , , , , , , , 57
5 SVCY00 CAMERA SVCY0016001 CMOS ,MEGA ,2M FF Toshiba 1/4" Sensor 59
4 SAFF00 PCB ASSY,MAIN,SMT SAFF0169101 58
PCB ASSY,MAIN,SMT
5 SAFC00 SAFC0105701
BOTTOM
3.0 ,-2.0 dBd, ,GPS, SMD, 10.0*3.0*4.1 ,; ,SINGLE ,-2.0

6 ANT605 ANTENNA,GSM,FIXED SNGF0036601
,50 ,3.0
6 C100 CAP,CERAMIC,CHIP ECCH0002201 0.33 uF,16V ,Z ,NP0 ,TC ,1608 ,R/TP
6 C101 CAP,CERAMIC,CHIP ECCH0000129 120 pF,50V,J,NP0,TC,1005,R/TP
6 C110 CAP,CERAMIC,CHIP ECCH0009101 0.1 uF,6.3V ,K ,X5R ,TC ,0603 ,R/TP
Location
No.
Location
No.


6 C215 CAP,CHIP,MAKER ECZH0001215 1 uF,10V ,K ,X5R ,TC ,1005 ,R/TP
6 C222 CAP,CHIP,MAKER ECZH0003103 0.1 uF,10V ,K ,X7R ,HD ,1005 ,R/TP
6 C227 CAP,TANTAL,CHIP ECTH0002201 10 uF,6.3V ,M ,STD ,1608 ,R/TP
6 C231 CAP,CERAMIC,CHIP ECCH0000163 47 nF,10V,K,X5R,HD,1005,R/TP
Location
No.
6 C232 CAP,CERAMIC,CHIP ECCH0000198 2.2 uF,6.3V ,M ,X5R ,TC ,1005 ,R/TP

6 C234 CAP,CHIP,MAKER ECZH0003503 1 uF,25V ,K ,X5R ,HD ,1608 ,R/TP
6 C235 CAP,CHIP,MAKER ECZH0001421 2.2 uF,6.3V ,K ,X5R ,HD ,1608 ,R/TP
6 C247 CAP,CHIP,MAKER ECZH0000830 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP
6 C252 CAP,CERAMIC,CHIP ECCH0000147 2.2 nF,50V,K,X7R,HD,1005,R/TP
6 C253 CAP,CERAMIC,CHIP ECCH0000179 22 nF,16V ,K ,X5R ,HD ,1005 ,R/TP
6 C254 CAP,CERAMIC,CHIP ECCH0000147 2.2 nF,50V,K,X7R,HD,1005,R/TP
6 C255 CAP,CERAMIC,CHIP ECCH0000179 22 nF,16V ,K ,X5R ,HD ,1005 ,R/TP
22000000 pF,6.3V ,M ,X5R ,HD ,2012 ,R/TP , , ,[empty]

22000000 pF,6.3V ,M ,X5R ,HD ,2012 ,R/TP , , ,[empty]

Location
No.
6 C312 CAP,CHIP,MAKER ECZH0001217 470 nF,6.3V ,K ,X5R ,TC ,1005 ,R/TP
6 C317 CAP,CERAMIC,CHIP ECCH0005603 2.2 uF,10V ,K ,X5R ,TC ,1608 ,R/TP
6 C320 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C321 CAP,CERAMIC,CHIP ECCH0009506 27 pF,25V ,J ,NP0 ,TC ,0603 ,R/TP
6 C325 CAP,CHIP,MAKER ECZH0001121 470 pF,50V ,K ,X7R ,HD ,1005 ,R/TP

Location
No.



6 C501 CAP,TANTAL,CHIP ECTH0003701 10 uF,6.3V ,M ,L_ESR ,1608 ,R/TP
6 C502 CAP,CERAMIC,CHIP ECCH0009106 10 nF,16V ,K ,X7R ,TC ,0603 ,R/TP
2200 pF,10V ,K ,X5R ,TC ,0603 ,R/TP , , ,[empty]

,[empty] ,[empty] ,[empty] ,[empty] ,[empty]
Location
No.
6 C603 INDUCTOR,CHIP ELCH0001056 2.7 nH,S ,1005 ,R/TP ,PBFREE
6 C608 CAP,CERAMIC,CHIP ECCH0000701 1.2 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP
6 C609 INDUCTOR,CHIP ELCH0004727 100 nH,J ,1005 ,R/TP ,
6 C617 INDUCTOR,CHIP ELCH0003820 3 nH,S ,1005 ,R/TP ,PBFREE
6 C621 CAP,CERAMIC,CHIP ECCH0009103 100 pF,50V ,J ,X7R ,TC ,0603 ,R/TP
6 C622 CAP,CERAMIC,CHIP ECCH0000175 2.7 pF,50V ,B ,NP0 ,TC ,1005 ,R/TP
Location
No.
6 C623 CAP,CHIP,MAKER ECZH0000822 1.5 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP


Location
No.
6 C681 INDUCTOR,CHIP ELCH0004713 6.8 nH,J ,1005 ,R/TP ,
100000 pF,16V ,Z ,X7R ,TC ,1005 ,R/TP , , ,[empty]

6 C686 CAP,CHIP,MAKER ECZH0004402
,[empty] ,[empty] ,[empty] ,[empty] ,[empty]
6 C693 INDUCTOR,CHIP ELCH0004718 5.6 nH,S ,1005 ,R/TP ,
Location
No.
6 C696 CAP,TANTAL,CHIP ECTH0005101 2.2 uF,10V ,M ,STD ,1608 ,R/TP
6 C698 INDUCTOR,CHIP ELCH0004720 1.2 nH,S ,1005 ,R/TP ,
33 uF,10V ,M ,L_ESR ,2012 ,R/TP ,; , ,[empty] ,[empty] ,

6 C800 CAP,TANTAL,CHIP ECTH0002002 ,-55TO+125C , ,2.2X1.1X1.1MM ,[empty] ,[empty]
,[empty]


6 C822 CAP,CERAMIC,CHIP ECCH0007802 4.7 uF,10V ,M ,X5R ,TC ,1608 ,R/TP
Location
No.
6 C857 CAP,CHIP,MAKER ECZH0000802 1 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP
CONNECTOR,BOARD TO
6 CN200 ENBY0039301 34 PIN,0.5 mm,ETC , ,H=4.0, Plug
BOARD
18 PIN,0.4 mm,ETC , , ,; ,18 ,0.40MM ,ANGLE

6 CN201 CONNECTOR,I/O ENRY0006801
,RECEPTACLE ,SMD ,R/TP ,
Location
No.
CONNECTOR,BOARD TO 70 PIN,0.4 mm,STRAIGHT , , ,; , ,0.40MM ,STRAIGHT

6 CN400 ENBY0043001
BOARD ,FEMALE ,SMD ,[empty] , ,
CONNECTOR,BOARD TO
6 CN402 ENBY0020401 24 PIN,0.4 mm,ETC , ,H=0.9, Socket
BOARD
3 PIN, mm,ETC , ,3 PIN, 1.9 mm, ETC , ,Battery

6 CN800 CONNECTOR,ETC ENZY0019801
Connector

IR=30uA(VR=10V)
USF ,30 V,1 A,R/TP , ,; , , ,22A , , ,667mW ,[empty]

,[empty] ,[empty] ,1
6 D201 DIODE,TVS EDTY0008602 SOD-323 ,13.3 V,400 W,R/TP ,PB-FREE
6 D800 DIODE,TVS EDTY0008601 SOD-323 ,6 V,400 W,R/TP ,PB-FREE

IR=30uA(VR=10V)
1500 ohm,1005 ,Chip bead ,; ,1500ohm ,1x0. ,[empty]

6 FB201 FILTER,BEAD,CHIP SFBH0009304
,R/TP
6 FL404 FILTER,EMI/POWER SFEY0013201 SMD ,1608 ,EMI-ESD Filter, 4ch, 14V, 15pF, 100ohm
6 FL601 FILTER,SAW SFSY0024301 942.5 MHz,1.4*1.1*0.6 ,SMD ,5pin, Unbal-Bal, 50//150
6 FL602 FILTER,SAW SFSY0024302 1842.5 MHz,1.4*1.1*0.6 ,SMD ,5pin, Unbal-Bal, 50//150
6 FL603 FILTER,SAW SFSY0024303 1960 MHz,1.4*1.1*0.6 ,SMD ,5pin, Unbal-Bal, 50//150
1575.42 MHz,1.4*1.1*0.4 ,SMD ,1574.42M~1576.42M, IL

6 FL604 FILTER,SAW SFSY0033403 1.2, 5pin, U-U, 50-50, GPS HIGH ATTEN. ,; ,1575.42
,1.4*1.1*0.4 ,SMD ,R/TP
1950 MHz,2140 MHz,1.6 dB,2.0 dB,53 dB,44

6 FL605 DUPLEXER,IMT SDMY0001301 dB,3.0*2.5*1.2 ,SMD ,FBAR, WCDMA duplexer ,; ,2140
,44 ,1950 ,53 ,2.0 ,1.6 ,3.0X2.5X1.2 ,DUAL ,SMD ,R/TP
Location
No.
2140 MHz,1.4*1.1*0.62 ,SMD ,2110M~2170M, IL 2.0,

6 FL606 FILTER,SAW SFSY0031201 5pin, U-B, 50-100_10, WCDMA BAND I Rx ,; ,2140
,1.4*1.1*0.62 ,SMD ,R/TP
1950 MHz,1.4*1.1*0.62 ,SMD ,RF Filter for WCDMA

6 FL607 FILTER,SAW SFSY0031101
2Ghz ,; ,1950 ,1.4*1.1*0.62 ,SMD ,P/TR
6 J300 CONN,SOCKET ENSY0018701 6 PIN,ETC , ,2.54 mm,H=1.8
6 L300 INDUCTOR,SMD,POWER ELCP0009401 4.7 uH,M ,2.8*2.6*1.0 ,R/TP ,
6 L301 INDUCTOR,SMD,POWER ELCP0009401 4.7 uH,M ,2.8*2.6*1.0 ,R/TP ,
6 L601 INDUCTOR,CHIP ELCH0004705 8.2 nH,J ,1005 ,R/TP ,
6 L603 INDUCTOR,CHIP ELCH0001052 18 nH,J ,1005 ,R/TP ,PBFREE
6 L607 INDUCTOR,CHIP ELCH0004709 3.3 nH,S ,1005 ,R/TP ,
6 L617 CAP,CHIP,MAKER ECZH0000822 1.5 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP
6 L619 INDUCTOR,CHIP ELCH0001035 4.7 nH,S ,1005 ,R/TP ,PBFREE
6 L622 INDUCTOR,CHIP ELCH0004703 1 nH,S ,1005 ,R/TP ,
6 L623 INDUCTOR,CHIP ELCH0012508 2 nH,S ,1005 ,R/TP ,Film chip, tolerance0.1nH
6 L624 INDUCTOR,CHIP ELCH0003820 3 nH,S ,1005 ,R/TP ,PBFREE
6 L625 CAP,CERAMIC,CHIP ECCH0000175 2.7 pF,50V ,B ,NP0 ,TC ,1005 ,R/TP
6 L629 CAP,CERAMIC,CHIP ECCH0000183 1.8 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP
Location
No.
6 L631 INDUCTOR,CHIP ELCH0003820 3 nH,S ,1005 ,R/TP ,PBFREE
4.7 uH,M ,1 ,R/TP , ,; , ,0.3NH , , , , , ,NON SHIELD

6 L800 INDUCTOR,SMD,POWER ELCP0008004
,2.5X2X1MM ,11MM ,R/TP


PIN ,42 dB,4.72*3.76*1.25 ,MEMS MIC , , , ,OMNI

6 MIC200 MICROPHONE SUMY0010603
,1.5TO5V , ,SMD
SC75-6 ,19 W,-20 V,-12 A,R/TP ,P-Channel FET ,; ,P-

6 Q800 TR,FET,P-CHANNEL EQFP0009401 CHANNEL ,MOSFET ,-20 ,8 ,-12 ,0.041 ,19 ,SC75 ,R/TP
,6P
SC-89 ,0.236 W,30 V,1.3 A,R/TP ,N-Channel FET ,; ,N-

6 Q801 TR,FET,N-CHANNEL EQFN0008501 CHANNEL ,MOSFET ,30 ,20 ,1.3 ,0.129 ,1.3 ,SC89
,R/TP ,6P
6 R103 RES,CHIP,MAKER ERHZ0000295 51 Kohm,1/16W ,F ,1005 ,R/TP
6 R105 RES,CHIP ERHY0009527 47 Kohm,1/20W(0.05W) ,J ,0603 ,R/TP
6 R106 RES,CHIP ERHY0009555 12 Kohm,1/20W(0.05W) ,F ,0603 ,R/TP
6 R108 RES,CHIP ERHY0009522 3.3 Kohm,1/20W(0.05W) ,J ,0603 ,R/TP
Location
No.
6 R214 RES,CHIP,MAKER ERHZ0000220 1500 ohm,1/16W ,F ,1005 ,R/TP
6 R304 RES,CHIP ERHY0009539 20 ohm,1/20W(0.05W) ,F ,0603 ,R/TP
6 R505 RES,CHIP ERHY0000105 51 ohm,1/16W,F,1005,R/TP
6 R602 RES,CHIP,MAKER ERHZ0003801 5.1 ohm,1/16W ,J ,1005 ,R/TP
Location
No.
6 R800 RES,CHIP,MAKER ERHZ0000318 80.6 Kohm,1/16W ,F ,1005 ,R/TP
6 R806 RES,CHIP ERHY0003201 1000 ohm,1/16W ,F ,1005 ,R/TP
Location
No.
,SMD , dB,H=1.85 ,; ,3.00MM ,STRAIGHT ,RF ADAPTER

6 SW601 CONN,RF SWITCH ENWY0005301
,SMD ,R/TP ,AU , ,
BGA(14*14) ,355 PIN,R/TP ,1Gbit NAND+512Mbit DDR

6 U100 IC EUSY0269702
SDRAM, 3G Smart Phone for Open OS MAP
6 U200 IC EUSY0269201 Flip-Chip20 ,20 PIN,R/TP ,8 bit Level Translator, Pb Free
6 U201 IC EUSY0269401 I2C Dual Codec ,48 PIN,R/TP ,
6 U203 IC EUSY0254201 DFN ,12 PIN,R/TP ,Dual SPDT Analog Switch(Pb Free)
6 U204 IC EUSY0317101 WQFN ,10 PIN,R/TP ,1.8*1.4*0.75
SC70 ,5 PIN,R/TP ,Comparator, pin compatible to

6 U206 IC EUSY0250501
EUSY0077701
6 U207 FILTER,EMI/POWER SFEY0015301 SMD ,Pb-free_Bais ,; ,Filter,LCR
6 U208 IC EUSY0333701 TLLGA ,8 PIN,R/TP ,OVP
uCSP ,32 PIN,R/TP ,Audio Subsystem, Class D, Stereo,

6 U209 IC EUSY0339501
Capless ,; ,IC,Audio Sub System
WQFN ,10 PIN,R/TP ,Small package Dual SPDT analog

6 U300 IC EUSY0300101
Switch, PB-Free
FLIP-CHIP 11 ,11 PIN,R/TP ,4-BIT DUAL SUP. BUS

6 U301 IC EUSY0242101
BUFFER LEVEL TRANS / 26 OHM SERIES ON A
TFBGA ,84 PIN,R/TP ,PMIC for Application Processor

6 U302 IC EUSY0269501
Engine of STM, Pb Free
6 U303 IC EUSY0223005 HVSOF5 ,5 PIN,R/TP ,150mA,3.0V,LDO
6 U304 IC EUSY0064501 SOT-23-5 ,5 PIN,R/TP ,2.7V LDO REGULATOR,PBFREE
6 U305 IC EUSY0102802 Micropak ,8 PIN,R/TP ,Daul 2 input AND gate,
Microarray ,49 PIN,R/TP ,Key Scan Controller(up to 72

6 U400 IC EUSY0270601
keys), Pb Free
6 U401 IC EUSY0317101 WQFN ,10 PIN,R/TP ,1.8*1.4*0.75
6 U500 IC EUSY0306201 Micro pak ,8 PIN,R/TP ,D Flip Flip
CSP ,409 PIN,R/TP ,WCDMA/GSM/GPRS/EDGE/HSDPA

6 U501 IC EUSY0295601
Base Band
6 U601 RF MODULE,HANDSET SMRH0004201 MHz, MHz,QUAD EDGE 6x6 ,EMP U300 Tx Module
QFN ,68 ,R/TP ,Quad GSM, Tri WCDMA RF Transceiver

6 U602 IC EUSY0344001
,; ,IC,Tx/Rx
6 U603 MODULE,ETC SMZY0016501 LNA Module(GPS LNA+B/P Filter) ,: ,RF Module
28 dBm,40 %,90 mA,-40 dBc,26.5 dB,4x4x1.1 ,SMD

6 U604 PAM SMPY0015501 ,MSM6280. Tr Switch Func included ,; , , , , , , , ,R/TP
,R/TP ,10
FBGA ,225 PIN,ETC ,1G(LB/64Mx16/2.7V)

6 U800 IC EUSY0336902
NAND+512(4Mx32x4) SDRAM ,; ,IC,MCP
Location
No.
CSP ,97 PIN,R/TP ,PMIC, CMOSRF RTR6285 reference

6 U801 IC EUSY0350001
,; ,IC,PMIC
COUPLER,RF -20.2 dB,0.22 dB,34 dB,10*5*4 ,SMD ,Pb-free_WCDMA ,;

6 U802 SCDY0004101
DIRECTIONAL ,[empty] ,1950MHz ,60MHz ,SMD ,R/TP
Micropak ,6 PIN,R/TP ,Single SPDT Analog Switch, Pb

6 U803 IC EUSY0186502
Free
6 U804 IC EUSY0294701 SON1612-6 ,6 PIN,R/TP ,1.8V 150mA LDO Pb-Free
VMN2 ,5 V,10 W,R/TP ,1.0*0.6*0.4 ,; , ,7.82V , , ,100mW

6 VA207 DIODE,TVS EDTY0009401
,[empty] ,[empty] ,2P ,1
VMN2 ,5 V,10 W,R/TP ,1.0*0.6*0.4 ,; , ,7.82V , , ,100mW

6 VA208 DIODE,TVS EDTY0009401
,[empty] ,[empty] ,2P ,1
6 VA800 VARISTOR SEVY0005402 5.6 V, ,SMD ,1005 Siez , 50pF
6 VA801 VARISTOR SEVY0005402 5.6 V, ,SMD ,1005 Siez , 50pF
19.2 MHz,20 PPM,15 pF,SMD ,3.2*2.5*1.0 ,1.71V ~

6 X300 OSCILLATOR EXSY0022201 1.89V, -20'C ~ +70'C ,; ,19.2MHz ,20PPM ,1.8V ,3.2 ,2.5
,1.0 , ,SMD ,R/TP
19.2 MHz,1.5 PPM,40 pF,SMD ,3.2*2.5*0.9 , ,; , ,1.5PPM

6 X601 VCTCXO EXSK0005703
,2.8V ,3.2 ,2.5 ,0.9 , ,SMD ,P/TP
32.768 KHz,20 PPM,12.5 pF,70 Kohm,SMD ,3.2*1.5*0.9

6 X800 X-TAL EXXY0024301 ,-40'C ~ +85'C, C0 1.05pF, C1 fF ,; ,32.768 ,20PPM ,12.5
, , ,SMD ,R/TP
5 SAFD00 PCB ASSY,MAIN,SMT TOP SAFD0104301




Location
No.
6 RA400 RES,ARRAY,R ERNR0000404 100 Kohm,100 Kohm,8 PIN,J ,1/16W ,SMD ,R/TP
6 RA401 RES,ARRAY,R ERNR0000404 100 Kohm,100 Kohm,8 PIN,J ,1/16W ,SMD ,R/TP
FR-4 ,0.8 mm,STAGGERED-10 ,3-8BVH,PYXIS ,; , , , , , ,

6 SPFY PCB,MAIN SPFY0165201
,,,
6 U402 IC EUSY0362601 SSON004 ,4 ,R/TP ,Hall IC ,; ,IC,CMOS
5 WSYY00 SOFTWARE WSYY0815401 SW-KT610-V10a-MAY-19-2008-H3G-IT-SEC-OFC
3 SAJY00 PCB ASSY,SUB SAJY0030501
4 SAJB00 PCB ASSY,SUB,INSERT SAJB0014001
4 SAJE00 PCB ASSY,SUB,SMT SAJE0024201 67
PCB ASSY,SUB,SMT
5 SAJC00 SAJC0023101
BOTTOM
6 C110 CAP,CHIP,MAKER ECZH0001216 220 nF,10V ,K ,X5R ,TC ,1005 ,R/TP
Location
No.
1.6*1.6*0.6 ,5 V,150 W,R/TP , ,; ,5 ,6 ,15 ,40 ,- ,[empty]

6 D100 DIODE,TVS EDTY0009201
,R/TP ,6P ,4
1.6*1.6*0.6 ,5 V,150 W,R/TP , ,; ,5 ,6 ,15 ,40 ,- ,[empty]

6 D101 DIODE,TVS EDTY0009201
,R/TP ,6P ,4
6 RA100 RES,ARRAY,R ERNR0000403 10000 ohm, ohm,8 PIN,J ,1/32 W ,SMD ,R/TP
6 U101 IC EUSY0293401 VFBGA ,48 PIN,R/TP ,Bluetooth Single Chip(V2.0+EDR)
19.2 MHz,20 PPM,15 pF,SMD ,3.2*2.5*1.0 ,1.71V ~

6 X100 OSCILLATOR EXSY0022201 1.89V, -20'C ~ +70'C ,; ,19.2MHz ,20PPM ,1.8V ,3.2 ,2.5
,1.0 , ,SMD ,R/TP
5 SAJD00 PCB ASSY,SUB,SMT TOP SAJD0025701
3.0 ,-2.0 dBd, ,Bluetooth, SMD, 8.0*2.0*1.2 ,; ,SINGLE ,-

6 ANT100 ANTENNA,GSM,FIXED SNGF0026001
2.0 ,50 ,3.0
2 V,0.5 mAh,CYLINDER ,Reflow type BB, Max T 1.67, phi

6 BAT100 BATTERY,CELL,LITHIUM SBCL0001701
4.8, Pb-Free
33 uF,10V ,M ,L_ESR ,2012 ,R/TP ,; , ,[empty] ,[empty] ,

6 C107 CAP,TANTAL,CHIP ECTH0002002 ,-55TO+125C , ,2.2X1.1X1.1MM ,[empty] ,[empty]
,[empty]
CONNECTOR,BOARD TO
6 CN100 ENBY0039401 34 PIN,0.5 mm,ETC , ,H=4.0, Socket
BOARD
6 FL100 FILTER,SAW SFSY0027301 2450 MHz,2.0*1.5*1.0 ,SMD ,Pb-free_B/T_SAW
6 S100 CONN,SOCKET ENSY0015801 8 PIN,ETC , ,1.1 mm,H=1.9, Detect Pin
5 SPJY00 PCB,SUB SPJY0052201 FR-4 ,0.5 mm,BUILD-UP 6 ,PYXIS(T610) ,; , , , , , , , , ,
12.3 Accessory Note: This Chapter is used for reference, Part order
Location
No.
3.7 V,950 mAh,1 CELL,PRISMATIC ,KT610 Europe

BATTERY PACK,LI-
3 SBPP00 SBPP0025901 BATT, Pb-Free ,; ,3.7V ,950mAh ,0.2C ,PRISMATIC Black 88
POLYMER
,59x37x38 , ,BLACK ,Hardpack ,Europe Label
; ,[empty] ,[empty] ,[empty] ,18pin 6.2mm. NYX Box

3 SGDY00 DATA CABLE SGDY0010908
Package ,BLACK , ,N
; ,RMS 20mW(0.56V,RMS) ,16Ohm+/-2.4Ohm 1KHZ

EAR PHONE/EAR MIKE ,116dB+/-3dB 1KHZ,3mW ,116dB 1KHZ ,96dB 100HZ
3 SGEY00 SGEY0003721
SET ,[empty] ,BLACK ,18P MMI CONNECTOR ,
,Earphone,Stereo
100-240V ,5060 Hz,5.1 V,.7 A,CE ,18pin MMI, Nyx

3 SSAD00 ADAPTOR,AC-DC SSAD0024506
packing, Europe ,; , , , , , ,WALL 2P ,I/O CONNECTOR ,
100-240V ,5060 Hz,5.1 V,.7 A,CE ,18pin, Europe, Viewty

ADAPTOR,AC-DC SSAD0024507
packing ,; , ,5.1V ,0.7A , , ,WALL 2P ,I/O CONNECTOR ,
Note
Note

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Service Manual

Internal Use Only

Date: June, 2008 / Issue 1.0

1.2 Regulatory Information

E. Notice of Radiated Emissions

G. Interference and Attenuation

H. Electrostatic Sensitive Devices

2.1 System Overview

Shape GSM900/1800/1900 and WCDMA Communicator Handset

Size 108.9 X 53.9 X 17.2 mm

Weight 124 g (with 950mAh Battery)

Power 3.7V normal, 950 mAh Li-Polymer

Talk Time Over 170 min (TX = 12dBm,Low Power mode)

Standby Time Over 220 hours (DRX = 1.28)

Antenna Internal type and Antenna

LCD Backlight LED Back Light (Main, Sub)

Camera Dual Camera ; 2 Mega pixel (CMOS), VGA Camera (CMOS)

Vibrator Yes (Cylinder Type)

Earphone Jack Yes

Connectivity Bluetooth, USB

Volume Key Push Type (+, -)

External Memory Micro-SD

I/O Connect 18 Pin

2.2 Usable environment

Voltage 3.7 V(Typ), [Shut Down : 3.22 V]

Operation Temp -20 ~ +60 °C

Storage Temp -20 ~ +70 °C

2.2.2 Environment (Accessory)

TA Power Available power 100 220 240 Vac

2.3 Radio Performance

2.3.1 Transmitter - GSM Mode

No Item GSM DCS & PCS

1 Conducted MS allocated 100k~1GHz -39dBm 9k ~ 1GHz -39dBm

Spurious Channel 1G~[A]MHz -33dBm

Emission 1G~12.75GHz -33dBm [A]M~[B]MHz -39dBm

Idle Mode 100k~880MHz -60dBm 100k~880MHz -60dBm

880M~915MHz -62dBm 880M~915MHz -62dBm

915M~1GHz -60dBm 915M~1GHz -60dBm

1G~[A]MHz -50dBm 1G~[A]MHz -50dBm

[A]M~[B]MHz -56dBm [A]M~[B]MHz -56dBm

[B]M~12.5GHz -50dBm [B]M~12.5GHz -50dBm

2 Radiated MS allocated 30M ~ 1GHz -36dBm 30M~1GHz 36dBm

Spurious Channel 1G~[A]MHz -30dBm

Emission 1G ~ 4GHz -30dBm [A]M~[B]MHz -36dBm

Idle Mode 30M ~ 880MHz -57dBm 30M~880MHz -57dBm

880M ~ 915MHz -59dBm 880M~915MHz -59dBm

915M~1GHz -57dBm 915M~1GHz -57dBm

1G~[A]MHz -47dBm 1G~[A]MHz -47dBm

[A]M~[B]MHz -53dBm [A]M~[B]MHz -53dBm

[B]M~4GHz -47dBm [B]M~4GHz -47dBm

No Item GSM DCS & PCS

3 Frequency Error ± 0.1ppm ± 0.1ppm

4 Phase Error ± 5(RMS) ± 5(RMS)

Under Multipath and RA250 : ± 200Hz RA250: ± 250Hz

Interference Condition HT100 : ± 100Hz HT100: ± 250Hz

TU50 : ± 100Hz TU50: ± 150Hz

TU3 : ± 150Hz TU1.5: ± 200Hz

6 Output RF Due to 0 ~ 100kHz +0.5dB 0 ~ 100kHz +0.5dB

Spectrum modulation 200kHz -30dB 200kHz -30dB

250kHz -33dB 250kHz -33dB

400kHz -60dB 400kHz -60dB

600 ~ 1800kHz -60dB 600 ~ 1800kHz -60dB

1800 ~ 3000kHz -63dB 1800 ~ 6000kHz -65dB