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482 IEEE~~~~~~~~~~~~~~~~~~~~-- ---- - ----

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-Indicon 2005 IEEE Indicon 2005 Conference, Chennai, India, II 1 3 Dec. 2005
Conference. Chnai nda -- 1-1
- Dec 2005

A New Push-Pull Zero Voltage Switching


Quasi-Resonant Converter: Topology, Analysis and
Experimentation
S. Arulselvil C.Subashini2 and G. Uma3

Abstract- This paper introduces a new buck type push-pull Zero proposed. The proposed method reduces the switching losses
Voltage Switching Quasi Resonant Converter (ZVS-QRC) in and size of the converter. It can be used as high-density power
continuous conduction mode. Theoretical analysis and design supply for aerospace applications.
methodology for a IOOW, 25 kHz laboratory prototype
push-pull ZVS-QRC are discussed in this paper. The simulation
and experimental results are also presented. The proposed Il. ANALYSIS AND DESIGN OF PUSH PULL ZVS QRC
converter is suitable for aerospace applications.
Keywords - push-pull converter, Zero Voltage Switching Quasi The proposed push-pull topology is basically two forward
Resonant Converter (ZVS-QRC), UC3861 analog controller. converters connected in anti-phase as shown in Fig. 1. An ad-
ditional two resonant tanks are added in this topology com-
pared to PWM push-pull converter. The resonant tank shapes
I. INTRODUCTION the switch voltage so that the active switches (S1 and S2) are
Pulse Width Modulation (PWM) based switched mode turned-on at ZVS. Hence the turn-on losses of the switch will
dc-dc converters play an important role in communica- be reduced considerably compared to PWM converters. Both
tion, automobile, computer and aerospace applications. primary and secondary windings are arranged in a cen-
In aerospace applications the allowable size and weight are ter-tapped configuration. The push-pull converter operates in
highly restricted to accommodate greater payload. To in- two quadrants (I and III) of the B-H curve, see-sawing back
crease the power packing density and to reduce the weight of and forth as the each primary is activated. This allows the
the magnetic components, it is desirable to operate the con- push-pull converter to deliver twice the maximum power than
verters at high switching frequencies. The conventional that of a forward converter. This makes the proposed con-
PWM switched mode converters are unsuitable at high fre- verter effective for medium anid high power applications. The
quencies as they experience high switching losses, high different modes of operation are explained in the following
switching stresses, reduced reliability, electromagnetic inter- section
ference and acoustic noise. To overcome the above disadvan-
tages, a new family of Quasi Resonant Converters (QRCs) is Si Dl L.f
reported [I]-[2]. Few research papers have been presented
about the design and implementation of push-pull hard
switched and Quasi Resonant converters [3]-[5]. Push-pull +ro
converter is mainly used for medium and high power applica-
tions compared to half-bridge and full-bridge converter. It
has wide duty ratio control and it can be used for multi-output
applications with low output and input ripple current.
In many applications, to generate switching pulses a sepa-
rate analog pulse generating circuit with opto coupler and
driver circuit is used [6]. These drawbacks are overcome by
using a dedicated analog resonant controller IC UC3861
[7]-[8]. A separate gate drive and fault protection circuit is Cr2
not required for the proposed controller. Hence, in this paper Fig. 1. Circuit diagram of push- pull ZVS-QRC
push-pull ZVS-QRC with IC UC3861 for pulse generation is
I2&3 College of Engineering, Anna University, Chennai - 600 025, INDIA. A. Modes of operation
arulselvi_2k3(yaboo.co.in', subashini2002356l7(yahoo.co.in2 The switches SI and S2 alternately power their respective
uma(annauniv.edu3 windings. The resonating capacitors Cri and Cr2, the resonat-
ing inductors Lri and Lr2 are used to form the resonant tanks.
0-7803-9503-4/05/$20.00 02005 IEEE

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483
The secondary voltage of the transformer is rectified by fast and iLrl(O)=-Im/2 (17)
recovery diodes (D1 and D2) and filtered to produce a steady The solution for the equations are given by
ripple free output voltage VO. Lower and upper part ofprimary iLrj(t)=-(Im/2)cos)o.t (18)
winding circuit is called here afterwards as Upper and Lower. VCrI(t)=2Vdc-(Im/2)sincoot (19)
Mode J:(to,td) This stage terminates when vcri(t) becomes zero. The dura-
tion of this stage is given by
Upper: The switch SI is opened for the beginning of a new
cycle at t equal to to. The current flows through resonant ca- Td4 =t4-t3 (20)
pacitor (Crl) and resonant inductor (Lri). The capacitor volt- Td4=(1/co0)sin [Vdc/(IrZo)] (21)
age rises linearly from zero to 2Vdc. The capacitor voltage is Td4- (c-)/Ioo (22)
given by the equation where ai=l+(sinWI[4Vdc/ImZo]) (23)
VCrl(t) = Imt/2Cr (1)
The inductor current is given by
When the resonant capacitor voltage reaches 2Vdc at t = t1.
The duration of this interval Tdi is given by iLrl=(Im/2)cosa (24)
Lower: vcr2 is zero and
Tdl=4CrVdc/Im (2)
diLr2/dt-(2Vdc-vcr2(t))/Lr2 (25)
Lower: The switch S2 opened in the previous cycle is still
with initial conditions
continued. The capacitor voltage vcr2 in the lower part de- ilr2(0) = Im/2 (26)
creases linearly from 2Vdc to Zero. The equations for vcr2 and
The solution for the above equation is
iLr2 are given as
Vcr2(t) = 2Vdc-(Im/2)Zosinolot (3) iLr2(t)=(Im/2)cos(c)ot) (27)
iLr2(t)=--IJcos(Oot (4) Mode 4: (t3,t4)
Mode 2:(t,,tz) Upper: The switch SI is turned on when vcri become zero to
Upper: The series resonant Lri and Crl forms a resonant cir- achieve zero voltage condition. During this mode the current
cuit. The state equations are iLrl increases linearly and reaches the value 1rn2 at t equal t4.
dVCrt/dt=- iLrI(t)/Crl (S) The corresponding state equation is
diLrt/dt=(2V&-vcrl(t))/Lrl (6) diLrl/dt-2Vdc/Lrl (28)
with initial conditions With initial condition
VCrl(O) = 2Vdc (7) iLrl(O) ( Im/2)cosac (29)
and iLri(O)='m/2 (8) The inductor current iLrl(t) is given by the equation
The solutions for the above equations are rl(t)=((2Vdc*t)/Lr)+((Im/2)cosa) (30)
VCri(t) = 2Vdc+(Im/2)ZosincoOt (9) This mode terminates when inductor current become Im. The
iLrl(t)-(Im/2)coso0ot (1 0) duration of this stage is given by the equation
At t equal to t2, iLrl reaches zero value and vcrl reaches its Td4=t4-t3 (31)
peak value as shown in Fig.2.a. They are given by Td4=[ImZJ4VdcO)o]( I -cosa) (32)
VCrl(t2)= 2Vdc+(Lm/2)Zo ( 11) is
Lower: The switch S2 opened at t = t4. The current flows
The duration of the mode Td2 is given by through resonant capacitor (Cr2) and resonant inductor (iLr2).
Td2=t2-t1=nr/Co (12) The capacitor voltage rises linearly from zero to 2Vdc and it is
Lower: The switch S2 is turned on when VCr2 become zero at governed by the equation
t=t1, to achieve zero voltage condition. During this stage the vc,2(t)=(I.t)/2C,l (33)
current iLr2 increases linearly and reaches the value Im/2 at At the end of this mode, a new cycle starts.
t= t2. The corresponding state equation for iLr2 is B. Theoretical resonant waveforms
diLr2/dt = 2Vdc/Lr2 The theoretical resonant waveforms of the proposed con-
The solution of the above equation is given by
verter for one switching cycle are shown in Fig 2. Whenever
iLr2 (Im/2)coso)ot
=
(13) there is a change in switching device from one state to an-
Mode 3:(t2,t3) other, the circuit configuration changes. Each configuration is
Upper: The equations determining this stage are referred to as mode. In this QRC, four different stages are
diLr1/dt=(2Vdc-VCrI(t))/Lr1 (14) identified for each half of the switching cycle.
and dvcr2/dt=iLrl(t)/Cr (15) C. Design
With initial conditions
VCrl(O)= 2Vdc (16) The design procedure is explained for push-pull ZVS-QRC
with the following specifications:

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484
484 IEEE Indicon 2005 Conference-:Chennai,
IEEE ofeene
--, ChennaI---
---I.-
205 India,
India
Indicon~~~~~~~~~~~~~~~~~~~~~~~~~~~----- - Dec. 2005---
11-13 Dec
1-1 2005
Input voltage Vdc =40V III. OPEN LooP STUDIES
Output Voltage VO =24V
Resonant frequency f0=165 kHz This section presents the simulation results of the proposed
Switching frequency f5 =25 kHz converter. It is proposed to study the control characteristics of
Normalized switching frequency f"5 =f1/ f0=O. 15 push-pull ZVS-QRC. The simulated resonant capacitor volt-
Power rating PO =1OOW age and inductor current ofthe converter are also discussed in
Turns ratio between primary and this section.
Secondary n=Np, / N, The converter is siinulated using SPICE Software in open
=Np2 / Ns2 loop with design parameters. The gating pulses applied to
The characteristic impedance ZO= sqrt (LICr) switch SI an-d S2 and the corresponding resonant capacitor
The resonant angular frequency co =(1/2n )JLrCr
voltage and resonant inductor current is shown in Fig.3 and
Fig.4 respectively.
Resonant inductor Lr >(lI/o))*(nlIo)*Vdc It is observed that the switch S I and S2 are turned on, when
Resonant capacitor Cr < (l/kO)*(Io/n)*(lNVdC)) the resonant capacitor voltage becomes zero to assure
The resonant capacitors are assumed to be equal ZVS condition. This waveform resembles the theoretical res-
Cr=Crl = Cr2O0.047 [tF. onant waveforms as shown in Fig.2.
The resonant inductors are assumed to be equal
Lr=Lrl=Lr2=0.16mH.
cn

G SEL>M
4A Vgi a II(S1.2:+,-)
rD
2
b- 0
El
Ck, Q
-id
JL) 4u 5U- A
1
2Vdc i1m
9 0
C* ::.. 2wd0
w
od rn,~
9 94M3
4.*q *^5 4.4*6 . 4.976M
-.9
u 0 a> V(I:1,S) * J(12:t,6)
-9 2i -11rn2
--,-

A k=.,
4- -ti Fig.3. Gating pulses to switch S1, Resonant inductor current (iLrl)
9 t:
:3
and Resonant Capacitor Voltage (VCrl) for Upper part of primary
tA
d) Q
9 circuit.
a. Upper part of primary circuit.
*5

C
P.
Cl

t 2...4...
I'~~~~~'

/2t t t t !

TdlI d2lTd3 dT Fig.4. Gating pulses to switch S2, Resonant inductor current
b. Lower part of primary circuit (iLr2),and Resonant Capacitor Voltage (VCr2) for Lower part of
Fig.2. Theoretical resonant waveforms of push-pull ZVS-QRC. primary circuit.

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IEEE Indicon 2005 Conference,
IEEE
Chennai, India, I I 1 3 Dec.
Conference_Chennai_India_11-13
Indicon 2005 Dec. 2005
2005 -
485
485
IV. HARDWARE IMPLEMENTATION
0. OV 25.OV O.OOs 10.0ri fl SW
An experimental model of the push-pull ZVS-QRC operat-
ing in buck mode is implemented with the designed parame-
ters. Power MOSFETs IRF540 is used as active switches. A , .,,, ..,,, .,,,
.;. . . .. ....... .. .. . .... ... .. ..
fast recovery schottky diodes FR107 are used as freewheeling
diodes. The schematic power circuit and open loop experi- .. . ..... .. ... .. ..

mental setup are shown in Fig.5 and Fig.6 respectively. The .~~~~~~~~~~~~~~~~~........ . ........, ......... ......... ' ...,. . .........

gating pulses to switch Si and S2 are generated using UC3861


is shown in Fig.7. The resonant capacitor voltages vcrl and .. .. ........... .....,.... ,.....

vcr2 are shown in Fig.8. The nominal converter output voltage


(VO) is shown in Fig.9. It is observed from Fig.7 and Fig.8 that ......... ......... .. . ......... ......... ......... .........

the switches SI and S2 are turned on, when vcrl and vcr2 be-
comes zero respectively.
The efficiency of the converter for various load condition is
shown in Fig. 10.
Fig.7. Gate pulse generated by UC13861 to switch S1 and SI S2
E1 GI
5.4
0
150.OV 250.OV rQ0S 10.0I ( $i Kw
b ........................... ......... ....................

........ ........ ........ ......... .......

p4
'.4
n
P
14
P.i
c)
04
.... ........

.............

Fig.5. Power circuit model of push-pull ZVS -QRC. Time (microsecond)


Fig.8. Resonant capacitor voltage vc,l and vcr2.
a c Air f r Air _I%m 10n 41 amI

r0. OOs 1OOs fl STOP

f
. lO.OV.0
I
--.

:
4
.........''1 '''''''''
.. .'..
.'... .'.. ...'.. .. ... ... ..

. s~~~
......... ......... ......... ........ ........ .. ..... .. ......... ... ..... .........

11 . S I L II L II JI
.t , s
1 w ......................... ...........................__I
~~~~~~~~~~~~........ . ..
......,.=
L
4
t .

t c
............. ......... ....
......... ......... ........ ........ .........
t
0-

......... ......... .. ......... .. .. .. .. ......... .. ......... i


d
Time (second)
Fig.9. Output voltage of push-pull ZVS-QRC.
Fig. 6. Open loop experimental setup.

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486 IEEE fndicon 2005 Conference, Chennai, India, I I 1 3 Dec. 2005 -
-

1-
97 REFERENCES
96
[1] Liu K.H. and Lee F.C.Y., Zero-Voltage Switching Technique in
c
95 Abs--
DC-DC Converters, IEEE Specialists Conference Record, 1986,
._ 94 pp.58-70.
93 -0.
qp
[2] Barbi, J.C.Bolacell, D.C.Martins and F.B.Libano, Buck Quasi-Reso-
f.
92 3
nant Converter Operating at Constant Frequency: Analysis, Design and
339 344 349 354 Experimentation, IEEE, pp. 873-880.
Load Current (mA) [3] Wildon C. P., de Aragao Filho, I. Barbi, A Comparison Between Two
Current- Fed Push-Pull DC-DC Converters- Analysis, Design and Ex-
Fig.1O. Efficiency of push-pull ZVS-QRC. perimentation, IEEE 1996, pp.3 13-320.
[4] Grover V., T. Bascope and I. Barbi, Isolated Flyback-Current-Fed
Push-Pull Converter For Power Factor Correction, IEEE, 1996,
V. CONCLUSION pp.1 184-1190.
[5] B. Swaminathan and V. Ramanarayanan, A Novel Resonant Transition
Theoretical analysis and design procedure of a new buck Push-Pull DC-DC Converter, J. Indian Inst. Sci, Nov.- Dec. 2004,
type push-pull ZVS-QRC was presented. A laboratory proto- 84,pp.217-232.
type rated at 100 W, operating at switching frequency of [6] G.Uma, M. Shanthi and C. Chellamuthu, Design and Implementation
25kHz and resonant frequency of 165kHz has been imple- of Constant Frequency Soft Switched Regulated Power Supply for
mented and tested for minimum and maximum load condi- Aerospace Applications, IEEE-ISIE'2000, Cholula, Puebla, Mexico.
tion. Operating principle and theoretical analysis were [7] B. Andreycak, Zero voltage switching resonant power conversion, Ap-
confirmed by simulation and experimental results. The pulse plication note., Unitrode corp., slusl38.
generation for the converter is achieved by using single chip [8] S.Arulselvi, T.Archana and G.Uma, Design and Implementation of
UC3861 resonant controller. This controller has inbuilt refer- Constant Frequency Zero Voltage Switching Quasi Resonant Control-
ence voltage generator, Zero voltage detection and fault de-
ler UC3861 for Aerospace Applications, IEEE-International Confer-
ence on Power System Technology, Singapore, 21-24th Nov., 2004.
tection circuits. This makes the circuit compact and also the
switching losses and stress are reduced by ZVS condition.
Hence, this is suitable for high-density, medium power
requirement, for example in aerospace applications.

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