VLSI Lab Manual PART-A, VTU 7th Sem KIT-Tiptur

VLSI Lab Manual
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FOR VII SEMESTER E&C ENGG., AS PER VTU SYLLABUS
Department of Electronics and Communication Engineering

KALPATARU INSTITUTE OF TECHNOLOGY
TIPTUR-572202
VLSI LAB VII Semester
CONTENTS
PROCEDURES FOR DIGITAL DESIGN Page No.

1. Syllabus 2
2. Prerequisites 5
Directory Structure
Steps to Invoke Tool
3. Verification 6
Compilation
Elaboration
Simulation
4. Synthesis 11
Running Synthesis
Timing Constraints or SDC file
5. Experiment 1 14
Inverter – digital design
6. Experiment 2 15
Buffer
7. Experiment 3 16
Transmission gate
8. Experiment 4 17
Logic gates
9. Experiment 5 19
Flip-flops
10. Experiment 6 27
Serial and Parallel adders
11. Experiment 7 30
4-bit counters (Synchronous & Asynchronous)
12. Experiment 8 33
Successive Approximation Register
PROCEDURES FOR ANALOG DESIGN

13. Custom IC design flow 36
Initial procedures
Steps for design entry
Steps for simulation and layout
14. Experiment 9 41
Inverter – analog design
15. Experiment 10 65
Common source & Common drain amplifiers
Single stage differential amplifier
Operational amplifier
4-bit R-2R DAC
SAR Based ADC
20. VIVA Questions 91
21. Books Referred 94
23. Physical Verification 95
Assura DRC
Assura LVS
Assura RCX
Department of Electronics & Communication, K.I.T, Tiptur 1

SYLLABUS
(Wherever necessary Cadence/Synopsis/Menta Graphics tools must be used)
PART – A
DIGITAL DESIGN
Asic-Digital Design Flow

Write Verilog Code for the following circuits and their Test Bench for verification,
observe the waveform and synthesize the code with the technological library, with the
given Constraints*. Do the initial timing verification with gate level simulation.
i. An inverter
ii. A Buffer
iii. Transmission Gate
iv. Basic/universal gates
v. Flip flop - RS, D, JK, MS, T
vi. Serial & Parallel adder
vii. 4-bit counter [Synchronous and Asynchronous counter]
viii. Successive approximation register [SAR]
* An appropriate constraint should be given
PART – B
ANALOG DESIGN
Analog Design Flow

1. Design an Inverter with given specifications*, completing the design flow mentioned
below:
a. Draw the schematic and verify the following:
i) DC Analysis
ii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design
e. Verify & Optimize for Time, Power and Area to the given constraint***
2. Design the following circuits with the given specifications*, completing the design flow
mentioned below:
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design.
i) A Single Stage differential amplifier
ii) Common source and Common Drain amplifier

3. Design an op-amp with the given specification* using given differential amplifier,
Common source and Common Drain amplifier in library** and completing the design
flow as mentioned below:
i) DC Analysis
ii) AC Analysis
c. Check for LVS
4. Design a 4 bit R-2R based DAC for the given specification and completing the design
flow mentioned using given op-amp in the library**.
i) DC Analysis
ii) AC Analysis
c. Check for LVS
5. For the SAR based ADC mentioned in the figure below, draw the mixed signal
schematic and verify the functionality by completing ASIC Design flow.
[Specifications to GDS-II]
* Appropriate specification should be given.

** Applicable Library should be added & information should be given to the Designer.
*** An appropriate constraint should be given.
Overview
The focus of this course is the CAD based VLSI design flow. The entire VLSI
design industry makes use of this design flow in some or the other. Proficiency and

familiarity with the various stages of this design flow is a prerequisite for any student
who wishes to be a part of either the industry or their search in VLSI.
Over this course, exposure to various stages of a typical, state of the art Cadence
VLSI tool be provided by various experiments designed to bring out the key aspects of
each important module in the Cadence tool including the synthesis , place and route,
layout, LVS, simulation.
Students will learn how to manage the files with the Library Manager, understand
the basics of the Schematics Editor, and simulate a simple circuit using the Analog
Design Environment (ADE). Understand the differences between using ideal and real
circuit elements.
Course Objectives
1. To provide an introduction to the fundamentals of Computer-Aided Design tools

for the modeling, design, analysis, test, and verification of digital Very Large
Scale Integration (VLSI) systems.
2. To understand and experience VLSI Design Flow, Learn Transistor - Level
CMOS Logic Design with Top-down and Bottom up approach.
3. To familiarize the students with the basics of the Cadence® Custom IC design
tool, Virtuoso®. RC Compiler, NCsim.
Course Outcomes
After studying this course the students would gain enough knowledge,
1. Establish comprehensive understanding of the various phases of CAD for digital

electronic systems, from digital logic simulation to physical design, including test
and verification.
2. Students are able to use Cadence Virtuoso Platform for verification of
functionality and simulation of RTL Verilog model.
3. The student would have hands on experience in the carrying out a complete VLSI
based experiments using CADENCE.
4. To have experience with a logic synthesis tool (RC Compiler) for mapping RTL
onto a cell library.
5. To understand designing full custom integrated circuits includes schematic entry,
behavioral modeling (Verilog - AMS), circuit simulation; full custom layout,
physical verification, extraction and back – Annotation.
Breadth options
This subject potentially can be taken as a breadth subject component for ASIC
Design, System on Chip Design, Testing and verification in VLSI, Low Power VLSI.
Prerequisites: CMOS VLSI Design, Logic Design, Digital Electronics

Prerequisites
Directory Structure
Before starting the flow, follow the below library structure. This is not mandatory but will
help in separating design files, library files, log files and command files generated by tools.
root
Cadence_tool
s
cadence_datab
ase
Design Directory
Experiment Directory
rtl synthesis lib
Below figure (fig 1) is an example for the directory structure created for a counter design.
Fig 1
Save your design (RTL files) inside the RTL directory and keep both RTL as well as test
bench inside the RTL directory. Libraries and Constraint files (SDC files) are kept in respective
directories. RTL and Synthesis directories are used to run simulation and synthesis so that all
log files, command files and other tool generated files won’t get mixed up.

Steps to Invoke Tools:
➢ Before invoking any tool, invoke C shell be typing ‘csh’ in terminal.
➢ Source the cshrc file by typing ‘source <cshrc file>’
e.g.:- source cshrc
Note: Every time you open a new terminal to invoke the tool, above steps should be followed.
Verification
IES (Incisive Enterprise Simulator) is the tool used for verification. Navigate to Simulation
directory where you have kept your RTL and test bench (rtl directory). Invoke the tool by typing
‘nclaunch -new -64’ in the terminal. Below figure (fig 2) shows how to invoke C shell, source
cshrc and invoke Incisive tool to simulate an inverter design.
1. NCLaunch window will appear, and in the NCLaunch window, select ‘Multiple Step’
option

2. On clicking the ‘Multiple Step’ option, ‘nclaunch: Open Design Directory’ window will
appear as shown.
3. Click on ‘Create cds.lib File’ option and a ‘Create a cds.lib file’ window will open. Click
‘Save’ option.

4. A ‘New cds.lib File’ window will appear. Click on don’t include any libraries option
available depending on your RTL and click ‘OK’. As the inverter design is in verilog, the
third option is selected.
5. Click ‘OK’in the ‘nclaunch: Open Design Directory’ window.
6. In the NCLaunch window, we will be able to see the design as well as the test bench
that we kept inside the rtl directory.Click ‘OK’.

Compilation
7. The next step is to compile (Checks syntax and semantics) the code. For this, select
both the design and test bench and choose the appropriate compilers. ncvlog for Verilog
designs. (Choose ncvlog for inverter design as the design is in Verilog)
Elaboration
8. The next step is elaboration, open the ‘worklib’ directory on the right side of the window
and we can see the design objects created inside. Select the testbench module and
select the ‘launch elaborator’ (ncelab) key.

Simulation
9. Open the ‘snapshots’ folder and select the snapshot and click on ‘launch simulator’
option.
10. ‘Launch simulator’ will open ‘Design Browser’ and ‘console’ windows. ‘Console –
SimVision’ window can be used to perform simulation in command mode and hence can
be minimized while using ‘Design Browser –SimVision’window to run simulation in GUI
mode. Select send to waveform window.

11. In the Design Browser window, select the testbench module (inverter_tb) and select
the ‘waveform’ option. A ‘waveform –SimVision’ window will appear and run waveform.
Synthesis
The tool used for synthesis (converting RTL to gate level netlist) is RTL Compiler (RC).
Running Synthesis
Change the directory from rtl to synthesis and write a script file for synthesis(rc_script.tcl). Below
is an example of a script file for synthesis
The necessary inputs to perform synthesis are RTL, standard cell library and constraints.
Fig: Synthesis
Let us see the usage and purpose of each command.

• set_attr library <library name with path>
This command will set the library file & path of the standard cell library.
• read_hdl <rtl filename with path>
This command will set the path for rtl files and read the file.
Note:-If the design is hierarchical or has multiple modules instantiated inside the top
module, use curly braces ‘{ }’ to mention all modules including the top design.
• elaborate
The elaborate command constructs design hierarchy and connects signals.
• read_sdc<sdc file name with path>

This command reads in the timing constraints file. Here we have to provide the
constraints file name along with the path. Explanation on constraints file is provided .
• Synthesize –to_mapped
This command will perform synthesis by combining the generic, mapped and
incremental synthesis .
➢ Include all the above commands in the script file.
Note: - In help_ug folder in desktop, you can see a script file ‘rc_script.tcl’ inside the
synthesis directory. Please open the script file for further understanding.
Figure Synthesis previous page shows script file
Timing Constraints or SDC file:

Now let us understand the content of the Constraints or SDC file.
Using SDC, we define clock period, pulse width, rise and fall time, uncertainty and also
input and output delays for different signals. Below is the constraints file used in counter
design.
Let us see the usage and purpose of each command.

• Create_clock –name –period 10 –waveform {0 5} {get_port “clk”}
This command will define clock with period 10ns and 50% duty cycle and signal is high
in the first half.
• ‘Set_clock_transition –rise/fall’ command defines the transition delay for clock.
• ‘Set_clock_uncertainty’ command will set the uncertainty due to (clock skew and
jitter).
• ‘Set_input/output_delay’ command will specify the input and output delay used
for timing slack calculations.
Keep the constraints file inside the Synthesis directory.

Note: - To know more about writing timing constraints, please refer the rc_ta.pdf
available inside the doc/rc_ta directory of the tool.
i.e., - <RC_tool directory>/doc/rc_ta/rc_ta.pdf
Once the script file to run synthesis and the constraints file are ready, we can initiate
synthesis.
Use the below command to invoke RTL compiler along with the script file.
rc -f <script file name with path>
‘rc’ is the command to invoke RTL Compiler and ‘-f’ option is used to passes the script
to RC at the time of launching the tool. RC will execute each commands mentioned
inside the script file one by one.
Note: - If the script file is in the current working directory (synthesis directory), we need
not have to provide the path for the script.
E.g. - In case of the inverter design, the command will be ‘rc –f rc_script.tcl’
While performing synthesis, always check the RC terminal whether the tool is reporting
any error. Figure below depicts the procedure to perform synthesis in RC terminal.

Experiment 1
Logic Inverter
Aim: To compile and to simulate the Verilog code for an inverter, and then to synthesize
the same for the given constraints.
Logic symbol:
Verilog Code:
// Inverter Design
module inverter(a,b);
input a;
output b;
assign b=~a;
A B
endmodule 0 1
1 0
Testbench:
module inverter_test;
reg a;
wire b;
inverter inverter1(a,b);
initial
begin
a=0; #10
a=1;#10
$stop;
end
endmodule
Waveform:
Constraints file for Synthesis:

set_input_delay -max 1.0 [get_ports "a"]
set_output_delay -max 1.0 [get_ports "b"]

Experiment 2
Buffer
Aim: To compile and to simulate the Verilog code for a buffer, and then to synthesize
the same for the given constraints.
Logic symbol:
Verilog Code:
// Buffer Design A B
module buffer(a,b); 0 0
1 1
input a;
output b;
assign b=a;
endmodule
Test Bench:
module buffer_test;
reg a;
wire b;
buffer buffer1(a,b);
initial
begin
a=1;#10;
a=0;#10;
$stop;
end
endmodule
Waveform:

set_output_delay -max 1.0 [get_ports "b"]

Experiment 3
Transmission Gate
Aim: To compile and to simulate the Verilog code for a transmission gate and then to
synthesize those designs for the given constraints.
Logic symbol:
Verilog Code:
// Tg Design
module tg(s,in,out);
input s,in; output out;
reg out;
always @ (s or in)
begin
if (s)
out<= in;
else S In Out
out <=1'bZ; 1 0 0
end 1 1 1
0 0 Z
endmodule 0 1 Z
Test Bench:
module tg_t;
reg s, in;
wire out;
tg tg1 (s, in, out);
initial
begin
s=0; in=0; #100;
s=0; in=1; #100;
s=1; in=0; #100;
s=1; in=1; #100;$stop;
end
endmodule
Waveform:

set_input_delay -max 1.0 [get_ports "in"]
set_input_delay -max 1.0 [get_ports "s"]
set_output_delay -max 1.0 [get_ports "out"]

Experiment 4
Basic/Universal Gates
Aim: To compile and to simulate the Verilog code for the basic logic gates, and then to
Logic symbol:
A B And_gate Or_gate Xor_gate Nand_gate Nor_gate

0 0 0 0 0 1 1
0 1 0 1 1 1 0
1 0 0 1 1 1 0
1 1 1 1 0 0 0
Verilog Code:
// Basic Gates Design

module gates (a,b,and_gate,or_gate,nand_gate,nor_gate,xor_gate);
input a,b;
output and_gate,or_gate,nand_gate,nor_gate,xor_gate;
assign or_gate=(a|b);
assign and_gate=(a & b);
assign nand_gate=~(a & b);
assign nor_gate=~(a|b);
assign xor_gate=(a^b);
endmodule
Test Bench
module gates_test;
reg a,b;
wire and_gate,or_gate,nand_gate,nor_gate,xor_gate;
gates gates1(a,b,and_gate,or_gate,nand_gate,nor_gate,xor_gate);
initial begin
a=0;b=0;
#10;
a=0;b=1;
#10;
a=1;b=0;
#10;

a=1; b=1;
#10;
end
endmodule
Waveform:

set_input_delay -max 1.0 [get_ports "b"]
set_output_delay -max 1.0 [get_ports " and_gate"]
set_output_delay -max 1.0 [get_ports " or_gate"]
set_output_delay -max 1.0 [get_ports " nand_gate"]
set_output_delay -max 1.0 [get_ports " nor_gate”]
set_output_delay -max 1.0 [get_ports " xor_gate"]

Experiment 5
Flip Flops
Aim: To compile and to simulate the Verilog code for the common flip-flops, and then to
Design Files: The main design modules and the respective test bench modules are given as
follows, in the order of – D, SR, T, JK and MS (The full forms for the names are: Data, Set
Reset, Toggle, Jack Kilby and Master Slave). The compiler directives are not used in these
modules, as the primitives are not used in the design modules, and the timing is specified in the
test bench modules.
a) D FLIP-FLOP
D Q
RESET D Q Q_BAR
D 1 X 0 1
CLK
0 0 0 1
FLIP-FLOP 0 1 1 0
RST QBAR
Verilog Code:
module dff(d,clk,q,q_bar,rst);
input clk,d,rst;
output q,q_bar;
reg q;
always @(posedge clk)
begin
if(rst==1)
q<=0;
else
q<=d;
end
assign q_bar=~q;
endmodule
Test Bench:
module dff_test;
reg d,clk,rst;
wire q,q_bar;
dff dff1(d,clk,q,q_bar,rst);
initial
begin
clk=1;rst=1;
d=0;
#100;rst=0;d=0;
#100;d=1;
#1000 $stop;
end
always #25 clk=~clk;
endmodule

Waveform:

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_clock_uncertainty 1.0 [get_ports "clk"]
set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "d"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "q_bar"] -clock [get_clocks "clk"]
b) SR FLIP-FLOP
Logic symbol: On positive edge of the CLK

Inputs Outputs
S Q S R Q Q_BAR
0 0 Previous state
S-R
CLK 0 1 0 1
1 0 1 0
FLIP-FLOP
R QBAR X
1 1
(Indeterminate state)
Verilog Code:
module srff(clk,s,r,q,q_bar);
input clk,s,r;
output q,q_bar;
reg q,q_bar;

always@(posedge clk)
begin
if(s==0 & r==0)
begin
q<=q;q_bar<=~q;
end
if(s==0 & r==1)
begin
q<=0;q_bar<=1;
end
if(s==1 & r==0)
begin
q<=1;q_bar<=0;
end
if(s==1 & r==1)
begin
q<=1'bz;q_bar<=1'bz;
end
end
endmodule
Testbench:
module srff_test;
reg clk,s,r;
wire q,q_bar;
srff srff1(clk,s,r,q,q_bar);
initial
begin
clk=1;
s=0;r=1; #100;
s=1;r=0; #100;
s=0;r=0; #100;
s=1;r=1;
#1000 $stop;
end
always
#25 clk=~clk;
endmodule
Waveform:

set_input_delay -max 1.0 [get_ports "s"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "r"] -clock [get_clocks "clk"]
c) T FLIP-FLOP
Logic symbol:
T
T Q
On positive edge of the CLK
FLIP-FLOP T Q Q_BAR
CLK Q_BAR
0 Previous state
1 Toggle
Verilog Code:
module tff(clk,T,q,q_bar,rst);
input clk,T,rst;
output q,q_bar;
reg q;
if(T)
begin
q<=~q;
end
else
begin
q<=1'b0;
end
assign q_bar=~q;
endmodule
Testbench:
module tff_test;
reg clk,T;
wire q,q_bar;
tff tff1(clk,T,q,q_bar);
initial
begin
clk=1;
T=0;
#100 T=1;
#100;T=0;
#100 T=1;
#1000 $stop;
end
endmodule

Waveform:

set_input_delay -max 1.0 [get_ports "T"] -clock [get_clocks "clk"]
d) JK FLIP-FLOP
Logic symbol:
On positive edge of the CLK
J Q
CLK J K Q Q_BAR
J-K
K Q_BAR
0 0 Previous state
FLIP-FLOP
0 1 0 1
1 0 1 0
1 1 Toggle
Verilog Code:
module jkff(clk,j,k,q,q_bar);
input clk,j,k;
output q,q_bar;
reg q=0;
reg q_bar;
begin
if(j==0 & k==0)
begin
q<=q;q_bar<=~q;
end
if(j==0 & k==1)
begin
q<=0;q_bar<=1;
end
if(j==1 & k==0)

begin
q<=1;q_bar<=0;
end
if(j==1 & k==1)
begin
q<=~q;q_bar<=~ q_bar;
end
end
endmodule
Testbench:
module jkff_test;
reg clk,j,k;
wire q,q_bar;
jkff jkff1(clk,j,k,q,q_bar);
initial
begin
clk=1;
j=0;k=1; #50;
j=0;k=0; #50;
j=1;k=0; #50;
j=1;k=1;
#400 $stop;
end

endmodule
Waveform:

set_input_delay -max 1.0 [get_ports "j"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "k"] -clock [get_clocks "clk"]

e) MS FLIP-FLOP
Verilog Code:
module ms_dff(d, clk, s_q, s_qbar);
output s_q, s_qbar;

input clk,d;
reg s_q, s_qbar ,m_q;
always @(clk)
begin
if (!clk)
begin
m_q <=d;
end
if (clk)
begin
s_q <= m_q;
s_qbar <= ~ m_q;
end
end
endmodule
Master Input Slave Output
Testbench:
module ms_dff_test;
reg clk,d;
wire s_q, s_qbar;
ms_dff ms1(d, clk, s_q, s_qbar);
initial
begin
clk = 1'b0;
d = 1'b0; #50
d = 1'b1;#50
d = 1'b0; #1000
$stop;
end

endmodule

Waveform:

set_input_delay -max 1.0 [get_ports "d"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "s_q"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "s_qbar"] -clock [get_clocks "clk"]

Experiment 6
Adders
Aim: To compile and to simulate the Verilog code for the serial and parallel adders, and then to
a) SERIAL ADDER
• Design a 4-bit serial adder. Addition will start with a control signal ‘Enable’, the 2
numbers would come serially to the adder. Output has to be given on register.
Logic symbol:
Verilog Code:
module serial_adder(clk,rst,en,x,y,D);
input clk,rst,en;
input x,y;
output [3:0]D;
reg [3:0]D;
reg carry;
always @(posedge rst or posedge clk)
begin
if(rst)
begin
D<=4'b0;
carry<=1'b0;
end
else if(en)
begin
D[0]<=D[1];
D[1]<=D[2];
D[2]<=D[3];
{carry,D[3]}<=x+y+carry;
end
end
endmodule

Testbench:
module serial_adder_test;
reg clk,rst,en,x,y;
wire [3:0]D;
serial_adder serial_adder1(clk,rst,en,x,y,D);
initial
begin
x=0;
y=0;
clk=1;rst=1;en=0;#50;
rst=0;en=1;
x=1;
y=1;#50;
x=0;
y=0;#50;
x=0;
y=1;#50;
x=1;
y=0;#1000
$stop;
end
endmodule
Waveform:

set_input_delay -max 1.0 [get_ports "en"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "x"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "y"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "D"] -clock [get_clocks "clk"]

b) PARALLEL ADDER
Logic symbol:
Verilog Code:
module parallel_adder(a,b,cin,result);
input [3:0]a,b;
input cin;
output [4:0] result;
assign result =a+b+cin;
endmodule
Testbench:
module parallel_adder_test;
reg [3:0]a,b;
reg cin;
wire [4:0] result;
parallel_adder parallel_adder1(a,b,cin, result);
initial
begin
a=4'b0000;
b=4'b0000;
cin=0;
#100;
a=4'b0010;
b=4'b0001;
#100;
a=4'b0010;
b=4'b0010;
#1000 $stop;
end
endmodule
Waveform:

set_input_delay -max 1.0 [get_ports "b"]
set_input_delay -max 1.0 [get_ports "cin"]
set_output_delay -max 1.0 [get_ports " result "]

Experiment 7
Counters
Aim: To write a Verilog code for Synchronous Counter and Synthesize and verify the
code with gate level simulation.
a) SYNCHRONOUS COUNTER
Logic symbol:
Verilog Code:
//4-bit Synchronous counter
module counter(clk,rst,q);
input clk,rst;
output reg [3:0] q;
always@(posedge clk or negedge rst)
begin
if(!rst)
q<=0;
else
q<=q+1;
end
endmodule
Testbench:
module counter_test;
reg clk, rst;
wire [3:0] q;
counter counter1(clk,rst, q);
initial
begin
clk=0;rst=1;#50;
rst=0;#50;
rst=1;#1000 $stop;
end
endmodule

Waveform:
Constraints file for Synthesis: Constraints_sc.g

b) ASYNCHRONOUS COUNTER
Logic symbol:
Verilog Code:
// Asynchronous 4-bit Counter
module async_count(clk,rst,q);
input clk,rst;
output [3:0]q;
reg q0,q1,q2,q3;
always @(posedge clk or posedge rst)
begin
if(rst)
q0<=0;
else
q0<=~q0;
end
always @(negedge q0 or posedge rst)

begin
if(rst)

q1<=0;
else
q1<=~q1;
end
begin
if(rst)
q2<=0;
else
q2<=~q2;
end
begin
if(rst)
q3<=0;
else
q3<=~q3;
end
assign q={q3,q2,q1,q0};
endmodule
Testbench:
module async_count_test;
reg clk, rst;
wire [3:0]q;
async_count async_count1(clk,rst,q);
initial
begin
clk=0;rst=1;#50;
rst=0;#1000
$stop;
end
endmodule
Waveform:

create_clock -name pulse -period 10 -waveform {0 5} [get_ports "clk"]

EXPERIMENT 8
SUCCESSIVE APPROXIMATION REGISTER
Aim: To compile and to simulate the Verilog code for the successive approximation
register.
Specifications:
Design a 4-bit SAR logic for 4-bit ADC, use start of conversion & end of
conversion signals.
Logic symbol:
Verilog Code:
module SAR_Counter(
input clk,
input rst,
input comparator_in,
input SOC,
output EOC,
output [3:0] Q
);
reg[3:0] q_temp; // DAC o/p register
reg [2:0] q_cntr; // cycle counter
reg en,EOC_temp;
// Enable Control
always@(posedge clk or posedge rst)
begin
if (rst)
en <= 1'b0;
else if (EOC_temp)
en <= 1'b0;
else if (SOC)
en <= 1'b1;
end
// End of conversion Control

begin
if (rst)
EOC_temp <= 1'b0;
else if (q_cntr==3'b111)
EOC_temp <= 1'b1;
else
EOC_temp <= 1'b0;
end
assign EOC = EOC_temp;
// Cycle Counter
begin

if (rst)
q_cntr <= 3'b0;
else if (EOC_temp)
q_cntr <= 3'b0;
else if (en)
q_cntr <= q_cntr + 1;
end
assign Q = q_temp;
// SAR logic
begin
if (rst)
q_temp <= 4'b1000;
else if (en)
begin
case (q_cntr)
3'b001 :
begin
if(comparator_in) // Check MSB bit
q_temp[3] <= q_temp[3];
else
q_temp[3] <= 1'b0;
end
3'b010 : begin
q_temp[2] <= 1'b1; // Set 2nd MSB bit
end
3'b011 : begin
if(comparator_in) // Check 2nd MSB bit
else
q_temp[2] <= 1'b0;
end
3'b100 : begin
q_temp[1] <= 1'b1; // Set 3rd MSB bit
end
3'b101 : begin
if(comparator_in) // Check 3rd MSB bit
else
q_temp[1] <= 1'b0;
end
3'b110 : begin
q_temp[0] <= 1'b1; // Set LSB bit
end
3'b111 : begin
if(comparator_in) // Check LSB bit
else
q_temp[0] <= 1'b0;
end
default: begin

q_temp <= q_temp;
end
endcase
end
else
q_temp <= 4'b1000;
end
endmodule
Testbench:
module SAR_t;
reg clk = 1'b0;
reg rst = 1'b0;
reg comparator_in = 1'b0;
reg SOC = 1'b0;
wire EOC;
wire [3:0] Q;
SAR_Counter SAR_Counter1 (clk, rst,comparator_in,SOC,EOC,Q);
initial begin
#50;
rst = 1'b1; #50;
rst = 1'b0;comparator_in = 1'b1;
#50; SOC = 1'b1;
#50; SOC = 1'b0;
#800;comparator_in = 1'b0;
#1000 $stop;
end
endmodule
Waveform:

create_clock -name pulse -period 10 -waveform {0 5} [get_ports "pulse"]
set_clock_transition -rise 0.1 [get_clocks "pulse"]
set_clock_transition -fall 0.1 [get_clocks "pulse"]
set_clock_uncertainty 1.0 [get_ports "pulse"]
set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "pulse"]
set_input_delay -max 1.0 [get_ports " comparator_in"] -clock [get_clocks "pulse"]
set_input_delay -max 1.0 [get_ports " SOC"] -clock [get_clocks "pulse"]
set_output_delay -max 1.0 [get_ports " EOC"] -clock [get_clocks "pulse"]
set_output_delay -max 1.0 [get_ports " Q"] -clock [get_clocks "pulse"]

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VLSI Lab Manual

FOR VII SEMESTER E&C ENGG., AS PER VTU SYLLABUS

Department of Electronics and Communication Engineering

PROCEDURES FOR DIGITAL DESIGN Page No.

PROCEDURES FOR ANALOG DESIGN

Department of Electronics & Communication, K.I.T, Tiptur 1

(Wherever necessary Cadence/Synopsis/Menta Graphics tools must be used)

Asic-Digital Design Flow

Analog Design Flow

Department of Electronics & Communication, K.I.T, Tiptur 2

* Appropriate specification should be given.

Department of Electronics & Communication, K.I.T, Tiptur 3

1. To provide an introduction to the fundamentals of Computer-Aided Design tools

1. Establish comprehensive understanding of the various phases of CAD for digital

Prerequisites: CMOS VLSI Design, Logic Design, Digital Electronics

Department of Electronics & Communication, K.I.T, Tiptur 4

rtl synthesis lib

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Department of Electronics & Communication, K.I.T, Tiptur 6

Department of Electronics & Communication, K.I.T, Tiptur 7

5. Click ‘OK’in the ‘nclaunch: Open Design Directory’ window.

Department of Electronics & Communication, K.I.T, Tiptur 8

Department of Electronics & Communication, K.I.T, Tiptur 9

Department of Electronics & Communication, K.I.T, Tiptur 10

Let us see the usage and purpose of each command.

• read_sdc<sdc file name with path>

➢ Include all the above commands in the script file.

Timing Constraints or SDC file:

Let us see the usage and purpose of each command.

Department of Electronics & Communication, K.I.T, Tiptur 12

Department of Electronics & Communication, K.I.T, Tiptur 13

Constraints file for Synthesis:

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Constraints file for Synthesis:

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Constraints file for Synthesis:

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A B And_gate Or_gate Xor_gate Nand_gate Nor_gate

// Basic Gates Design

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Constraints file for Synthesis:

set_input_delay -max 1.0 [get_ports "a"]

Department of Electronics & Communication, K.I.T, Tiptur 18

Department of Electronics & Communication, K.I.T, Tiptur 19

Constraints file for Synthesis:

Logic symbol: On positive edge of the CLK

Department of Electronics & Communication, K.I.T, Tiptur 20

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Constraints file for Synthesis:

Department of Electronics & Communication, K.I.T, Tiptur 23

always #25 clk=~clk;

Constraints file for Synthesis:

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module ms_dff(d, clk, s_q, s_qbar);

output s_q, s_qbar;

ms_dff ms1(d, clk, s_q, s_qbar);

always #25 clk=~clk;

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Constraints file for Synthesis:

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Constraints file for Synthesis:

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