05 - The Buck Regulator, Part 3 - Power Supply Design Tutorial Section 2-3 PDF

14/4/2018 The Buck Regulator, Part 3 – Power Supply Design Tutorial Section 2-3
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The Buck Regulator, Part 3 – Power Supply Design Tutorial

Section 2-3
This is the nal part of three sessions dedicated to the buck regulator in great detail. Though not strictly necessary, I
strongly suggest that you read sections 2-1 and 2-2, where I discussed the input capacitors, the output inductor, and the
output capacitors before watching this section, which is dedicated to the various types of power switches used in bucks.
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Section 2-3 Agenda (http://wikipedia.org/wiki/HTTP_cookie)
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Control switch selection

Various types of loss
Packages
“Bootstrap” charge pump circuits
Low-side switch selection
Diodes – PN vs. Schottky
Synchronous MOSFETs – losses and packaging
Using power switches in parallel
Clock synchronization and out-of-phase operation
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This is the nal part for the buck converter where we’ll look, again, in some detail atcontent/uploads/2018/03/PIDWebinar2-
the control switch, or high side switch. The types of discrete switch are almost3-16_Power-Switches-In-Parallel-
exclusively MOSFETs. For low side switches, we’ll discuss diodes, usually used at MOSFET.jpg)
high duty cycles and lower currents or synchronous MOSFETs, which are exclusively
nMOSFET type and these are used for lower duty cycles and or higher output currents. Then we’ll examine the pros and
cons of placing MOSFETs in parallel and discuss why diodes are not used in parallel and we’ll look at the clocking of
switchers and how this can bene t both the time domain and frequency domain characteristics of switchers.
De nition of Key Terms

Nominal input voltage, VIN, ex. 13.8V for passenger vehicles
Maximum input voltage, VIN-MAX, ex. 42V for a clamped load dump
Minimum input voltage, VIN-MIN, ex. 4.5V for start-stop
Maximum output current / maximum load, IO-MAX / RO-MIN
Nominal Duty Cycle, DNOM, when input voltage is nominal
Maximum duty cycle, DMAX, when input voltage is at a minimum
Minimum duty cycle, DMIN, when input voltage is at a maximum
Multi-layer ceramic capacitors, MLCCs
DC resistance, DCR, of inductors
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Equivalent series resistance, ESR, of capacitors
Converter or regulator: switching IC with at least one internal power MOSFET

Controller: switching IC with external power MOSFET(s)
Module: switching control, power switches, inductor and passives in one package
MOSFETs, BJTs and Diodes

I’ve listed bipolar transistors here, but in practice they are a dying breed. I haven’t seen a buck design that used a discrete
BJT in a long time. The vast majority of discrete control switches are nMOSFETs, followed by pMOSFETs.
The control MOSFET in a buck regulator will almost always dissipate the most power of any component on the PCV and
you can expect it to be the hottest part of the circuit. For a general rule by the way, I try to keep the case temperatures on
my power MOSFETS and power diodes under around 100 degrees C. Keep in mind that a case temperature of 100 degrees
C means that the actual silicon is hotter.
It should come of no surprise that keeping a power fed cool is the main objective when selecting and placing it. One last
thing before I move on to the next slide. Take a good look at the transients on each edge of the switching node wave form.
These transients, which I call PARD noise or ringing can be a serious EMC headache and part ve of this seminar will focus
on reducing them. They start with these fast edges and if not treated can spread everywhere.
Control FET Design Philosophy
Selecting the maximum drain voltage is pretty straightforward. Take the maximum input voltage, which is applied from
across the channel when the MOSFET is off and add about 20%. That 20% helps with transients like the spikes we saw on
the edges on the previous slide’s wave form as well as temporary overloads or input oscillations.
Now, I never pay much attention to the maximum drain current specs of power MOSFETs, because they’re speci ed in such
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way or ways that never match the actual operating conditions. You might see for example a maximum drain current of
200 amps and that’s continuous, not pulsed. Sounds amazing, right, but that’s with a temperature of 25 °C. Even if that
MOSFET had an RDS(on) at one milli ohm based on I squared R, that would be 40 watts of power dissipation. Modern
packages like the Power SO-8, my current favorite, can get their thermal resistance down to around 50 degrees C per watt
if you connect enough copper and thermo via to their exposed power pads or tabs, but if you’re doing some mental math
and thinking that 40 watts times 50 °C is to a 2000 degree rise, then I agree. At 200 amps such a MOSFET would pretty
much vaporize. Now, I hadn’t updated this slide in about a year and since then a new package that I like quite a bit has come
out. The three by three millimeter QFN style Power 3×3.
Power 3×3 isn’t the real name. Every MOSFET maker has their own name, but the good news is that they’re all footprint
compatible. It’s like a mini Power SO-8 with a thermal resistance that’s nearly as good, but occupies about half the area. To
get the best performance out of this kinda package place at least four thermo vias directly unto the drain, which is also the
power pad.
Selecting Heatsinks for Power Packages
TO-220 is probably the only through hole package you’re likely to use with a buck regulator. The much bigger TO-247 is
really too big and in most cases has too much lead inductance for buck regulators operating at 50 kilohertz and above. Like
the thermal expressions I discussed at the beginning of section 1-1, this equation for heat sink thermal resistance is rst
order and not very accurate. As usual, lab testing is key for thermal management. One note about radiated emissions and
heat sinks. The more area the switching node is connected to, the more it will radiate EMI.
The drain of the low side MOSFET is connected to the switch node, so whenever you use that 220 package, I suggest
isolating it from the heat sink with a thermally conductive isolating pad. These are available as stickers. Another possibility
is to use the TO-220 FP or full pack, which has an electrically isolated drain tab.
Control FET: Conduction Loss
I like to split the losses in the control MOSFET into three main parts. Of these conduction loss is easy to calculate and it
would be accurate if it wasn’t so dif cult to determine the two RDS(on) of the MOSFET. The trouble with RDS(on) comes
from many things, but the main ones are one, RDS(on) changes with the gate voltage. This is very important when pairing a
control IC to the external MOSFET. Most modern control ICs for just about any switching typology include MOSFET gate
drivers, but in most cases the gate drive voltage is xed. It’s absolutely critical to use a MOSFET that has the RDS(on) and
other characteristics speci ed for your gate drive voltage. It’s okay to have higher gate voltage.
For example, a six volt gate drive for a Logic Level MOSFET speci ed at 4.5 volts is just ne. But if you paired a standard
drive MOSFET, which needs 10 volts from gate to source with only six volts of gate drive, the channel wouldn’t turn on all
the way. The RDS(on) will be much higher and the MOSFET would most likely burn up. Two, RDS(on) changes in proportion
to temperature. If a maximum value over temperature isn’t given in a data sheet you can estimate it by multiplying the
typical 25 °C value by 1.3
Control FET: Switching Loss
Switching loss occurs for two main reasons. One, the rise and fall times of voltage and current are not instantaneous. A
good compromise between ef ciency and EMC is usually a rise time or fall time in the range of 20 to 50 nanoseconds.
During the overlap time where there is current owing through the channel and voltage across it and voltage times current
is power. Two, the parasitic of the MOSFET has to be charged and discharged each time it’s turned on or off and takes
energy. Energy divided by time is once again power.
This equation for switching loss is not accurate to actual switching losses, but it does serve to put in a spreadsheet and
compare the relative losses of MOSFETs from the same manufacturer. The reason I say this is that different manufacturers
specify their devices with different conditions making it quite dif cult to say that two devices from two different suppliers
even with similar characteristics on paper are really the same. Lab testing is once again still the best way to nd the best
power MOSFETs. Note that switching loss is proportional to switching frequency. Higher frequency means more current
and voltage overlaps and more parasitic capacitor charges and discharges per unit time. This is the main reason that lower
frequency circuits are more ef cient.
Control FET: Gate Charging Loss
Gate charging loss tends to be quite small compared to conduction losses and switching loss, but there’s a key difference. It
occurs not in the MOSFET itself, but in the gate driver and that’s usually the control IC. More and more control ICs are
available in packages with exposed power tabs or pads but there’s still many older controllers that are still excellent parts.
However, their SOIC or TSSOP type packages have thermal resistances on the order of 100 °C per watt. A seemingly small
amount of dissipation driving the gates of big FETS can overheat the controller.
PFETs don’t need the so called boot strap circuit shown here, but NFETS are far more common and the boot strap a type of
charge pump, charges CBOOT up to VCC when the switching node connected to the source of the FET is at ground. Diode
DBOOT prevents the capacitor CBOOT from discharging when the source of the control FET ies up to VN and CBOOT
therefore serves as a charge reservoir. I don’t show it here, but the actual dissipation in most control ICs is actually equal to
the input voltage multiplied by the total gate charge and the switching frequency.
That’s because most controllers have an internal linear regulator to generate VCC from VN. The same current needed to
drive the FET or FETs also power dropping VN to VCC. IN conclusion, when you do your temperature testing, make sure to
monitor your control IC as well as those power switches.
Totaling FET Losses and Checking TJ
In modern MOSFET packaging bigger is not always better, but more copper area and more thermal vias are great. Both
have that inverse exponential drop off. Meaning that twice the copper or a number of vias is far better than one, but 20
times the copper or the number of vias provides diminishing returns. Thermal vias need to be directly under the thermal
pad, the drain of the MOSFET in order to work best. That means talking to your PCB manufacturer and your contract
manufacturer to nd the best compromises of cost and manufacturability. My personal favorite size is a hole measuring
250 microns, that’s one quarter of a millimeter. With an outer via diameter of 500 microns or half a millimeter.
And I like to space them at least one millimeter apart, but I was recently surprised by a surcharge on the design that needed
a minimum via diameter of 0.7 millimeters in order to use the 0.25 millimeter drill bit. In any case, holes of 250 microns or
below are less likely to wick or less likely to drain away the solder on the thermal pad during assembly. This is essential
since any voids, meaning air gaps between a thermal pad and a PCB will make the thermal resistance of the MOSFET rise.
Sometimes dramatically.
The Recirculating Diode
In general, I use diodes for circuits that have duty cycles of 50% most of the time. Meaning that the control FET carries the
current during the majority of the switching cycle. Also, I tend to use diodes from output currents of three amps and below.
Although some bigger diodes use modern low inductance and low thermal resistance packaging that can handle ve amps
or more.
Most design guides will recommend silicon Schottky diodes, but they don’t always explain why. PN diodes, even ultra-fast
recti ers have declared the electrons and the holes out of the barrier regions when they turn on and off. That’s the so
called forward recovery loss or reverse recovery loss. Schottky diodes don’t have this problem, but Schottkys do have
junction capacitance so they’re not perfect. Also, at junction temperatures above about 100 °C or so, the reverse current
leakage of Schottky diodes starts to increase quite quickly. Exponentially in fact. In general, I use Schottky diodes without
hesitation up to 100 volts. Silicon Schottkys are available up to 200 volts, but these I evaluate on a case by case basis.
Recirculating Diode Design Equations
For reverse voltage capability, I use the same criterion for diodes as I do for MOSFETs. The maximum the diode sees is VN
max, so I add a 20% margin to this to handle transients and overloads. Now I said that Schottky diodes to have parasitic
capacitance, so there is the switching loss component, but it’s quite small compared to the conduction loss and I don’t
bother calculating it. Instead, I start by calculating the average height of the trapezoid wave of current pulses that the diode
must handle. Then I pick a device with a continuous forward current rating that is about 10% higher than ID max.
Recirculating Diode Power Losses
Diode loss is assumed to be all forward conduction loss. Using a simple expression shown here. As usual, the complex part
of thermal management is selecting the appropriate package, which is based on thermal resistance and PCB design. Some
of the newer offerings, such as eSMP and the Power DI5 not only have better thermal resistances in footprint similar to the
SOD-123 or SMP respectively, but also have lower inductance.
You saw the trapezoid wave of current with its sharp edges, so lower inductance is wonderful for EMC. Minimization of
inductance is the reason I don’t suggest any Ldi/dt packages on this slide.
Synchronous FET, “Low-Side” FET
Two main factors in uence the decision to use a synchronous MOSFET instead of a diode. Duty cycle and output current.
When duty cycle is low, let’s say 25% or below, then the low side switch carries the current during most of the switching
cycle. That improves the gains and ef ciency you would get by using a MOSFET instead of a diode. Remember that the
diode always drops around 0.5 volts whereas the MOSFET drop could be less than 50 millivolts. When output current is
higher than three amps or so and de nitely when it’s above ve amps is when the synchronous MOSFET becomes really
necessary. Because few diodes can handle more than 1.5 watts of dissipation. Let alone 2.5 watts or more and that’s what
you get for currents of three amps, ve amps or above.
There are some exceptions in other typologies like the yback converter where a big diode and a heat sink are employed.
For the buck though dissipating more than about one watt in the diode makes me consider a MOSFET instead.
Duty Cycle Equations, Sync Buck

If you watched the rst two sessions of this seminar, you saw that practical duty cycles are always higher than ideal duty
cycles, because some voltage is always dropped or lost across each power path element that carries current. When both
switches are MOSFETs it’s usually not worth trying to calculate what their voltage drops are. Especially because RDS(on) is
so dif cult to predict. Plus, there are voltage drops across the DC resistance of the power inductor, drops in the PC
retraces across any input lters. In short, one way to avoid all these little calculations is to estimate the power ef ciency
and then divide the ideal duty cycle by that ef ciency.
The buck is so well characterized that there’s often a similar circuit with an ef ciency to look at. Even if there isn’t anything
close I usually start with around 95% ef ciency.
Sync FET Design Philosophy
The maximum drain voltage limit is the same as for the control FET. Just add around 20% for a safety margin to the
maximum input voltage. Also, those drain current limits you see in the data sheets are still for unrealistic conditions, so
keep ignoring them. These are exactly the same packages as I suggested for the control FET, but as we’ll see in the next few
slides, the silicon inside them is selected based on different pros and cons.
Synchronous FET: Conduction Loss
The big loss term that’s missing here is the switching loss. The reason that’s absent is that the body diode of the
synchronous FET turns on before the channel does. That’s done on purpose. To prevent having the top and bottom
MOSFETs on simultaneously. When this happens, it’s called shoot through.
When huge amounts of current go shooting through both FETs, because the source is effectively short circuited and usually
one of both MOSFETs blows up, often taking a bunch of other components with them. In any case, when the body diode
turns on, the drain voltage is reduced from VN down to the body diode forward voltage. Usually about one volt. That makes
switching loss negligible. For this reason, FETs that turn on more slowly, but have lower RDS(on) are preferred for use as
synchronous switches and you’ll often see a line in the typical application section of their data sheet front pages, saying,
“Optimized for synchronous recti cation.” Now, gate charging loss is still the smaller term by far, but there are two reasons
why you should even pay more attention here than you do for the gate charge of the control FET. Number one, since the
sync FET seems to be a bigger device in order to have lower RDS(on) it has higher gate charge and that means higher
average current to charge and discharge that gate capacitance.
Two, again, I’ve written VCC in the loss term and that voltage is usually the output of the internal linear regulator of the
control IC, but that same charging current ows inside the control IC from VN, the input to the internal linear regulator to
VCC. That means that effectively you should replace VCC with VN. Meaning the power input voltage for most cases in this
equation. That can add up to hundreds of milli watts and hundreds of milli watts with high thermal resistance control IC
packages like SOIC or TSSOP can mean overheating.
Totaling FET Losses and Checking TJ
In the very rst session in this seminar, I mentioned that the equation for temperature rise in electronic components is very
simple, but the terms of the equation can be very dif cult to predict.
MOSFET cooling is especially tough, because the loss term equations aren’t very accurate and the thermal resistance
values aren’t very accurate either. Trial, error and experience are very important for this part of switching converter design.
This image is from the PCB layout section of the seminar and it shows how the massive copper attached to a hot …
Temperature hot node can be increased without increasing the overall area. That’s important due to radiated EMI, but
more on that in part four, the PCB layout section.
Power Switches In Parallel: MOSFET
As a general rule, if I predict that a power MOSFET is going to dissipate more than about two watts of power or if I measure
the case temperature of a MOSFET in the lab and get 120 °C or more, then I consider either a better MOSFET, which means
a device with lower conduction loss and if appropriate lower switching loss. Better MOSFETs usually cost more money
though and that’s ne as long as the budget allows, but if PCB area is available, then I also consider putting two or more
devices in parallel. This assumes that(http://wikipedia.org/wiki/HTTP_cookie)
we’re dealing with service mount parts that can’t make full use of a heat sink. Now the
TO-220 is one of the few through hole packages I still consider for bucks, but its unavoidable, large lead inductance means
that I don’t often use it. The good use for parallel MOSFETs is that problematic, that RDS(on) rises with temperature is
actually bene cial in this case. Consider the diagram on the right. Q1 and Q2 are both the same part number and they’re
both driven with the same voltage, which is guaranteed to be above their gate turn on threshold.
Their channels are fairly enhanced. We also assume that they have the same amount of copper area connected to their
drain tabs and the same number of thermo vias and et cetera, so that their thermal resistances are as equal as possible.
When we force a constant current [inaudible 00:16:57] through them, the following sequence occurs. One, [inaudible
00:17:05] splits between the two devices and since they are real parts, whichever one’s RDS(on) is slightly lower takes
more current. Let’s assume that’s Q1. Two, because Q1 is drawing more current, it heats up more than Q2. Three, due to
the positive temperature coef cient Q1’s RDS(on) increases faster and soon equals the RDS(on) of Q2. Four, the current in
both FETs is now equal. Should Q2 begin to draw more current than Q1, its RDS(on) will increase in proportion and current
will once again balance.
Power Switches In Parallel: Diode
Paralleling diodes is another matter entirely and I don’t recommend it at all. Anyone who has worked with high power LEDs
has seen the same problem. It has to do with the negative temperature coef cient of the forward voltage of any diode. I did
a lot of testing of high powered LEDs, none of which shared current very well I’ve places in parallel. Although for this
experiment I use two PN recti ers in a DO-201 package, a big through hole package that can handle three amps
continuously. Whichever diode has a lower forward voltage due to tolerance simply takes more current. That’s D1 in this
case, but instead of balancing D1 actually draws more and more current, because it’s forward voltage drops hat heats up.
This static image doesn’t show it, but Id2 was dropping slowly while Id1 was rising. In practice, an equilibrium would
eventually establish itself, because eventually the higher forward current of Id1 would make its forward voltage rise, but
the two diodes would never share a current properly.
Note that in practice you can nd some duo-diodes where using a same sub permits better current sharing. That’s because
they have very close of the same temperature. However, with discrete diodes, putting them in parallel is generally a very
bad idea.
Multiphase and Phase Shifting

Multiphase and Phase Shifting are two techniques that improve electrical noise, power ef ciency and thermal
management. Either for systems with very high power or for systems where multiple buck regulators connect to the same
input voltage. Of course, this is also true when multiple switching regulators of any typology connect to the same input
source, but when lots of switchers coexist in this way they’re almost always bucks.
Normally, buck converters draw heavy, trapezoidal current pulses with high RMS values from their input supplies. When
two or more bucks, or actually when two or more switchers of any typology draw their inputs from the same rail, it always
helps to synchronize their switching frequencies and then run them out of phase.
For two switchers 180 degrees out of phase. The RMS value of the input current drops considerably. Mainly because one
switcher draws up holes with a height of X amps, then the other one draws up holes of Y amps. If, they both drew their input
current simultaneously, the total pulse would be X plus Y amps. Remember that large peak to peak deltas increase the RMS
value of any wave form. There’s a second bene t to out of phase switching, which is that the fundamental noise frequency
doubles. That is to say two bucks switching at 200 kilohertz each would draw an input current at 400 kilohertz if they were
synchronized and run 180 degrees out of phase. Sometimes this isn’t so great, because it can push the fundamental
frequency into a band with a lower conducted EMI limit, but most of the time the EMI limit stays the same and a higher
switching frequency can be af liated with less inductance and capacitance. That means smaller, lighter and cheaper input
lters for inductance and capacitance.
Switching Frequency Synchronization
When two or more switching regulators work on the same input rail, the possibility of beat frequencies arises. Beat
frequencies occur more often when the two signals are close to one another in frequency, but are not synchronized. The
buck is a prime example, but re backs and buck-boosts are the same thing. As my schematic shows, buck LED drivers in a
big array can cause big frequencies, which can show up with a sum of too similar, but not synchronized signals or at the
difference of those two signals. My 500 kilohertz example here would likely generate big frequencies at around one
megahertz and also at around one kilohertz or so and both cold be problems for conducted EMI. Not all switchers can be
frequency synchronized. Some devices use clocks, but do not have an input for an external clock. Many others, especially in
LED driving use hysteretic or quadra hysteretic control and can’t ever be synchronized.
In such cases it’s important to watch the input voltage in the frequency domain. Usually with a spectrum analyzer. More
aggressive input lters, such as the inductor shown here are one way to get rid of beat frequency problems, but they cost
money and do take up PCB area. Clock synchronization eliminates beat frequencies so I recommend it whenever possible.
In all cases where two or more switching converters connect to the same input rail.
Next Up: Section 3-1 – PCB Layout for EMC

Section 3-1 is the beginning of the dedicated portion on PCB layout for switching converters. We’ll begin by looking at
inductors and how they can either work for us or against us, then move to the ground connection as a practical concept.
From there, signals as currents will be explored. Followed by an experiment designed to explain the differences between
resistance and impedance. The nal parts of section 3-1 will be exploring how electrical noise gets to its victim from the
source and then a look at shielding from magnetic elds and from magnetic elds.
Link to next section: 3-1 PCB Layout for EMC (https://www.powerelectronicsnews.com/problems-solutions/pcb-

layout-for-emc-power-supply-design-tutorial-section-3-1)
Link to previous section: 2-2 Buck Converter, Part 2 (https://www.powerelectronicsnews.com/problems-solutions/the-

buck-regulator-continued-power-supply-design-tutorial-part-2-2)

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05 - The Buck Regulator, Part 3 - Power Supply Design Tutorial Section 2-3 PDF

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Home (https://www.powerelectronicsnews.com) / Power Supplies & Energy Storage (/category/power-supplies-problems-solutions)

The Buck Regulator, Part 3 – Power Supply Design Tutorial

Control switch selection

De nition of Key Terms

Converter or regulator: switching IC with at least one internal power MOSFET

MOSFETs, BJTs and Diodes

Control FET Design Philosophy

Selecting Heatsinks for Power Packages

Control FET: Conduction Loss

Control FET: Switching Loss

Control FET: Gate Charging Loss

Totaling FET Losses and Checking TJ

The Recirculating Diode

Recirculating Diode Design Equations

Recirculating Diode Power Losses

Synchronous FET, “Low-Side” FET

Duty Cycle Equations, Sync Buck

Sync FET Design Philosophy

Synchronous FET: Conduction Loss

Totaling FET Losses and Checking TJ

Power Switches In Parallel: MOSFET

Power Switches In Parallel: Diode

Multiphase and Phase Shifting

Switching Frequency Synchronization

Next Up: Section 3-1 – PCB Layout for EMC

Link to next section: 3-1 PCB Layout for EMC (https://www.powerelectronicsnews.com/problems-solutions/pcb-

Link to previous section: 2-2 Buck Converter, Part 2 (https://www.powerelectronicsnews.com/problems-solutions/the-

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