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NV3047D Datasheet
720x544 System-On-Chip Driver
For 480RGB x 272 TFT LCD
Version 1.0
Apr, 2018
NV3047D—480(RGB) x272 TFT LCD Single-Chip Driver
1. General Description
NV3047D offers all-in-one chip solution of 480RGBx272 for color TFT-LCD
panel. This chip incorporated with digital timing generator, source and gate driver,
power supply circuit, PWM control circuit and embedded serial communication
interface for function setting. The source output support real 8-bit resolution and
256-gray scale with small output deviation are designed to support higher color
resolution. The power supply circuit incorporated with step-up circuit, regulators
and operational amplifiers to generate power supply voltages to drive TFT LCD.
2. Features
Display resolution options:
480(RGB) (H) X 272 (V)
3. Pad arrangement
3.1. Output Bump Dimension
MM
MM
YY
UU
GGGGGDD
11 9 7 5 3 1
DUMMY
G
1
DGND
2
DUMMY
3
DUMMY
4
DGND
………
VPP
6
VPP
7
VPP
8
VPP
9
VPP
0
1
VPP
1
1
DGND
2
1
DUMMY
3
1
DUMMY
4
1
DUMMY
5
1
DUMMY
6
1
DGND
7
1
GVDD
8
1
GVDD
9
1
GVDD
0
2
GVDD
1
2
GVDD
2
2
GVDD
3
2
GVCL
4
2
GVCL
5
2
GVCL
6
2
GVCL
7
2
GVCL
8
2
GVCL
9
2
VCOM
0
3
VCOM
1
3
VCOM
2
3
VCOM
3
3
VCOM
4
3
VCOM
5
3
DGND
6
3
DUMMY
7
3
DUMMY
8
3
DGND
9
3
Pad Location: Pad center
DUMMY
0
4
DUMMY
1
4
DUMMY
2
4
Coordinate Origin: Chip center
DUMMY
3
4
DUMMY
4
4
DUMMY
5
4
DGND
6
4
DGND
7
4
DGND
8
4
DGND
9
4
DGND
0
5
DGND
1
5
DGND
2
5
DGND
3
5
VCC
4
5
VCC
5
5
VCC
6
5
VCC
7
5
VCC
8
5
VCC
9
5
VDDI
0
6
VDDI
1
6
VDDI
2
6
VDDI
3
6
VDDI
4
6
GGGGG
GGGGGGGGGGUUUUUU 3 1 9 7 5 3
54 54 53 53 53 53
VDDI
5
6
VDD
6
6
DDDDDDDDDDMMMMMM
NNNNNNNNNNMMMMMM
YYYYYY
7
6
VDD
8
6
VDD
9
6
VDD
0
7
VDD
1
7
VDD
2
7
VDD
3
7
DUMMY
7 77 77 7
4
7
VSYNC
5
7
VSYNC
6
7
HSYNC
7
7
HSYNC
8
7
DCLK
9
7
DCLK
0
8
VDPOL
1
8
VDPOL
2
8
………
HDPOL
3
8
HDPOL
4
8
DCLKPOL
5
8
DCLKPOL
6
8
SBGR
7
8
SBGR
8
8
9 DE
8
DE
0
9
DUMMY
1
9
DUMMY
2
9
DUMMY
3
9
DUMMY
4
9
PARA_SERI
5
9
PARA_SERI
6
9
EXTC
7
9
EXTC
8
9
HDIR
9
9
HDIR
0
0
1
VDIR
1
0
1
VDIR
2
0
1
TEST_IN3
3
0
1
TEST_IN3
4
0
1
TEST_IN4
5
0
1
TEST_IN4
6
0
1
CS
7
0
1
CS
8
0
1
SDA
9
0
1
SDA
0
1
1
SCL
1
1
1
SCL
2
1
1
DISP
3
1
1
DISP
4
1
1
TEST_IN5
5
1
1
TEST_IN5
6
1
1
RGB
7
1
1
RGB
8
1
1
SYNC
9
1
1
SYNC
0
2
1
DUMMY
1
2
1
DUMMY
2
2
1
DUMMY
3
2
1
DUMMY
Y
4
2
1
DGND
5
2
1
DR7
6
2
1
DR7
7
2
1
DR6
8
2
1
DR6
9
2
1
DR5
0
3
1
DR5
1
3
1
DR4
2
3
1
DR4
3
3
1
DR3
4
3
1
DR3
5
3
1
DR2
6
3
1
DR2
7
3
1
DR1
8
3
1
DR1
9
3
1
DR0
0
4
1
DR0
X
1
4
1
DG7
2
4
1
DG7
3
4
1
DG6
4
4
1
DG6
5
4
1
DG5
6
4
1
DG5
7
4
1
DG4
8
4
1
DG4
9
4
1
DG3
0
5
1
DG3
1
5
1
DG2
2
5
1
DG2
3
5
1
DG1
4
5
1
DG1
5
5
1
DG0
6
5
1
DG0
7
5
1
DB7
8
5
1
DB7
9
5
1
DB6
0
6
1
DB6
1
6
1
DB5
2
6
1
S55 S56 S57 S58 S59 S60 DDDDDD S61 S62 S63 S64 S65 S66
333333
DB5
3
6
1
DB4
4
6
1
MMMMMM
MMMMMM
YYYYYY
UUUUUU
DB4
5
6
1
DB3
6
6
1
DB3
7
6
1
DB2
3 3 3333
8
6
1
DB2
9
6
1
DB1
0
7
1
DB1
1
7
1
DB0
2
7
1
DB0
3
7
1
DUMMY
4
7
1
DUMMY
5
7
1
DUMMY
6
7
1
………
DUMMY
7
7
1
DUMMY
8
7
1
TEST_OUT0
9
7
1
TEST_OUT1
0
8
1
TEST_OUT2
1
8
1
TEST_OUT3
2
8
1
TEST_OUT4
3
8
1
TEST_OUT5
4
8
1
TEST_OUT6
5
8
1
TEST_OUT7
6
8
1
TEST_IN0
7
8
1
TEST_IN1
8
8
1
TEST_IN2
9
8
1
DUMMY
0
9
1
DUMMY
1
9
1
DUMMY
2
9
1
DUMMY
3
9
1
DUMMY
4
9
1
DUMMY
5
9
1
DUMMY
6
9
1
DUMMY
7
9
1
DUMMY
8
9
1
DUMMY
9
9
1
DUMMY
0
0
2
DUMMY
1
0
2
DUMMY
2
0
2
DUMMY
3
0
2
DUMMY
4
0
2
DUMMY
5
0
2
DUMMY
6
0
2
DUMMY
7
0
2
DUMMY
8
0
2
DUMMY
9
0
2
DUMMY
0
1
2
DUMMY
1
1
2
DUMMY
2
1
2
DUMMY
3
1
2
DUMMY
4
1
2
DUMMY
5
1
2
DUMMY
6
1
2
AGND
7
1
2
AGND
8
1
2
AGND
9
1
2
AGND
0
2
2
AGND
1
2
2
AGND
2
2
2
AGND
3
2
2
AVCL
4
2
2
AVCL
5
2
2
AVCL
6
2
2
AVCL
7
2
2
AVCL
8
2
2
AVCL
9
2
2
DUMMY
0
3
2
DUMMY
1
3
2
DUMMY
2
3
2
DUMMY
3
3
2
DUMMY
4
3
2
DUMMY
5
3
2
DUMMY
6
3
2
DUMMY
7
3
2
DUMMY
8
3
2
DUMMY
9
3
2
DUMMY
0
4
2
DUMMY
1
4
2
AVDD
2
4
2
AVDD
3
4
2
AVDD
4
4
2
AVDD
5
4
2
AVDD
6
4
2
AVDD
7
4
2
AVDD
8
4
2
AVDD
9
4
2
PGND
0
5
2
PGND
1
5
2
PGND
2
5
2
PGND
3
5
2
PGND
4
5
2
PGND
5
5
2
PGND
6
5
2
4 DDDDDDSSSSSS
123456
PGND
7
5
2
DUMMY
8
5
2
MMMMMM
MMMMMM
YYYYYY
UUUUUU
DUMMY
9
5
2
DUMMY
0
6
2
2G
DUMMY
53 53 53 54 54 54
0G
1
6
2
8G
AVDD1
6G
2
6
2
4G
G
AVDD1
3
6
2
AVDD1
4
6
2
1
D
D
V
A
AVDD1
5
6
2
AVDD1
6
6
2
AVDD1
7
6
2
TESTOUT9
8
6
2
TESTOUT9
9
6
2
TESTOUT9
………
0
7
2
TESTOUT9
1
7
2
TESTOUT9
2
7
2
TESTOUT9
3
7
2
AVCL1
4
7
2
AVCL1
5
7
2
AVCL1
6
7
2
1
D
D
V
A
AVCL1
7
7
2
AVCL1
8
7
2
AVCL1
9
7
2
TESTOUT11
0
8
2
TESTOUT11
1
8
2
TESTOUT11
2
8
2
TESTOUT11
3
8
2
TESTOUT11
4
8
2
TESTOUT11
5
8
2
PVDD
6
8
2
PVDD
7
8
2
PVDD
8
8
2
PVDD
9
8
2
PVDD
0
9
2
PVDD
1
9
2
PVDD
2
9
2
PVDD
3
9
2
VGSP
4
9
2
VGSP
5
9
2
VGSP
6
9
2
VGSP
7
9
2
VGSP
8
9
2
VGSP
9
9
2
TESTOUT13
0
0
3
TESTOUT13
1
0
3
TESTOUT13
2
0
3
TESTOUT13
3
0
3
TESTOUT13
4
0
3
TESTOUT13
5
0
3
VGH
6
0
3
VGH
7
0
3
VGH
8
0
3
VGH
9
0
3
VGH
0
1
3
VGH
1
1
3
TESTOUT14
2
1
3
TESTOUT14
3
1
3
TESTOUT14
4
1
3
TESTOUT14
5
1
3
TESTOUT14
6
1
3
TESTOUT14
7
1
3
TESTOUT15
8
1
3
TESTOUT15
9
1
3
TESTOUT15
0
2
3
TESTOUT15
1
2
3
TESTOUT15
2
2
3
TESTOUT15
3
2
3
VGL
4
2
3
VGL
5
2
3
VGL
6
2
3
VGL
7
2
3
VGL
8
2
3
VGL
9
2
3
DUMMY
0
3
3
DDGGGG0G2G
246811
DUMMY
1
3
3
MM
MM
YY
UU
4. Block Diagram
S1~S720 GVCL GVDD G1~G544
Voltage
Voltage Reference
Reference
720
720 Source
Source Buffer
Buffer 544
544 Gate
Gate Buffer
Buffer
DAC
DAC Level
Level Shifter
Shifter
Gamma
Gamma Circuit
Circuit
Level
Level Shifter
Shifter
Gate
Gate Decoder
Decoder
Data
Data Latch
Latch Gamma
Gamma Table
Table
Data
Data Shift
Shift
Display
Display Control
Control Vcom
Vcom Generator
Generator VCOM
VPP NVM
NVM Instruction
Instruction Register
Register
Booster
Booster
Interface
Interface
A
S D LC R G B
C S S D D D
VSYNC
HSYNC
DE
DCLK
GRB
DISP
SYNC
PARA_SERI
VGL
VGH
GVCL
GVDD
VCC
PVDD
VDDI
VDD
[7 [7 [7
:0 :0 :0
] ] ]
5. Pin Description
SDA I Serial communication data input and output, Internal pull low.
Vertical scan direction control (Please refer to the register setting: VDIR)
VDIR (pin) = “Low”: The definition of VDIR register setting is inversion
from original.
VDIR (register) = “0”: Shift from up to down;
VDIR I
VDIR (register) = “1”: Shift from down to up. (Default)
VDIR (pin) = “High”: The definition of VDIR register setting is invariant.
VDIR (register) = “0”: Shift from down to up;
VDIR (register) = “1”: Shift from up to down. (Default)
Power Supply
Power input pin for NVM. When writing NVM, it needs external power
VPP P
supply voltage (7.5V). If not used, let this pin open.
AVCL1 P A power supply pin for generating Gamma reference voltage (Negative).
AVDD1 P A power supply pin for generating Gamma reference voltage (Positive).
Test Pin
TESTOUT9
TESTOUT11
TESTOUT14
TESTOUT15
TEST_IN[4:
I Test pins for internal testing only. Internal pull low.
0]
TEST_IN5 I Test pins for internal testing only. Internal pull high.
TESTOUT[0
O Digital test pins for internal testing only.
:7]
Note:
I: input, O: output, I/O: input/output, P: power input, G: GND
If unused pin don’t floating, the pin fix to VDDI or DGND.
CSX
SCL
SDA R/W A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
a. Each serial command consists of 17 bits of data which is loaded one bit a
time at the rising edge of serial clock SCL.
b. Command loading operation starts from the falling edge of CSX and is
completed at the next rising edge of CSX.
c. The serial control block is operational after power on reset, but commands
are established by the VSYNC signal. If command is transferred multiple times for
the same register, the last command before the VSYNC signal is valid.
d. If less than 16 bits of SCL are input while CS is low, the transferred data is
ignored.
e. If 16 bits or more of SCL are input while CS is low, the previous 16 bits of
transferred data before the rising edge of CS pulse are valid data.
f. Serial block operates with the SCL clock
g. Serial data can be accepted in the power save mode.
7. Register list
7.1. Register Summary
R/
ADDR D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT
W
0X04 W GLOBAL_CTR[7:0] 40H
0X05 W 0 SUB_RED_CTR[6:0] 40H
0X06 W 0 SUB_BLUE_CTR[6:0] 40H
0X07 W GLOBAL_BRT[7:0] 40H
0X08 W 0 SUB_RED_BRT[6:0] 40H
0X09 W 0 SUB_BLUE_BRT[6:0] 40H
OTP_ OTP_
OTP_A OTP_V OTP_
0X10 W 0 OTP_PTM[1:0] WR_E RD_E 00H
DDR[8] PP_SEL PROG
N N
0X11 W OTP_ADDR[7:0] 00H
0X12 W OTP_WR_DAT[7:0] 00H
0X13 R OTP_RD_DAT[7:0] -
AUT
SYNC_CTRL[1 PCLK
0X21 W 0 O_DE 0 HPOL VPOL 40H
:0] _POL
TECT
0X22 W HBP_PARA [7:0] 2BH
0X23 W HFP_PARA [7:0] 08H
0X24 W VBP_PARA [7:0] 0CH
0X25 W VFP_PARA [7:0] 08H
0X26 W HBP_SERI [7:0] 81H
0X27 W HFP_SERI [7:0] 18H
0X28 W VBP_SERI [7:0] 0CH
0X29 W VFP_SERI [7:0] 08H
AVDD_CLP_IBA AVCL_CLP_IB GAM_IBADJ[1:0 GAM_LDO_IB
0X30 W 55H
DJ[1:0] ADJ[1:0] ] ADJ[1:0]
GATE_IBADJ[1: SRC_IB
0X31 W VCC_VS[1:0] BIAS_ADJ[2:0] 50H
0] ADJ
OTP_S
LVD_
0X32 W LPOUT LVD_ADJ[1:0] 0 VDDS_TRIM[2:0] E3H
EN
_EN
0X38 W 0 GVCL_ADJ[6:0] 47H
0X39 W 0 GVDD_ADJ[6:0] 16H
0X3A W 0 VGSP_ADJ[6:0] 3FH
0X40 W GATE_SWITCH[7:0] 42H
0X41 W 0 0 0 0 GATE_POINT1[3:0] 03H
R/
ADDR D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT
W
PCHG
0X54 W 0 _BYP LD3N_ED[5:0] 0EH
ASS
AVDD_ AVCL
0X55 W FREQ_ _FRE AVCL_RATIO_ED1[5:0] CEH
EN Q_EN
0X56 W 0 0 0 AVDD_RATIO_ED1[4:0] 08H
0X57 W 0 0 AVDD_AVCL_FREQ_ED1[5:0] 0CH
AVCL_FREQ_
ST2/AVCL_RA
AVDD_FREQ_ST2/AVDD_RATIO_ST2[4:0]/
0X58 W 0 TIO_ST2 09H
P_PRECHG_2ND_ED[4:0]
P_PRECHG_2
ND_ST[1:0]
0X59 W SOURCE_IB[2:0] AVDD_RATIO_ED2[4:0] 66H
0X5A W SOURCE_IC[2:0] AVDD_AVCL_FREQ_ED2[4:0] 6AH
0X5B W CHOP_SEL[2:0] AVCL_RATIO_ED2[4:0] 0AH
0X5E W 0 0 PCHG_N_ED[5:0] 12H
0X60 W 0 0 GAM_VRP0[5:0] 00H
0X61 W 0 0 GAM_VRP1[5:0] 14H
0X62 W 0 0 GAM_VRP2[5:0] 19H
0X63 W 0 0 GAM_VRP3[5:0] 27H
0X64 W 0 0 GAM_VRP4[5:0] 28H
0X65 W 0 0 GAM_VRP5[5:0] 3DH
0X66 W 0 GAM_PRP0[6:0] 37H
0X67 W 0 GAM_PRP1[6:0] 4DH
0X68 W 0 0 0 GAM_PKP0[4:0] 0BH
0X69 W 0 0 0 GAM_PKP1[4:0] 16H
0X6A W 0 0 0 GAM_PKP2[4:0] 0CH
0X6B W 0 0 0 GAM_PKP3[4:0] 0DH
0X6C W 0 0 0 GAM_PKP4[4:0] 17H
0X6D W 0 0 0 GAM_PKP5[4:0] 04H
0X6E W 0 0 0 GAM_PKP6[4:0] 0FH
0X70 W 0 0 0 GAM_VRN0[5:0] 00H
0X71 W 0 0 0 GAM_VRN1[5:0] 14H
0X72 W 0 0 0 GAM_VRN2[5:0] 19H
0X73 W 0 0 0 GAM_VRN3[5:0] 27H
0X74 W 0 0 0 GAM_VRN4[5:0] 28H
0X75 W 0 0 0 GAM_VRN5[5:0] 3DH
0X76 W 0 0 GAM_PRN0[6:0] 37H
0X77 W 0 0 GAM_PRN1[6:0] 4DH
0X78 W 0 0 0 GAM_PKN0[4:0] 0BH
0X79 W 0 0 0 GAM_PKN1[4:0] 16H
0X7A W 0 0 0 GAM_PKN2[4:0] 0CH
0X7B W 0 0 0 GAM_PKN3[4:0] 0DH
0X7C W 0 0 0 GAM_PKN4[4:0] 17H
0X7D W 0 0 0 GAM_PKN5[4:0] 04H
0X7E W 0 0 0 GAM_PKN6[4:0] 0FH
0X80 W AVDD_ AVD AVDD_CLK_S 0 AVD AVDD_CLP_A E6H
R/
ADDR D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT
W
SS_EN D_RA EL[1:0] D_CL DJ[1:0]
TIO_S P_EN
EL
AVCL
AVCL
AVCL_ _RATI AVCL_CLK_S AVCL_CLP_A
0X81 W 0 _CLP E6H
SS_EN O_SE EL[3:0] DJ[1:0]
_EN
L
VGH_CLK_SEL[ VGH_RATIO_S VGH_C
0X82 W VGH_CLP_ADJ[2:0] 5DH
1:0] EL[1:0] LP_EN
VGL_CLK_SEL[ VGL_RATIO_S VGL_C
0X83 W VGL_CLP_ADJ[2:0] 5DH
1:0] EL[1:0] LP_EN
VGH_ VGL_
VGH_NON_TD VGL_NON_TD
0X84 W 0 SKIP_ 0 SKIP_ 66H
_SEL[1:0] _SEL[1:0]
SYNC SYNC
ESD_F AVDD_ AVCL
ESD_FUNC_S MV_CLK_SEL
0X85 W UNC_E 0 FDBK_ _FDB 3EH
EL[1:0] [1:0]
N EN K_EN
ABNOR
0XA0 W MAL_E 0 0 0 HDIR VDIR SBGR NBW 8EH
N
GATE_ SRC_
PXL_S CLR_
0XA1 W SWAP_ GATE_SWAP_SEL[2:0] 0 ODD_ 80H
WAP SEL
EN EVEN
PUMP
SERI_DB_SEL[
0XA2 W 0 0 0 _CTR 0 0 00H
1:0]
L_EN
0XDA R READ ID1 -
0XDB R READ ID2 -
0XDC R READ ID3 -
Note:
When GRB is low, all registers reset to default values.
All commands will be executed at next VSYNC.
7.2. Algorithm
Restriction -
Restriction -
LVD_EN Description
0 Disable LVD block
1 Enable LVD block
Restriction -
Restriction -
Restriction -
Restriction -
avdd_ratio_ed2: avdd pump ratio ending position for second half-line, the step is 16*pclk
Restriction -
avdd_avcl_freq_ed2[4:0]: Ending position for second half-line mv pump frequency switching, the
step is 16*pclk
Restriction -
avcl_ratio_ed2: avcl pump ratio ending positon for second half-line,step is 8*pclk
Restriction -
Restriction -
Restriction -
Restriction -
Restriction -
Restriction -
Restriction -
Restriction -
Restriction -
8. Electrical specifications
8.1 Absolute Maximum Ratings
Note: If one of the above items is exceeded its maximum limitation momentarily, the quality of the product may be
degraded. Absolute maximum limitation, therefore, specify the values exceeding which the product may be physically
8.2. DC Characteristics
8.3. AC Characteristics
Note: It is necessary to keep Tvbp =12, Tvfp = 8, Tvw = 4 and Thbp = 43, Thfp = 8 Thw = 4 in sync mode.
VSYNC
(VDPOL=0)
VSYNC
(VDPOL=1)
HSYNC
INPUT
DATA
GROUP
HSYNC
(HDPOL=0)
HSYNC
(HDPOL=1)
DCLK
DR[7:0]
DG[7:0]
DB[7:0]
NV3047
R R R R R R R R G G G G G G G G B B B B B B B B
D D D D D D D D D D D D D D D D D D D D D D D D
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
R R R R R R R R G G G G G G G G B B B B B B B B
D D D D D D D D D D D D D D D D D D D D D D D D
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
NV3047
R R R R R R R R G G G G G G G G B B B B B B B B
D D D D D D D D D D D D D D D D D D D D D D D D
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
R R R R R R G G G G G G B B B B B B
D D D D D D D D D D D D D D D D D D
5 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0
NV3047
R R R R R R R R G G G G G G G G B B B B B B B B
D D D D D D D D D D D D D D D D D D D D D D D D
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
R R R R R G G G G G G B B B B B
D D D D D D D D D D D D D D D D
4 3 2 1 0 5 4 3 2 1 0 4 3 2 1 0
NV3047
R R R R R R R R G G G G G G G G B B B B B B B B
D D D D D D D D D D D D D D D D D D D D D D D D
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
R R R R G G G G B B B B
D D D D D D D D D D D D
3 2 1 0 3 2 1 0 3 2 1 0
U1
U1
U1
2 DUMMY1 2 DUMMY1 2 DUMMY1
VCOM 3 VCOM VCOM 3 VCOM VCOM 3 VCOM
VCOM VCOM VCOM
NV3047D
NV3047D
NV3047D
VGL 4 VGL 4 VGL 4
CS
CS
CS
5 O_C 5 O_C 5 O_C
SCL
SCL
SCL
VCOM VCOM VCOM
SDA
SDA
SDA
GND2
VCOM VCOM VCOM
GND2
GND2
DGND 6 DGND 6 DGND 6
7 DGND 7 DGND 7 DGND
8 DUMMY2 8 DUMMY2 8 DUMMY2
VPP 9 VPP VPP 9 VPP VPP 9 VPP
10 VPP 10 VPP 10 VPP
DGND 11 VPP DGND 11 VPP DGND 11 VPP
12 DGND 12 DGND 12 DGND
CS
CS
CS
13 GVDD 13 GVDD 13 GVDD
SCL
SCL
SCL
GVDD GVDD GVDD
SDA
SDA
SDA
14 GVDD 14 GVDD 14 GVDD
15 GVDD 15 GVDD 15 GVDD
GVCL 16 GVCL GVCL 16 GVCL GVCL 16 GVCL
17 GVCL 17 GVCL 17 GVCL
18 GVCL 18 GVCL 18 GVCL
VCOM 19 VCOM VCOM 19 VCOM VCOM 19 VCOM
20 VCOM 20 VCOM 20 VCOM
DGND 21 VCOM DGND 21 VCOM DGND 21 VCOM
22 DGND 22 DGND 22 DGND
DGND 23 DUMMY3 DGND 23 DUMMY3 DGND 23 DUMMY3
24 DGND 24 DGND 24 DGND
25 DUMMY4 25 DUMMY4 25 DUMMY4
26 DUMMY5 26 DUMMY5 26 DUMMY5
27 DGND+PGND 27 DGND+PGND 27 DGND+PGND
28 DGND+PGND 28 DGND+PGND 28 DGND+PGND
DGND+PGND 29 DGND+PGND DGND+PGND 29 DGND+PGND DGND+PGND 29 DGND+PGND
30 DGND+PGND 30 DGND+PGND 30 DGND+PGND
VCC 31 VCC VCC 31 VCC VCC 31 VCC
32 VCC 32 VCC 32 VCC
VDD
VDD
VDD
33 VCC 33 VCC 33 VCC
VDDI 34 VDDI VDDI 34 VDDI VDDI 34 VDDI
35 VDDI 35 VDDI 35 VDDI
VDDI
VDDI
VDDI
36 VDDI 36 VDDI 36 VDDI
PVDD+VDD 37 PVDD+VDD PVDD+VDD 37 PVDD+VDD PVDD+VDD 37 PVDD+VDD
38 PVDD+VDD 38 PVDD+VDD 38 PVDD+VDD
PVDD+VDD
PVDD+VDD
PVDD+VDD
39 PVDD+VDD 39 PVDD+VDD 39 PVDD+VDD
VSYNC 40 PVDD+VDD VSYNC 40 PVDD+VDD VSYNC 40 PVDD+VDD
HSYNC 41 VSYNC HSYNC 41 VSYNC HSYNC 41 VSYNC
DCLK 42 HSYNC DCLK 42 HSYNC DCLK 42 HSYNC
43 DCLK 43 DCLK 43 DCLK
44 VDPOL 44 VDPOL 44 VDPOL
45 HDPOL 45 HDPOL 45 HDPOL
46 DCLKPOL 46 DCLKPOL 46 DCLKPOL
DE 47 SBGR DE 47 SBGR DE 47 SBGR
48 DE 48 DE 48 DE
49 DUMMY6 49 DUMMY6 49 DUMMY6
PARA_SERI 50 DUMMY7 PARA_SERI 50 DUMMY7 PARA_SERI 50 DUMMY7
51 PARA_SERI 51 PARA_SERI 51 PARA_SERI
52 EXTC HDIR 52 EXTC HDIR 52 EXTC
53 HDIR VDIR 53 HDIR VDIR 53 HDIR
54 VDIR 54 VDIR 54 VDIR
55 TEST_IN3 55 TEST_IN3 55 TEST_IN3
CS 56 TEST_IN4 CS 56 TEST_IN4 CS 56 TEST_IN4
SDA 57 CS SDA 57 CS SDA 57 CS
SCL 58 SDA SCL 58 SDA SCL 58 SDA
DISP 59 SCL DISP 59 SCL DISP 59 SCL
60 DISP 60 DISP 60 DISP
61 TEST_IN5 61 TEST_IN5 61 TEST_IN5
62 GRB 62 GRB 62 GRB
63 SYNC 63 SYNC 63 SYNC
64 DUMMY8 64 DUMMY8 64 DUMMY8
DGND 65 DUMMY9 DGND 65 DUMMY9 DGND 65 DUMMY9
DR7 66 DGND DR7 66 DGND DR7 66 DGND
DR6 67 DR7 DR6 67 DR7 DR6 67 DR7
DR5 68 DR6 DR5 68 DR6 DR5 68 DR6
DR5 DR5 DR5
11. FPC Application circuit
FPC1 FPC
FPC1 FPC
FPC1 FPC
DB7 29 DGND VGH 137 VGH DB7 29 DGND VGH 137 VGH DB7 29 DGND VGH 137 VGH
DGND 30 DCLK 138 VGH DGND 30 DCLK 138 VGH DGND 30 DCLK 138 VGH
DCLK 31 DISP 139 VGH DCLK 31 DISP 139 VGH DCLK 31 DISP 139 VGH
DISP 32 140 TESTOUT14 DISP 32 HSYNC 140 TESTOUT14 DISP 32 HSYNC 140 TESTOUT14
HSYNC 33 141 TESTOUT14 HSYNC 33 VSYNC 141 TESTOUT14 HSYNC 33 VSYNC 141 TESTOUT14
VSYNC 34 DE 142 TESTOUT14 VSYNC 34 142 TESTOUT14 VSYNC 34 DE 142 TESTOUT14
DE 35 143 TESTOUT15 DE 35 143 TESTOUT15 DE 35 143 TESTOUT15
NC 36 DGND 144 TESTOUT15 NC 36 DGND 144 TESTOUT15 NC 36 DGND 144 TESTOUT15
DGND 37 XR 145 TESTOUT15 DGND 37 XR 145 TESTOUT15 DGND 37 XR 145 TESTOUT15
XR 38 YD VGL 146 VGL XR 38 YD VGL 146 VGL XR 38 YD VGL 146 VGL
YD 39 XL 147 VGL YD 39 XL 147 VGL YD 39 XL 147 VGL
XL 40 YU 148 VGL XL 40 YU 148 VGL XL 40 YU 148 VGL
YU DUMMY19 YU DUMMY19 YU DUMMY19
90
VCOM 149 VCOM 149 VCOM 149
150 VCOM 150 VCOM 150 VCOM
VGL 151 C_E VGL 151 C_E VGL 151 C_E
VCOM 152 SW VCOM 152 SW VCOM 152 SW
VCOM VCOM VCOM
1 1 1
U2
U2
U2
2 DUMMY1 2 DUMMY1 2 DUMMY1
VCOM 3 VCOM VCOM 3 VCOM VCOM 3 VCOM
VCOM VCOM VCOM
NV3047D
NV3047D
NV3047D
VGL 4 VGL 4 VGL 4
5 O_C 5 O_C 5 O_C
CS1
CS1
CS1
VCOM VCOM VCOM
SCL1
SCL1
SCL1
SDA1
SDA1
SDA1
VCOM VCOM VCOM
GND3
GND3
GND3
DGND 6 DGND 6 DGND 6
7 DGND 7 DGND 7 DGND
8 DUMMY2 8 DUMMY2 8 DUMMY2
VPP 9 VPP VPP 9 VPP VPP 9 VPP
10 VPP 10 VPP 10 VPP
DGND 11 VPP DGND 11 VPP DGND 11 VPP
12 DGND 12 DGND 12 DGND
CS
CS
CS
13 GVDD 13 GVDD 13 GVDD
SCL
SCL
SCL
GVDD
SDA
GVDD
SDA
GVDD
SDA
14 GVDD 14 GVDD 14 GVDD
15 GVDD 15 GVDD 15 GVDD
GVCL 16 GVCL GVCL 16 GVCL GVCL 16 GVCL
17 GVCL 17 GVCL 17 GVCL
18 GVCL 18 GVCL 18 GVCL
VCOM 19 VCOM VCOM 19 VCOM VCOM 19 VCOM
20 VCOM 20 VCOM 20 VCOM
DGND 21 VCOM DGND 21 VCOM DGND 21 VCOM
22 DGND 22 DGND 22 DGND
DGND 23 DUMMY3 DGND 23 DUMMY3 DGND 23 DUMMY3
24 DGND 24 DGND 24 DGND
25 DUMMY4 25 DUMMY4 25 DUMMY4
26 DUMMY5 26 DUMMY5 26 DUMMY5
27 DGND+PGND 27 DGND+PGND 27 DGND+PGND
28 DGND+PGND 28 DGND+PGND 28 DGND+PGND
DGND+PGND 29 DGND+PGND DGND+PGND 29 DGND+PGND DGND+PGND 29 DGND+PGND
30 DGND+PGND 30 DGND+PGND 30 DGND+PGND
VCC 31 VCC VCC 31 VCC VCC 31 VCC
32 VCC 32 VCC 32 VCC
VDD
VDD
VDD
33 VCC 33 VCC 33 VCC
VDDI 34 VDDI VDDI 34 VDDI VDDI 34 VDDI
35 VDDI 35 VDDI 35 VDDI
VDDI
VDDI
VDDI
36 VDDI 36 VDDI 36 VDDI
PVDD+VDD 37 PVDD+VDD PVDD+VDD 37 PVDD+VDD PVDD+VDD 37 PVDD+VDD
38 PVDD+VDD 38 PVDD+VDD 38 PVDD+VDD
PVDD+VDD
PVDD+VDD
PVDD+VDD
39 PVDD+VDD 39 PVDD+VDD 39 PVDD+VDD
VSYNC 40 PVDD+VDD VSYNC 40 PVDD+VDD VSYNC 40 PVDD+VDD
HSYNC 41 VSYNC HSYNC 41 VSYNC HSYNC 41 VSYNC
DCLK 42 HSYNC DCLK 42 HSYNC DCLK 42 HSYNC
43 DCLK 43 DCLK 43 DCLK
44 VDPOL 44 VDPOL 44 VDPOL
45 HDPOL 45 HDPOL 45 HDPOL
46 DCLKPOL 46 DCLKPOL 46 DCLKPOL
DE 47 SBGR DE 47 SBGR DE 47 SBGR
48 DE 48 DE 48 DE
49 DUMMY6 49 DUMMY6 49 DUMMY6
PARA_SERI 50 DUMMY7 PARA_SERI 50 DUMMY7 PARA_SERI 50 DUMMY7
51 PARA_SERI 51 PARA_SERI 51 PARA_SERI
52 EXTC 52 EXTC 52 EXTC
53 HDIR 53 HDIR 53 HDIR
54 VDIR 54 VDIR 54 VDIR
55 TEST_IN3 55 TEST_IN3 55 TEST_IN3
CS 56 TEST_IN4 CS 56 TEST_IN4 CS 56 TEST_IN4
SDA 57 CS SDA 57 CS SDA 57 CS
SCL 58 SDA SCL 58 SDA SCL 58 SDA
DISP 59 SCL DISP 59 SCL DISP 59 SCL
60 DISP 60 DISP 60 DISP
61 TEST_IN5 61 TEST_IN5 61 TEST_IN5
62 GRB 62 GRB 62 GRB
63 SYNC 63 SYNC 63 SYNC
64 DUMMY8 64 DUMMY8 64 DUMMY8
DGND 65 DUMMY9 DGND 65 DUMMY9 DGND 65 DUMMY9
DR7 66 DGND DR7 66 DGND DR7 66 DGND
DR6 67 DR7 DR6 67 DR7 DR6 67 DR7
DR5 68 DR6 DR5 68 DR6 DR5 68 DR6
DR4 69 DR5 DR4 69 DR5 DR4 69 DR5
DR3 70 DR4 DR3 70 DR4 DR3 70 DR4
DR2 71 DR3 DR2 71 DR3 DR2 71 DR3
DR1 72 DR2 DR1 72 DR2 DR1 72 DR2
DR0 73 DR1 DR0 73 DR1 DR0 73 DR1
DG7 74 DR0 DG7 74 DR0 DG7 74 DR0
DG6 75 DG7 DG6 75 DG7 DG6 75 DG7
DG5 76 DG6 DG5 76 DG6 DG5 76 DG6
DG4 77 DG5 DG4 77 DG5 DG4 77 DG5
DG3 78 DG4 DG3 78 DG4 DG3 78 DG4
DG2 79 DG3 DG2 79 DG3 DG2 79 DG3
DG1 80 DG2 DG1 80 DG2 DG1 80 DG2
DG0 81 DG1 DG0 81 DG1 DG0 81 DG1
DB7 82 DG0 DB7 82 DG0 DB7 82 DG0
DB6 83 DB7 DB6 83 DB7 DB6 83 DB7
DB5 84 DB6 DB5 84 DB6 DB5 84 DB6
DB4 85 DB5 DB4 85 DB5 DB4 85 DB5
DB3 86 DB4 DB3 86 DB4 DB3 86 DB4
DB2 87 DB3 DB2 87 DB3 DB2 87 DB3
DB1 88 DB2 DB1 88 DB2 DB1 88 DB2
DB0 89 DB1 DB0 89 DB1 DB0 89 DB1
90 DB0 90 DB0 90 DB0
91 DUMMY10 91 DUMMY10 91 DUMMY10
92 DUMMY11 92 DUMMY11 92 DUMMY11
93 DUMMY12 93 DUMMY12 93 DUMMY12
94 AGND 94 AGND 94 AGND
AGND 95 AGND AGND 95 AGND AGND 95 AGND
FPC2 FPC
FPC2 FPC
FPC2 FPC
5 DR0 113 5 DR0 113 5 DR0 113
DR0 6 DR1 114 PGND DR0 6 DR1 114 PGND DR0 6 DR1 114 PGND
DR1 7 DR2 AVDD1 115 AVDD1 DR1 7 DR2 AVDD1 115 AVDD1 DR1 7 DR2 AVDD1 115 AVDD1
DR2 8 DR3 116 AVDD1 DR2 8 DR3 116 AVDD1 DR2 8 DR3 116 AVDD1
DR3 9 DR4 117 AVDD1 DR3 9 DR4 117 AVDD1 DR3 9 DR4 117 AVDD1
DR4 10 DR5 118 TESTOUT9 DR4 10 DR5 118 TESTOUT9 DR4 10 DR5 118 TESTOUT9
DR5 11 DR6 119 TESTOUT9 DR5 11 DR6 119 TESTOUT9 DR5 11 DR6 119 TESTOUT9
DR6 12 DR7 120 TESTOUT9 DR6 12 DR7 120 TESTOUT9 DR6 12 DR7 120 TESTOUT9
DR7 13 DG0 AVCL1 121 AVCL1 DR7 13 DG0 AVCL1 121 AVCL1 DR7 13 DG0 AVCL1 121 AVCL1
DG0 14 DG1 122 AVCL1 DG0 14 DG1 122 AVCL1 DG0 14 DG1 122 AVCL1
DG1 15 DG2 123 AVCL1 DG1 15 DG2 123 AVCL1 DG1 15 DG2 123 AVCL1
DG2 16 DG3 124 TESTOUT11 DG2 16 DG3 124 TESTOUT11 DG2 16 DG3 124 TESTOUT11
DG3 17 DG4 125 TESTOUT11 DG3 17 DG4 125 TESTOUT11 DG3 17 DG4 125 TESTOUT11
DG4 18 DG5 126 TESTOUT11 DG4 18 DG5 126 TESTOUT11 DG4 18 DG5 126 TESTOUT11
DG5 19 DG6 127 PVDD DG5 19 DG6 127 PVDD DG5 19 DG6 127 PVDD
DG6 20 DG7 PVDD 128 PVDD DG6 20 DG7 PVDD 128 PVDD DG6 20 DG7 PVDD 128 PVDD
DG7 21 DB0 129 PVDD DG7 21 DB0 129 PVDD DG7 21 DB0 129 PVDD
DB0 22 DB1 130 PVDD DB0 22 DB1 130 PVDD DB0 22 DB1 130 PVDD
DB1 23 DB2 VGSP 131 VGSP DB1 23 DB2 VGSP 131 VGSP DB1 23 DB2 VGSP 131 VGSP
DB2 24 DB3 132 VGSP DB2 24 DB3 132 VGSP DB2 24 DB3 132 VGSP
DB3 25 DB4 133 VGSP DB3 25 DB4 133 VGSP DB3 25 DB4 133 VGSP
DB4 26 DB5 134 TESTOUT13 DB4 26 DB5 134 TESTOUT13 DB4 26 DB5 134 TESTOUT13
DB5 27 DB6 135 TESTOUT13 DB5 27 DB6 135 TESTOUT13 DB5 27 DB6 135 TESTOUT13
DB6 28 DB7 136 TESTOUT13 DB6 28 DB7 136 TESTOUT13 DB6 28 DB7 136 TESTOUT13
NV3047D—480(RGB) x272 TFT LCD Single-Chip Driver
DB7 29 DGND VGH 137 VGH DB7 29 DGND VGH 137 VGH DB7 29 DGND VGH 137 VGH
DGND 30 DCLK 138 VGH DGND 30 DCLK 138 VGH DGND 30 DCLK 138 VGH
DCLK 31 DISP 139 VGH DCLK 31 DISP 139 VGH DCLK 31 DISP 139 VGH
DISP 32 140 TESTOUT14 DISP 32 HSYNC 140 TESTOUT14 DISP 32 HSYNC 140 TESTOUT14
HSYNC 33 141 TESTOUT14 HSYNC 33 VSYNC 141 TESTOUT14 HSYNC 33 VSYNC 141 TESTOUT14
VSYNC 34 DE 142 TESTOUT14 VSYNC 34 142 TESTOUT14 VSYNC 34 DE 142 TESTOUT14
DE 35 143 TESTOUT15 DE 35 143 TESTOUT15 DE 35 143 TESTOUT15
NC 36 DGND 144 TESTOUT15 NC 36 DGND 144 TESTOUT15 NC 36 DGND 144 TESTOUT15
DGND 37 XR 145 TESTOUT15 DGND 37 XR 145 TESTOUT15 DGND 37 XR 145 TESTOUT15
XR 38 YD VGL 146 VGL XR 38 YD VGL 146 VGL XR 38 YD VGL 146 VGL
YD 39 XL 147 VGL YD 39 XL 147 VGL YD 39 XL 147 VGL
XL 40 YU 148 VGL XL 40 YU 148 VGL XL 40 YU 148 VGL
YU DUMMY19 YU DUMMY19 YU DUMMY19
91
VCOM 149 VCOM 149 VCOM 149
150 VCOM 150 VCOM 150 VCOM
VGL 151 C_E VGL 151 C_E VGL 151 C_E
VCOM 152 SW VCOM 152 SW VCOM 152 SW
VCOM VCOM VCOM
NV3047D—480(RGB) x272 TFT LCD Single-Chip Driver
VDD,VDDI,
PVDD T0 T1
VSYNC
T4
DE
STB
VGL
T2 T3
AVDD
AVCL
T5
VGH
VCOM Output=0V
VLED
VDD,VDDI,
PVDD
VSYNC
DE
DISP
(Standby)
VGL
AVDD
AVCL
VGH
VCOM Output=0V
VLED
Wait at
least 100us
Set register
FFH = 0xA5
Continue Yes
Writing OTP ?
No
Finish
Step 3: Check the image quality of display module. If flicker can be still observed
on the panel, repeat the command 40h until the flicker disappearance.
Step 4: Read Optimization VCOM Value
Function W/R CMD Par Note
Read Optimization
R 40 VMF=Read(0x40);
VMF
Waiting 100ms
Step 11: Turn off VDD and VDDI, waiting for 200ms then and turn on again.
Step 12: Execute normal display on sequence.
Function W/R CMD Par Note
HW reset
HW reset sequence
Waiting 100ms
Display On LCD Refer Power On
Module Sequence
Recommend Flicker
Display Check Pattern
Pattern